Wafer Level Reliability Test Research Articles

A Novel Evaluation Methodology for the Reliability and Lifetime of 200 mm E-Mode GaN-on-Si Power HEMTs

In this paper, a novel evaluation methodology for the reliability and lifetime of E-mode AlGaN/GaN HEMTs has been proposed. A practical example of reliability evaluation is presented for commercial 100V E-mode GaN-on-Si power HEMTs, which are fabricated on an industrial 200mm Si CMOS compatible technology platform. Firstly, wafer-level reliability test (WLRT), Joint Electron Device Engineering Council (JEDEC) qualification and dynamic high temperature operating life (DHTOL) test of 200mm GaN-on-Si power HEMTs for mass production have been carried out. Secondly, the relationships of WLRT with JEDEC and DHTOL have been found, therefore, a fast evaluation method for the reliability of commercial 100V E-mode GaN-on-Si power devices has been established. Finally, DHTOL and switching accelerated lifetime test (SALT) have been carried out to demonstrate the validity of the fast evaluation method. In summary, it is proved that the novel evaluation methodology can better screen the robust GaN power devices, and greatly simplify the reliability testing flow of commercial 200mm GaN-on-Si power devices for mass production.

Sub-100 nm2 Cobalt Interconnects

Co has elicited a strong interest to replace Cu for future interconnect applications in microelectronic circuits due to its potentially lower resistivity and better reliability at scaled dimensions. Here, we demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique. Semiclassical resistivity modeling of the wire resistivity indicates that grain boundary scattering is the dominant contribution for cross-sectional areas of the order of 100 nm2, while the contribution of surface scattering increases drastically below 50 nm2. Furthermore, wafer-level reliability tests of the Co wires show the high fusing current densities and a strong resistance to thermoelectric stress demonstrating the potential for robust reliability. The resistivity and the reliability of the Co wires are comparable with those of Ru wires.

Lead-Free Solder Material and Chip Thickness Impact on Board-Level Reliability for Low-K WLCSP

This paper evaluates the effect of the solder ball material and chip thickness on board-level reliability using low-K wafer-level chip-scale packaging (WLCSP). The composition of the three evaluated solder ball materials includes SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> , SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> , and SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2.6</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> . The chip thickness is ranging from 200, 300, and 775 ¿m. Initially, the high temperature storage and ten-time multiple reflow tests were used as the wafer-level reliability test items. The work uses both the low speed (500 ¿m/s) and the high speed (200 mm/s and 1 m/s) solder ball shear test to compare the shear force, displacement, and fracture energy of the three solder compositions. The high speed shear test result shows the high silver content correlates to small displacement and the low fracture energy. Next, the finite element model was employed to compare the board level chip and solder ball stress for these three different chip thicknesses. The finite element method simulation results indicate the thinner chip implies the preferred thermal fatigue cycles. In addition, the drop test results show the chip thickness of 200 and 300 ¿m improve the drop test performance (81 drops and 88 drops) by 20.9%-31.34% than that of chip thickness of 775 ¿m. Moreover, the chip thickness of 200 and 300 ¿m substantially enhance the thermal fatigue life (665 cycles and 655 cycles) by 81.44%-84.21% than that of chip thickness of 775 ¿m using the SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> . Notably, the experimental results correlate well with the simulation trend. This work provides a design guideline for selecting the favorable solder materials and the chip thickness to obtain the satisfactory board-level reliability of the low-K WLCSP packaging.

A Versatile, Via Terminated Electromigration Test Structure for Various Stress Modes Used During Fast Wafer Level Reliability (fWLR) Testing

A multipurpose electromigration (EM) test structure designed for advanced fast wafer level reliability (WLR) tests is described in this work. It is shown that different failure location and failure modes can be detected electrically by this test structures which is beneficial for early technology development as well as productive in-line monitoring. Highly accelerated WLR tests use the metal self-heating effect for temperature stress acceleration. It is shown here that the design of interconnects with respect to the critical metal line and the periphery of the tested metal line has a large impact on the stress temperature. A carefully designed test structure guarantees the ability to test for different EM failure modes (upstream, downstream). The presented experimental data focuses on the investigation of different process splits.

A cost-effective wafer-level reliability test system for integrated circuit makers

Wafer-level reliability (WLR) testing receives much attention and becomes a major tool for process reliability qualification and in-line monitoring because WLR can provide real-time results for timely improvements. This in-situ test capability is greatly attributed to an automatic parametric tester for sample handling and data collection/analysis. This paper presents a cost-effective WLR test system for a semiconductor maker (an IDM as well as a foundry). The proposed system consists of flexible and extensible algorithm generation, which helps realize low-cost WLR solutions. The key features of our proposed system include cost-effective instrumentation (i.e., an Agilent 4156C parameter analyzer, a semi-auto, and thermal CASCADE 12751 wafer prober, a pulse generator, and a switching matrix) and the software for interface control and data analysis. Compared with the corresponding automatic test equipment (ATE), our system is capable of measuring electrical characteristics with higher accuracy and a wider temperature range. This leads to significant cost saving, much enhanced tool utilization, and improved flexibility. Its great extensibility is especially important for a wafer foundry, which often suffers test capacity shortage when numerous verifications and qualifications are to be done.

Some practical concerns on isothermal electromigration tests

The isothermal electromigration (EM) test at wafer level can greatly reduce the test time from months to minutes. This plausible feature makes inline reliability monitoring a promising approach to enhance product reliability. Although most wafer-level reliability (WLR) tests are applied for process monitors and comparisons, their applicability for qualification will be justified. The correlation between package-level reliability (PLR) and the isothermal EM is necessary and is discussed in this paper. Besides failure analysis, a 95% confidence interval of activation energy is constructed. Since the sizes of voids formed at isothermal EM are much smaller than those at PLR EM tests, the failure criterion should be changed (i.e., using a smaller OR). Issues for better test structure designs are described and verified. Generally, the straight-line test structure with four pads is recommended for the isothermal EM tests because of the uniform temperature profile. An extensive example is provided to illustrate the procedures on isothermal EM tests for WLR control. In the example, we propose using t/sub 50/ for routine Cpk review and the slope of the fitting line to monitor the degradation. The spec limits can be obtained based on customers' or internal reliability goals.

A Reliability Statistics Perspective on the Pitfalls of Standard Wafer-Level Electromigration Accelerated Test (SWEAT)

Standard Wafer Level Electromigration Accelerated Test (SWEAT) has become a common fast wafer level reliability test for electromigration in industry. However, its ability to detect changes in processes and its correlation with conventional electromigration test result has come under close scrutiny. From the perspective of reliability statistics, SWEAT also has other pitfalls that render its test results questionable. In this work, these pitfalls are highlighted, and alternative wafer-level electromigration tests are discussed. The arguments that the SWEAT is not appropriate for evaluation of electromigration of metal lines are presented. SWEAT as a tool to evaluate electromigration lifetime of metal lines is not recommended unless the pitfalls are seriously looked at.

Electromigration characterization of damascene copper interconnects using normally and highly accelerated tests

We have completed a set of experiments on damascene Chemical Vapor Deposition Copper (CVD-Cu) interconnects using Wafer Level and Package Level Reliability (WLR and PLR) tests. Two line widths have been extensively characterized : w=4 and 0.6 μm. For both line widths, the activation energy values extracted using WLR and PLR data are good in agreement demonstrating that the active diffusion paths remain the same over the wide range of used measurement conditions : Ea=0.65eV for w = 4μm, Ea = 0.7-0.8eV for w = 0.6μm. spite of Ea experimental values lower than the reference values of the literature.

Electromigration Characterization Versus Texture Analysis in Damascene Copper Interconnects

AbstractWe have studied the effect of texture (X-ray diffraction pole figures) and grain morphology (Focus Ion Beam cross-sections) on the electromigration performances of copper damascene interconnects. Three different metallizations have been characterized : Chemical Vapor Deposition copper deposited on TiN (process A) and electroplated copper deposited either on Ta (process B) or TaN (process C). The reliability performance of these interconnects has been evaluated using both Wafer Level Reliability (WLR) and Package Level Reliability (PLR) tests on 4 and 0.6 νm wide lines using single metal level test structures. On the basis of the activation energy values and failure analysis observations, we concluded that interfacial diffusion plays a key role in the electromigration phenomenon for processes B and C whereas grain boundaries seem to be the active diffusion path for process A. The existence of several failure mechanisms during electromigration tests (interfacial or grain boundary diffusions), the impact of the damascene architecture on microstructure (sidewall textures and non columnar grain shapes) and the copper propensity for twinning seem to mask the impact of texture on the electromigration reliability of copper damascene interconnects.

Wafer level reliability: Process control for reliability

Wafer Level Reliability test techniques can be used to provide fast feedback process control information regarding the reliability of the product of a semiconductor process. The purpose of wafer level reliability (WLR) tests is the measurement of variation in the materials comprising the semiconductor device. They are not intended as modeling tools for the quantification of the effect of stress on these materials. As such, WLR tests must provide a repeatable stress, independent of normal process variation. The results of these tests will be a measurement of the “rate of degradation” of the basic circuit elements caused by a standard stress.

The Effect of Post W-Etchback Cleaning Treatments and Implementation of Refractory Metal Buffer Layers on the Electromigration Performance of TiN/AlCu/TiN/Ti Metallization Systems

AbstractTiN/Ti films employed as glue layers for a blanket/etchback W plug technology show a significant surface contamination after the W-etchback process. An Al film deposited directly on a contaminated TiN/Ti underlayer exhibits a very weak texture, increasing the susceptibility to electromigration. Reliability tests confirm that the electromigration performance of a TiN/AlCu/TiN/Ti metallization system with a W plug technology, is significantly inferior to interconnecs that do not employ this plug technology. To improve the electromigration performance of this metallization system, several TiN surface cleaning treatments were evaluated. Also, the impact of the implementation of refractory metal buffer layers, before Al deposition was investigated. Analysis was performed by means of several surface analysis techniques, Al texture measurements and wafer-level reliability tests. It has been demonstrated that the contamination needs to be removed completely, or to be covered by a refractory buffer layer in order to restore the Al texture and to recover the proper electromigration resistance.

Electrical noise and VLSI interconnect reliability

This paper discusses the characteristics of noise sources in Al-based thin films and their relationships to VLSI reliability. Techniques of applying noise measurements in detecting existing defects/damages in the films, determining electromigration activation energy, and predicting the time to failure of VLSI interconnects are presented. The noise measurement technique can be applied to wafer-level reliability testing because it is much faster than the conventional MTF method and is nondestructive in nature. Some important considerations for wafer-level reliability testing via noise measurements are also presented in this paper.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effects of Line Width, Thickness and Alloy Temperature on the Breakdown Energy of thin Aluminum Lines

ABSTRACTReliability issues have assumed greater importance as critical dimensions in microelectronic devices have entered the sub-micron regime. Wafer level reliability tests have been performed to study the breakdown energy of aluminum. 1500Å, 3500Å, 5500Å aluminum films were sputter deposited at 400 °C on oxide-on-silicon substrates. Test structures with line widths varying from 1 μm to 10 μm were defined on the metal film. The aluminum lines were then passivated using a stacked layer of silicon dioxide and silicon nitride. Finally, the substrates were alloyed at temperatures from 400°C to 450 °C. An attempt has been made to minimize process variability effects by processing the substrates through the same process conditions as far as possible. Failure was induced by stressing the metal lines with high DC current densities and at a constant slew rate. The samples were characterized using optical and scanning electron microscopy. Failure analysis of the samples processed under the different conditions will be discussed.