Wafer Grinding Research Articles

Test Methods for Silicon Die Strength

Recently, the 3D or stacked-die packages become increasingly popular for packaging ICs into a system or subsystem to satisfy the needs of low cost, small form factor, and high performance. For the applications of these packages, IC silicon wafers have to be ground to be relatively thin through the wafer-thinning processes (such as grinding, polishing, and plasma etching). The strength of dies has to be determined for the design requirement and reliability assurance of the packages. From the published data, there still exist some issues, including a large scatter existed in die strength data and difficulties in differentiating the causes of the low strength between from the wafer grinding and from wafer sawing by either the three-point bending or four-point bending test. The purposes of this study are to develop new, reliable, and simple test methods for determination of die strength, in order to improve the data scatter, and to provide a solution for differentiating the factors that affect the variability of die strength for finding out the causes of the weakness of the die strength. In this study, two new test methods, point-loaded circular plate with simple supports test (PLT-I) and point-loaded plate on elastic foundation test (PLT-II), are proposed and then evaluated by testing two groups of silicon dies with different surface conditions. The surface conditions (roughness) of the specimens are determined by atomic force microscopy and correlated to failure strength. The failure forces from both tests have to be modified by using maximum stress obtained from theories or finite element analyses to obtain the failure strength. The test results are compared to each other and further with a widely used four-point bending test. The results suggest that, unlike the four-point bending test suffering the chipping effect, both methods provide very consistent data with a small scatter for each group of specimens and can be used for identifying the effect of surface grinding (roughness) on the die strength. It is also shown that the die strength is highly dependent on the surface roughness. Accordingly, these two methods can provide not only a (biaxial) stress field similar to temperature-loaded die in the packages, but also simple, feasible, reliable, and chipping-free tests for silicon dies of dummy or real IC chips, without strict geometrical limitation, such as beam-type geometry for the three-point or four-point bending test.

A Fundamental Modeling Approach for Nano-Grinding of Silicon Wafers

The advantages of ductile regime grinding of silicon wafer such as smooth surface roughness (Ra < 10 nm) and minimum subsurface damage layer (< 10μm) have great impact on the production process of wafer. With ductile regime grinding, the subsequent processes such as etching and rough polishing processes can be minimized. To achieve ductile regime grinding, a fundamental concept is the application of grain depth of cut being less than the critical cut depth, dc, of the silicon wafer. However, dc is dependent on material properties, cutting conditions, and crystallographic orientation [1].The objective of this paper is to derive, and to investigate by experiment, the dc value for silicon wafer grinding. Following these key steps, the effects of dc on various major grinding parameters are studied.

Materials Aspects to Consider in the Fabrication of Through-Silicon Vias

ABSTRACTThe formation of vertical interconnects to create three-dimensional (3D) interconnects enables integration of dissimilar electronic material technologies. These vertical interconnects are metal filled blind vias etched in silicon and are formed by a series of processing steps that include: silicon etch; insulation/barrier/seed layer deposition; electroplating of Cu to fill the via; wafer grinding and thinning; and back side processing to form contacts. Deep reactive ion etching (DRIE) is used to etch silicon vias with attention given to process parameters that affect sidewall angle, sidewall roughness, and lateral etch growth at the top of the via. After etching, vias are insulated by depositing 0.5 μm of silicon dioxide by plasma enhanced chemical vapor deposition (PECVD) at 325°C. A barrier film of TaN is reactively sputtered after insulation deposition followed by a Cu sputtered seed film allowing electroplated Cu to fill the blind via. Reverse pulse plating is used to achieve bottom-up filling of the via. Once void-free electroplated vias are prepared, the process wafer is attached to a carrier wafer for silicon back grinding. Vias on the process wafer are “exposed” from the back side of the wafer with a combination of processes that include mechanical grinding, polishing, and reactive ion etching (RIE). Contact pads are then formed by conventional IC processes. Cu posts are used to connect the electronic devices and to address thermal management issues as well. This paper presents materials aspects to consider when fabricating through silicon vias (TSVs). Modeling of the Cu-filled vias to investigate thermal management schemes and Cu posts to investigate mechanical reliability is also presented.

Development of silica PVA wheels for wet mirror grinding of a silicon wafer

Development of silica PVA wheels for wet mirror grinding of a silicon wafer

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.

Grinding performance of pellet prepared using nanosize ceria particles

The cerium oxide particles of single crystal were obtained only by the combination of precipitation method and hydrothermal treatment at lower temperature than 200 °C. The particles showed plate-like shape even in the particle size of about 4 nm, and the plate-like plane was identified to be (1 1 1) from the observation of lattice images. By heating at 100–700 °C in air, the particle size was increased from about 4 to 60 nm maintaining the plate-like shape with elevating the temperature. These cerium oxide particles were applied as a fine abrasive grain for mirror grinding. We manufactured a grinding pellet, consisting of the plate-like cerium oxide particles, using electrophoretic deposition (EPD) phenomenon. It is called “ceria EPD pellet”. As a result of grinding of quartz-crystal wafer using the ceria EPD pellet, fine mirror surface with roughness less than 1 nmRy was realized. Grinding efficiency of the ceria EPD pellet was fourth time as high as a silica EPD pellet.

Thinning Technology of Patterned Silicon Wafer for Micro Pressure Sensor

Recently, the research of the gene using the transgenic mouse has been performed for the development of new medicines. However, 600,000 kinds of mice are produced for the elucidation of each gene function. For this reason, the intelligent microchips have been developed to obtain an individual identification and biological information. The ventricular rate of a mouse can be monitored by the micro pressure sensor mounted on the intelligent microchip. In this research, the detailed structure and functions of the micro pressure sensor were investigated by the FEM analysis, and the sensor-chips were manufactured on 6-inch silicon wafer. The wafer thickness had to be reduced owing to the size restriction of the intelligent microchip. The grinding of the 6-inch silicon wafer with 560 µm in thickness with 19200 sensor-chips was carried out by the newly developed thinning technology. After the basic characteristics of a sensor-chip were evaluated, the output profile containing small peaks corresponding to the heartbeat of a transgenic mouse was finally detected using a mounted sensor-chip.

Separation of Gallium and Arsenic in Wafer Grinding Extraction Solution Using a Supported Liquid Membrane that Contains PC88A as a Carrier

Wafer grinding extraction solution was passed through a supported liquid membrane (SLM) that contained PC88A (2-ethylhexyl phosphonic acid mono 2-ethylhexyl ester) as a carrier, to separate gallium from arsenic by selective permeation. The SLM separation process was conducted under various conditions. The kind of membrane supporter, the pH of the feed, the feed concentration, and the HCl content in the strip governed the concentration of gallium and arsenic in the strip phase. The conditions determined as optimal in the laboratory test were used to perform the pilot test. Well separation between gallium and arsenic was performed in both laboratory and pilot tests. Hydrophobic membrane polytetrafluoroethylene (PTFE) with 0.2 μm pores was the best of three membrane supporters. The most efficient separation was obtained using an acidic feed (pH at 1.8) with 1000 ppm gallium. Over a 12-h period of stripping, the striped Ga concentration increased with the HCl concentration from 0.5 to 2.0 M and then leveled off. The recovery rate in the pilot test exceeded that on the laboratory scale because the membrane area was greater. The pilot test yielded a high recovery percentage of gallium (at 91%) and a low recovery of arsenic (merely 1.3 ppm) in the strip over 72 h.

2610 硬脆材料の鏡面研削砥石に関する研究 : EPD研削における粗さの原因究明(S74-1 砥粒加工(1),S74 砥粒加工)

It has been demonstrated that damage less mirror grinding of silicon wafer is realized by EPD pellet. However, the surface roughness after EPD grinding is on the order of 10nmRz. In this study, brush cleaning and O_3/HF cleaning operations were carried out, and it found that the roughness of EPD ground surface after these operations was 5nmRz or less. This result may show that the roughness have been measured the ground surface which constituents of the EPD pellet was adhered.

In-process force monitoring for precision grinding semiconductor silicon wafers

Forces generated during precision wafer grinding are small and present challenges for accurate and reliable process monitoring. In this work, these challenges are met by incorporating noncontact displacement sensors into an aerostatic spindle that is calibrated to measure grinding forces from the relative motion between the spindle rotor and stator. This arrangement allows the calculation of grinding forces without introducing compliance into the structural loop of the grinding machine. Aerostatic spindles are used in precision wafer grinding requiring high stiffness and very low error motions (5-25 nm). Several experiments evaluate this force sensing approach in detecting workpiece contact, process monitoring with small depths of cut, and detecting workpiece defects. The results indicate that force measurements offer good performance for monitoring precision wafer grinding since this approach provides excellent contact sensitivity, high signal resolution, and has sufficient bandwidth to detect events occurring within a single revolution of the grinding wheel.

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.

Fine grinding of silicon wafers: machine configurations for spindle angle adjustments

This paper addresses an important aspect of silicon wafer fine grinding: machine design. For any commercially available wafer grinders, spindle angle adjustments based on the wafer shape ground is almost inevitable in order to achieve flat wafers. However, there has been no commonly accepted guidance for the design of machine configurations to ensure the easiest adjustment. Practitioners doing spindle angle adjustments have been frustrated by the difficulties of achieving the adjustments on commercial wafer grinders. This paper first illustrates such difficulties with a machine configuration frequently cited in the literature. It then demonstrates the potential ease of spindle angle adjustments with a proposed machine configuration. Next, it shows mathematically that the proposed configuration (specifically, a pair of the axes for spindle angle adjustments) is uniquely determined once the wheel diameter and wafer diameter are known. It also shows that the proposed configuration is the best in terms of ease in spindle angle adjustments. The spindle angle adjustments will be more difficult with any other configurations deviating from the proposed one.

Separation of Gallium and Arsenic from the Wafer Grinding Extraction Solution

This work investigates the separation of gallium and arsenic from the wafer grinding extraction solution. The wafer grinding extraction solution was generated using hot and concentrated nitric acid. In this study, adsorption technology was employed to remove the toxic arsenic from the extraction solution. Ferric hydroxide was the adsorbent employed to adsorb arsenic. The effects of pH value, contact time, absorbent dosage, and chloride ion concentration on the efficiency of adsorption of gallium and arsenic were investigated. The optimal conditions for recovering gallium and removing arsenic were a raw pH of 0.2, a contact time of 6 min and a ferric hydroxide concentration of 30.4 g/L. Additionally, adding chloric ions reduces the residual percentage of gallium (ReGa) and the percentage of arsenic removed (RAs). Under these optimal conditions, ReGa and RAs are 100 and 80%, respectively.

Finite Element Analysis on Soft-Pad Grinding of Wire-Sawn Silicon Wafers

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. Several approaches (namely, combination of grinding and lapping, reduced chuck vacuum, soft-pad, and wax mounting) have been proposed to address this issue. Finite element analysis modeling of these approaches was conducted and the results were published earlier. It was shown that soft-pad grinding was a very promising approach since it was very effective in reducing the waviness and very easily adopted to conventional grinding environment. This paper presents a study of finite element analysis on soft-pad grinding of wire-sawn silicon wafers, covering the mechanisms of waviness reduction and the effects of pad material properties.

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.

Rotational grinding of silicon wafers—sub-surface damage inspection

Industrial practise in wafer manufacturing indicates that there is not one agreed method available to acquire a conclusive picture of the sub-surface damage, defined as structural inhomogeneities of the crystal lattice. Therefore, various methods have been studied and compared for measurement of the sub-surface damage introduced to single crystal silicon wafers during rotational grinding process. Several probing techniques were used to analyse a controlled set of ground silicon wafers. Optical methods were used to study the strain distribution, scattering-in depth and surface topography of the sample set. Acoustic and X-ray diffraction were used to directly observe variations in the Young’s modulus and the lattice constant, respectively. The techniques used ranged from point analysis to whole-wafer mapping and averaging. The study indicates that the various physical properties of the lattice damage arise from closely linked processes taking place during the grinding process. The correlations between the methods included in this study have been identified and quantified, and the relationships between the various observable quantities of sub-surface damage are discussed.

Separation of Gallium and Arsenic from the Wafer Grinding Extraction Solution

Abstract This work investigates the separation of gallium and arsenic from the wafer grinding extraction solution. The wafer grinding extraction solution was generated using hot and concentrated nitric acid. In this study, adsorption technology was employed to remove the toxic arsenic from the extraction solution. Ferric hydroxide was the adsorbent employed to adsorb arsenic. The effects of pH value, contact time, absorbent dosage, and chloride ion concentration on the efficiency of adsorption of gallium and arsenic were investigated. The optimal conditions for recovering gallium and removing arsenic were a raw pH of 0.2, a contact time of 6 min and a ferric hydroxide concentration of 30.4 g/L. Additionally, adding chloric ions reduces the residual percentage of gallium (ReGa) and the percentage of arsenic removed (RAs). Under these optimal conditions, ReGa and RAs are 100 and 80%, respectively.

An experimental investigation into soft-pad grinding of wire-sawn silicon wafers

Silicon is the primary semiconductor material used to fabricate microchips. A series of processes are required to manufacture high-quality silicon wafers. Surface grinding is one of the processes used to flatten wire-sawn wafers. A major issue in grinding of wire-sawn wafers is reduction and elimination of wire-sawing induced waviness. Results of finite element analysis have shown that soft-pad grinding is very effective in reducing the waviness. This paper presents an experimental investigation into soft-pad grinding of wire-sawn silicon wafers. Wire-sawn wafers from a same silicon ingot were used for the study to ensure that these wafers have similar waviness. These wafers were ground using two different soft pads. As a comparison, some wafers were also ground on a rigid chuck. Effectiveness of soft-pad grinding in removing waviness has been clearly demonstrated.

Waviness removal in grinding of wire-sawn silicon wafers: 3D finite element analysis with designed experiments

Silicon wafers are used to fabricate more than 90% of integrated circuits. Surface grinding has been used to flatten wire-sawn silicon wafers. A major issue in grinding of wire-sawn wafers is that conventional grinding cannot effectively remove the waviness induced by wire-sawing process. Soft-pad grinding is a promising method to effectively remove waviness. This paper presents the results of three-dimensional (3D) finite element analysis of soft-pad grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal main effects as well as interaction effects of four factors (Young’s modulus, Poisson’s ratio, and thickness of the soft pad, and waviness wavelength of the wafer) on the effectiveness of waviness reduction. Implications of this study to manufacturing are also discussed.

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.