Wafer Grinding Research Articles

Molecular Dynamics Simulation of Chemo-Mechanical Grinding (CMG) by Controlling Interatomic Potential Parameters to Imitate Chemical Reaction

This paper reports a molecular dynamics simulation of chemo-mechanical grinding (CMG) of silicon wafer by controlling the interatomic potential parameters to imitate the chemo-mechanical or mechano-chemical reactions between an abrasive grain and a Si wafer. Some comparisons between diamond grinding and CMG were made by using the proposed simulation model. From the simulation results, reductions of surface damages, wears of abrasive grain and scratching forces in CMG were confirmed to be same as observed in actual experiments by a CeO2 abrasive wheel, and the availability of proposed simulation model was verified.

Effects of Sodium Carbonate and Ceria Concentration on Chemo-Mechanical Grinding of Single Crystal Si Wafer

Chemo-mechanical grinding (CMG) process is a promising process for large-sized Si substrate fabrication at low cost. An encountered issue in current CMG process of Silicon (Si) wafers is metallic contaminations on ground Si wafer surface, which is attributed to the existence of sodium carbonate in wheel compounds. In this paper, four different CMG wheels were developed and grinding experiments were conducted to study the effects of exclusion of sodium carbonate and concentration of ceria abrasive on grinding performance. The grinding characteristics of the four wheels were analysized and discussed to reveal the effects of different compositions.

A Novel Single Step Thinning Process for Extremely Thin Si Wafers

The demand for extremely-thin Si wafers is expanding. Current manufacturing technologies are meeting great challenges with the continuous decrease in Si wafer thickness. In this study, a novel single step thinning process for extremely thin Si wafers was put forward by use of an integrated cup grinding wheel (ICGW) in which diamond segments and chemo-mechanical grinding (CMG) segments are alternately allocated along the wheel periphery. The basic machining principle and key technologies were introduced in detail. Grinding experiments were performed on 8-in. Si wafers with a developed ICGW to explore the minimal wafer thickness and grinding performance. The experimental results indicate that the proposed grinding process with the ICGW is an available thinning approach for extremely thin Si wafer down to 15μm

Study on Improvement of Material Removal Rate in Chemo-Mechanical Grinding (CMG) of Si Wafer

Silicon wafer thinning process is meeting great challenges to fulfill requirements of ultra-thin IGBT for automotive applications. Chemo-mechanical grinding (CMG) process is potentially emerging stress relief thinning process which combines the advantages of fixed abrasive machining and chemical mechanical polishing (CMP). A major issue in CMG of Si wafers is the relatively low material removal rate (MRR). This paper studies the influence of the wheel specifications and grinding conditions on the MRR of CMG. Two sets of three-factor two-level full factorial designs of experiment (DOE)[1] are employed to reveal the main effects and interacted effects of CMG wheel specifications and grinding parameters on MRR. The optimal combination scenarios for improving MRR of CMG are analysized and obtained. By use of the optimal CMG wheel and grinding parameters, the MRR of more than 60nm/min is achieved.

Material Removal Mechanism of Chemo-Mechanical Grinding (CMG) of Si Wafer by Using Soft Abrasive Grinding Wheel (SAGW)

An innovative fixed abrasive grinding process of chemo-mechanical grinding (CMG) by using soft abrasive grinding wheel (SAGW) has been recently proposed to achieve a damage-free ground workpiece surface. The basic principle, ideas and characteristics of CMG with SAGW are briefly introduced in this paper. The CMG experiments using newly developed SAGW for Si wafer are conducted at the condition of dry grinding. The grinding performances are evaluated and analyzed in terms of surface roughness, surface topography and surface/subsurface damage of ground wafer by use of Zygo interferometer, Scan Introduction ning Electron Microscope (SEM) and Cross-section Transmission Electron Microscope (Cross-section TEM). The component of product of ground Si surface is studied by X-ray Photoelectron Spectroscopy (XPS) to verify chemical reaction between the abrasive / additives of grinding wheel and Si wafer. The CMG process model by using SAGW is developed to understand the material removal mechanism and generation principle of damage-free surface. The study results show that the material removal mechanism of CMG by using SAGW can be explained as a hybrid process of chemical and mechanical action.

An experimental study of flat fixed abrasive grinding of silicon wafers using resin-bonded diamond pellets

The purpose of this paper is to investigate the effect of the diamond grain size, the wheel rotation speed, the table rotation speed, and the applied pressure in the vertical flat grinding on the surface roughness of silicon wafers using Taguchi orthogonal array design. Besides, the pits and resistivity on the wafers were studied as well. The experiment results showed that the diamond grain size and the wheel rotation speed of the vertical flat grinding for the roughness of wafers obtained are the relatively larger significant contribution. When the smaller diamond grit size, the faster wheel rotation speed, the faster table rotation speed, and the smaller applied pressure in the flat grinding are employed, the traces produced by the grains are denser and the chip thickness and the depth of cut were smaller, which cause the silicon wafer to produce the higher degree of the ductile grinding. This will lead the wafer surface to produce the smaller amount and size of the pits, thereby generating the lower surface roughness. In addition, the center site of the wafer obtained is the smaller amount and size of the pits than the outer of the wafer, which produces the better surface roughness and the lower resistivity.

Simultaneous double side grinding of silicon wafers: a mathematical model for the wafer shape

Silicon wafers are the most widely used substrates for fabricating Integrated Circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. Simultaneous Double Side Grinding (SDSG) is one of the processes used to flatten the sliced wafers. The literature contains several mathematical models for the wafer shape in Single Side Grinding (SSG). However, no systematical study on the wafer shape in SDSG has been reported. The first part of this paper gives an overview of current mathematical models for the wafer shape in SSG (or SDSG) of silicon wafers. Then a mathematical model for the wafer shape in SDSG of silicon wafers is developed. This developed model is then used to systematically study the effects of several SDSG parameters on the wafer shape.

A process model of wafer thinning by diamond grinding

Abstract This paper is to develop and investigate a wafer thinning process model (WTPM) to integrate the wafer thickness into set-up parameters and predict total thickness variation (TTV) of ground wafers with modification of the wafer grinding process model (WGPM) developed previously. Due to the variation of wafer thickness during diamond grinding, the WTPM can be used to estimate the TTV after wafer thinning process. Experiments have been performed on a G&N nano grinder MPS-940 to demonstrate its feasibility of silicon wafer thinning. Results have been obtained that the TTV is less than 3 μm for two sets of tests of wafer thickness of 600–700 μm and 700–800 μm as compared with the desired TTV of 0 μm from simulation of the developed WTPM with certain set-up of tilting angles. Therefore, the WTPM has been verified in this study and further used for forecasting the limitation of wafer thinning with different wafer thickness.

High Throughput SiC Wafer Polishing with Good Surface Morphology

We report SiC wafer polishing study to achieve high throughput with extremely flat, smooth and damageless surface. The polishing consists of three process, wafer grinding, lapping and chemical mechanical polishing (CMP), which are completed in shortest about 200 minutes in total for 2 inch wafer. Specimens of 4H- and 6H-SiC were provided from slicing single crystal as wafers oriented (0001) with 0 or 8 degrees offset angle toward to <112 _ 0>. By the first grinding using a diamond whetstone wheel, we realized flat surface on the wafers with small TTV error of 1 μm in 15 minutes. After second process of lapping, the wafers were finished by CMP using colloidal silica slurry. AFM observation showed not only scratch-free surface but also atomic steps on the wafers after CMP. Rms marks extremely flat value of 0.08 nm in 10 μm square area.

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: DECOMPOSITION ANALYSIS OF WAFER SURFACES

It is difficult for the lapping-based manufacturing method currently used to manufacture the majority of silicon wafers to meet the ever-increasing demand for flatter wafers at lower costs. A grinding-based manufacturing method for silicon wafers has been investigated. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. The generation mechanisms of the dimples and bumps in the central areas on ground wafers have also been studied. This paper reports another study on the grinding-based method, aiming to reduce the cost of chemical-mechanical polishing – the final material removal process in manufacturing of silicon wafers. Using design of experiments, investigations were carried out to understand the influences of grinding process variables on the peak-to-valley values of the polished wafer surfaces. It was found that the peak-to-valley values over the entire wafer surfaces did not show any relationship with grinding process variables. However, after analyzing the surface profiles by decomposing them into different frequencies, it was observed that there is a correlation between grinding process variables and certain surface feature components. Based on this finding, it is recommended to optimize the grinding process variables by minimizing the peak-to-valley values for each surface feature component, one at a time. This methodology has not been published for wafer grinding and is of practical use to the wafer industry.

Investigations of silicon wafer grinding using finite element analysis

Silicon wafers are used as substrates to build more than 90% of integrated circuits. One of the manufacturing processes for silicon wafers is grinding. This paper reports the investigations of silicon wafer grinding using Finite Element Analysis (FEA). FEA models are first used to study the effects of process parameters on waviness reduction in the grinding of wire-sawn wafers on a rigid chuck. Then, soft-pad grinding of wire-sawn wafers is modelled using FEA to study the effects of pad properties on waviness reduction. Finally, FEA is used to study the elastic deformation of the grinding wheel, providing an explanation for the central dimples on ground wafers.

Experimental Investigations of Silicon Wafer Grinding

The majority of integrated circuits are built on silicon wafers. To manufacture high-quality silicon wafers, a series of processes are needed. After a wire sawing process slices silicon ingots into wafers, grinding processes can be used to flatten the sliced wafers. This paper reports three experimental investigations on wafer grinding. The first investigation was to study the effectiveness of soft-pad grinding in removing the wire-sawing induced waviness. The second was to explore the capability of grinding in achieving super flatness. The third was to study the effects of grinding parameters on wafer flatness.

Different approaches to integrate patterned buried CoSi 2 layers in SOI substrates

The fabrication of a new silicon on silicide on insulator (SSOI) substrate for the integration of bipolar and CMOS devices on the same wafer is demonstrated. This structure includes a 500 nm thick buried oxide (BOX) and a 90 nm patterned cobalt disilicide film under a 300 nm thick silicon device layer. Two different process flows were used to build the final SSOI substrate. The first process bases on the known BESOI regime and includes wafer grinding and polishing steps. The second technology is a modified variant of the SmartCut TM method, where the SOI substrates are formed using hydrogen implantation, wafer splitting and CMP polishing. The cobalt disilicide was produced using a conventional cobalt salicide process. This process consists of cobalt deposition, two RTA steps and a selective etch. Some modifications in the salicide regime were made to improve the interface between the CoSi 2 and the device silicon.

Novel method to investigate the critical depth of cut of ground silicon wafer

Ductile regime grinding of silicon wafer has advantages such as smooth surface roughness ( R a < 10 nm) and minimum subsurface damage layer (<10 μm). With ductile regime grinding, the subsequent processes such as etching and rough polishing processes can be minimized in the production of silicon wafer. To achieve ductile regime grinding, a fundamental concept is the application of grain depth of cut being less than the critical cut depth, d c, of the silicon wafer. The objective of this paper is to derive, and to investigate by experiment, the d c value for silicon wafer grinding. Following these key steps, the effects of d c on various major grinding parameters are studied.

Back side exposure of variable size through silicon vias

The formation of microscale vertical interconnects enables three-dimensional interconnects for chip stacking applications. These vertical interconnects, or metal filled through silicon vias, are formed by a series of processing steps that include silicon etch, insulation/barrier/seed deposition, electroplated Cu to fill via, wafer grinding and thinning, and back side processing for contacts. Variable diameter size vias residing in the same wafer allow flexibility in integration for many applications. Producing variable size through silicon vias (VTSVs) on a single wafer is challenging. This article presents details regarding the exposure of VTSV using a unique wafer back side processing technique. Via diameters are in the range of 10–30μm and etch depth varies with via diameter due to the commonly observed reactive ion etch lag. In this approach, the finished wafers are thicker than that produced in a previous project which reduces the risk of wafer breakage during the debonding process.

Development of silica PVA wheels for wet mirror grinding of a silicon wafer

Development of silica PVA wheels for wet mirror grinding of a silicon wafer

Fabrication of Nanoabrasive Grinding Wheels and Their Application to Grinding Silicon Wafers

In the surface machining of brittle materials, there exists a transition from brittle to ductile modes when the depth of cut is reduced below a critical size using ultrafine abrasive grains. Vitrified grinding wheels containing ultrafine abrasives in the sub-micrometer to nanometer range were fabricated by mechanochemically milling nanoabrasive particles and subsequent viscous sintering of abrasive-binder composites. The grinding characteristics of the nanoabrasive grinding wheels were evaluated for the fine grinding of silicon wafers in terms of a variety of variables. Preliminary wafer grinding results are presented on material removal rate and surface quality of silicon wafers.

ELID grinding of silicon wafers: A literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.

Modelling and analysis of waviness reduction in soft-pad grinding of wire-sawn silicon wafers by support vector regression

The manufacturing of silicon wafers forms the most important step in the construction of integrated circuit (IC) chips. One of the difficulties in this manufacture process is the removal of the waviness from the resulting wafers. In this paper, mathematical modelling and analysis of this removal process is carried out by the use of the support vector regression (SVR) algorithm. The results show that SVR is ideally suited for the modelling of this complicated process. Furthermore, by the use of the learning ability of SVR, the model can be continuously improved as more data become available. Based on the resulting model, the influences of the various factors on the rate of removal and the ease of control of the removal process are also discussed.

A Fuzzy Adaptive Network Model for Waviness Removal in Grinding of Wire-Sawn Silicon Wafers

Silicon is the primary semiconductor material used to fabricate microchips, and the quality of microchips depends directly upon the quality of the starting silicon wafers. One of the manufacturing problems in silicon wafer manufacturing is the presence of waviness on the surface as a result of wire-saw slicing. Various factors influence the waviness reduction capacity during soft-pad grinding; the grinding process is very complicated and difficult to define. In this research, fuzzy adaptive network, which is ideally suited to the modeling of vague phenomena, is used to model the waviness problem. Fuzzy adaptive network has the learning ability of a neural network and the linguistic representation of a complex, not well understood phenomenon. Simulation data are used to illustrate the applicability of fuzzy adaptive network. The results, even though based on some very limited data, indicate the influences of the independent parameters clearly.