Wafer Fabrication Research Articles

Dual-Arm Cluster Tool Scheduling for Reentrant Wafer Flows

Cluster tools are the key equipment in semiconductor manufacturing systems. They have been widely adopted for many wafer fabrication processes, such as chemical and physical vapor deposition processes. Reentrant wafer flows are commonly seen in cluster tool operations for deposition processes. It is very complicated to schedule cluster tools with reentrant processes. For a dual-arm cluster tool with two-time reentering, the existing studies point out that a one-wafer periodical (1-WP) schedule can be found, and it is optimal in terms of productivity. However, for some wafer fabrication processes, wafers should be processed at some PMs more than two times. This gives rise to a question of whether there still exists a 1-WP schedule for dual-arm cluster tools with the number of reentering times being more than two such that the cycle time of a tool can reach the lower bound. This problem is still open, and this is what this work wants to tackle. For a dual-arm cluster tool with the number of reentering times being k (>2) times, if there does not exist a value f ∈ {1, 2 …} such that k = 3f, theoretical proofs are given to show that a 1-WP schedule can be found, otherwise it does not exist. For cases with a 1-WP schedule, the cycle time can be obtained by analytical expressions. For the cases without a 1-WP schedule, two new methods for a three-wafer periodical schedule are proposed to improve the system productivity by comparing it with an existing three-wafer periodical schedule. The applications of the obtained results are demonstrated by examples. Wafer residency time constraints are required for some wafer fabrication processes. Note that the results obtained in this work cannot be directly applied to cluster tools with both reentrant wafer flows and wafer residency time constraints. Nevertheless, schedulablity and scheduling analyses for that applications can be conducted based on the obtained results in this work.

Sidewall Modification Process for Trench Silicon Power Devices

In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF6/CHF3 proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF3 flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

Optimal Cyclic Scheduling of Wafer-Residency-Time-Constrained Dual-Arm Cluster Tools by Configuring Processing Modules and Robot Waiting Time

Optimal cyclic scheduling problems of wafer-residency-time-constrained dual-arm cluster tools in wafer fabrication are challenging and remain to be fully solved. Existing studies assume that all processing modules (PMs) of a required type are used to process the same type of wafers. This sometimes brings unneeded conservation to scheduling results, because we may be able to make a tool schedulable by reducing the number of PMs in some steps if the original one is not. In some cases, we may use fewer PMs to reach the same result if the original one is schedulable. This work selects a proper number of PMs of needed types to process wafers with the highest productivity. It proposes the necessary and sufficient conditions under which a tool is schedulable and develops a polynomial-complexity algorithm that finds an optimal cyclic schedule. Examples are given to show its superiority over existing ones, thus advancing this field greatly.

A lexicographic optimization approach for a bi-objective parallel-machine scheduling problem minimizing total quality loss and total tardiness

In wafer fabrication, production quality is a key performance index and is subject to machine condition deterioration. This paper studies a parallel-machine scheduling problem that can typically be found in the photolithography process. To solve the problem, a lexicographic optimization approach is proposed where the total quality loss is firstly minimized and the second objective is to minimize total tardiness. An optional maintenance activity is also considered to restore the machine condition to a certain level. Optimality properties are discussed, based on which an exact scheduling algorithm is developed. Experimental analyses derived from real data demonstrate the effectiveness of the proposed algorithm and support some managerial insights.

The Co-Design of Broadband Diplexer and Quasi-Reflectionless Lowpass/Highpass TFIPD Filter Chip

A new ultra-miniaturized 5G N78 and N79 diplexer based on GaAs Thin Film Integrated Passive Device (TFIPD) technology is proposed in this brief. By a NiCr thin film resistor, the quasi-reflectionless lowpass/highpass filter can also be achieved on the same circuit structure without any increase of size. Circuit schematic is composed of serial-parallel inductances and capacitances, which generates out-of-band transmission zeros. The proposed design provides <2 dB insertion loss and >15 dB out-of-band rejection. Therefore, the GaAs-based TFIPD technology can support low-loss, high-precision, and miniaturized design desires of 5G radio-frequency (RF) front-end devices. Chip model is demonstrated through EM simulation, wafer fabrication, and measurement.

Introduction of IC Manufacturing to Amateurs

In the fabrication of silicon wafers to create integrated circuits, chemistry and physics play a significant role. It is important to change the silicon wafer surface conditions and properties using both innocuous and harmful compounds, particular and uncommon circumstances, plasma-state elements, and RF (Radio Frequency) energies. Starting with the production of silicon wafers, sands are molten under high temperature in order to change its molecular structure. In this process, silicon ingot with particular diameter is formed and sliced into pieces of wafer. Following by chemical manufacture, wafer would be prepared to be fabricated into integrated circuits. Then, the circuits would be drawn onto the wafer through oxidation, photolithography, etching, diffusion, and ion implanation. After those fabrication, all these components (transistors, resistors, capacitors, and so on) were only accessible as discrete units, would have taken up most of a medium-sized room 20 years ago, the devices currently fill a one-inch square IC’s surface. When it comes to wafer sorting, a systematic mode will be used to take each bad die from the whole die pie. The researchers will use the relative finder and tester to gain the situation for each die and this work will bring foundation to the following stages including packaging and final test. The packaging process comes to the next consideration. This work divides the packaging process into five steps. All those steps are listed clearly in the essay below, from sawing up the wafer into an individual die to marking the packages. The final process after packaging is the final test. The final test is not such complicated. So this work only introduces the devices that it will use and its purpose.

Integrated membrane-free thermal flow sensor for silicon-on-glass microfluidics.

Lab-on-a-chip (LOC) forms the basis of new-generation portable analytical systems. LOC allows the manipulation of ultralow flows of liquid reagents and multistep reactions on a microfluidic chip, which requires a robust and precise instrument to control the flow of liquids on a chip. However, commercially available flow meters appear to be a standalone option adding a significant dead volume of tubes for connection to the chip. Furthermore, most of them cannot be fabricated within the same technological cycle as microfluidic channels. Here, we report on a membrane-free microfluidic thermal flow sensor (MTFS) that can be integrated into a silicon-glass microfluidic chip with a microchannel topology. We propose a membrane-free design with thin-film thermo-resistive sensitive elements isolated from microfluidic channels and a 4'' wafer silicon-glass fabrication route. It ensures MTFS compatibility with corrosive liquids, which is critically important for biological applications. MTFS design rules for the best sensitivity and measurement range are proposed. A method for automated thermo-resistive sensitive element calibration is described. The device parameters are experimentally tested for hundreds of hours with a reference Coriolis flow sensor demonstrating a relative flow error of less than 5% within the range of 2-30 μL min-1 along with a sub-second time response.

Photolithography Fabricated Sub-Decibel High-Efficiency Silicon Waveguide Grating Coupler

Using the optimized shift-pattern overlay method, we present a new high-efficiency silicon waveguide grating coupler operating at 1550 nm center wavelength, which has a simulation predicted coupling loss of 0.68 dB and experimentally measured loss of 0.89 dB. This record result was achieved without any substrate bottom mirrors or use of electron beam lithography and was fabricated with the standard processes of a multi-project wafer fabrication service from a commercial foundry.

Path Planning of Randomly Scattering Waypoints for Wafer Probing Based on Deep Attention Mechanism

Wafer probing is a critical process employed to measure the yield of wafer fabrication. The primary object of wafer probing is to find the defect grain on the wafer. After a full coverage check, there are always some suspected grains existing for further inspection. However, this second probing result could be affected by the shape of the probe card and the setting actions (path planning) of operators for grains randomly scattering on the wafer. Good grains can be damaged by reprobe actions, which decrease production performance and customer trust. In general, it also requires manpower to perform reprobing, which dramatically deteriorates the throughput of production. This article has studied this problem, and an adaptive coverage path planning (CPP) method for randomly scattering grains using an attention interface is proposed. The proposed randomly scattering waypoints method uses deep reinforcement learning (DRL) for automatic real-time path planning of the second detection. A soft attention interface accelerates the process with a less overlapped check. The experimental results demonstrate the efficiency of the proposed method in terms of less overlapping and steps, and this method learns a better CPP strategy for wafer probing than programmed paths and other RL-based methods.

Advances in machine learning for large-scale manufacturing of photonic circuits

Machine learning has opened a new realm of possibilities in photonic circuit design and manufacturing. First, we describe our approach of using deep learning to optimize the multi-dimensional parameter space for hundreds of optical chips on a mask, resulting in homogeneity of performance in high volume applications. Second, we present our approach of using a support vector machine to predict the performance of optical devices by wafer probing. This approach eliminates the expensive and labour-intensive process of optical chip testing, and allows unprecedented control over the fabrication process, including in-situ monitoring of wafer fabrication and real-time process adjustments. The combination of these two approaches paves the way for accelerated adoption of photonics in high volume applications.

Hierarchical Decision-Making for Qualification Management in Wafer Fabs: A Simulation Study

A qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is discussed. The stepper equipment needs to be qualified to process lots that belong to different families. Stepper- and family dependent qualification time windows exist. Time windows can be reinitialized if required and can be extended by on-time processing of lots from qualified families. A hierarchical approach is proposed. The base-level provides a dispatching strategy that takes into account qualification decisions, while the mid-level consists of a mixed integer linear program (MILP) for making qualification decisions. The top-level comprises a linear program (LP) that computes target quantities for the families on the steppers in each period of the planning window taking into account fab-wide objectives. In addition to an LP formulation with conventional capacity constraints, we provide a formulation where clearing functions are used to represent the congestion of the wafer fab. We also discuss how to anticipate the behavior of the mid-level on the top-level. Results of simulation experiments where the hierarchical approach is applied in a rolling horizon manner demonstrate that the LP-based approaches outperform a heuristic to determine the target quantities. Among the LP formulations, the ones with clearing functions perform best. We also demonstrate the value of anticipation. Note to Practitioners—A hierarchical approach is designed to decide when tools in wafer fabs have to be qualified for a certain lot family. Qualification-related decisions are highly relevant because qualifications are costly and take a lot of time. The top-level determines target quantities for each family based on linear programming. The mid-level is formed by a MILP. A dispatching scheme to implement the qualification decisions provides the base-level. The hierarchical approach is assessed in a rolling horizon setting using a simulation model of a 200mm wafer fab. The benefit of the different levels of the hierarchy is demonstrated by simulation experiments.

Data-Driven Adaptive Virtual Metrology for Yield Prediction in Multibatch Wafers

Virtual metrology (VM) is widely used for yield management and control in semiconductor manufacturing owing to its high real-time inspection, low cost, and convenient maintenance. However, the multimodal characteristics of batch processes are ignored in the existing yield VM models. The adaptive multimodal division and modal sample imbalance have also not been considered. Therefore, a data-driven adaptive VM model based on the Gath–Geva fuzzy clustering (GGFC) and multitask learning deep belief network (MLDBN) is proposed to solve the problems above. First, the GGFC model is designed to realize the feature extraction of the batch direction and the modal division of the time and variable directions. Second, the partition coefficient and classification entropy indexes are designed to determine the modal categories automatically and establish the SMOTE model to deal with the imbalance of multimodal samples. Third, the local features of multimodal are extracted by the designed MLDBN models. After that, the batch direction features and the multi-features extracted from multimodal are used as the improved MLDBN parameters to realize the fusion prediction. Finally, experiments are carried out by the accurate industrial data from a multibatch wafer fabrication process. The efforts show that the proposed VM model presents better performances in the result of different indicators and has higher accuracy and robustness than the traditional models.

Scheduling of time-constrained single-arm cluster tools with purge operations in wafer fabrications

Purge operations are widely used to remove residual chemicals and impurities in chambers of wafer fabrication systems to ensure wafer quality. However, such operations lead to more start-up transient processes and wafer delays. In addition, wafer residency time constraints must be met to ensure the wafer quality. Thus, the system scheduling problem with such considerations will become more complicated. This work aims to optimize the start-up transient process of a single-arm cluster tool with purge operations and wafer residency time constraints by using resource-oriented Petri net (ROPN) models. Based on the models, we dynamically depict the behavior of the steady state and start-up transient processes of a single-arm cluster tool with purge operations. Then, a scheduling method that dynamically adjusts the robot waiting time is proposed to find an optimal schedule for such systems with purge operations and wafer residency time constraints. Finally, some examples are tested to illustrate the effectiveness of our method.

A class imbalanced wafer defect classification framework based on variational autoencoder generative adversarial network

Wafer defect classification (WDC) can be crucial to the wafer fabrication process. Engineers can quickly respond to improve the technological process, averting further defects through WDC. However, due to the complex fabrication steps, wafer defects are different in various types. This causes a severe data imbalance problem in WDC. To effectively solve the problem, this study introduces a class imbalanced WDC based on Variational Autoencoder Generative Adversarial Network (VAE-GAN). This framework consists of VAE-GAN and wafer defect classifier. Among them, VAE-GAN is responsible for creating new samples to solve the imbalance problem while the classifier is responsible for classifying wafer defect patterns. Specifically, VAE-GAN combines the advantage of a Variational Autoencoder (VAE) and generative adversarial network. VAE networks can produce subtle differences that do not affect the properties of the data when generating new images. At the same time, the proposed discriminator can help us constrain the generated images to be close to real samples and avoid irrational, feature-missing, and ambiguous samples. WM-811 K dataset is utilized to verify the above method. The experimental results validate that the samples generated by VAE-GAN have a significant improvement in the performance of the WDC system.

Polarization-independent waveguide grating coupler using an optimized polysilicon overlay.

We propose and validate a new, to the best of our knowledge, approach to designing a polarization-independent waveguide grating coupler, using an optimized polysilicon overlay on a silicon grating structure. Simulations predicted coupling efficiencies of about -3.6 dB and -3.5 dB for TE and TM polarizations, respectively. The devices were fabricated using photolithography in a multi-project wafer fabrication service by a commercial foundry and have measured coupling losses of -3.96 dB for TE polarization and -3.93 dB for TM polarization.

A Dynamic Dispatching Method for Large-Scale Interbay Material Handling Systems of Semiconductor FAB

Interbay Automated Material Handling Systems (AMHS) are widely adopted especially in Semiconductor Wafer Fabrication Systems (SWFS). The dispatching method plays a major role in the control of AMHS. This paper proposes an efficient multi-objective dynamic dispatching method which will dynamically adjust vehicle-load assignments according to the real-time situation of the system. A multi-objective cost function with variable weights is established, taking into account various performance indices (i.e., transport time, throughput, cycle time, vehicle utilization, movement, and waiting time), and the corresponding mathematical model is formulated. Then, in order to obtain the suitable weights according to the real-time condition, an advanced method is developed based on fuzzy theory. After that, a Hungarian algorithm is adopted to solve the model. Finally, simulations are conducted to validate the proposed method. The results demonstrate that it has better comprehensive performance compared to the previous dispatching methods.

유전알고리즘 기반 로트 타겟팅 최적화 연구: 반도체 포토공정을 대상으로

Production scheduling in a semiconductor wafer fabrication (FAB) can be decomposed into two phases: lot targeting and lot dispatching. A weighted dispatching rule is a widely applied concept to obtain the production schedule in the FAB under its complex manufacturing factors. The weights of the dispatching rule should be carefully determined since the weights substantially impact the performance of the FAB. In this study, we investigate a weighted lot targeting rule considering the time-variant manufacturing factors, i.e., processing times, set-up operations, work-in-process levels, and transportation times for the bottleneck (photolithography) process. We propose a Genetic Algorithm (GA) to determine the efficient weights of the weighted lot targeting rule within a limited simulation run. Our simulation experiments demonstrate that the proposed approach outperforms widely used targeting rules under the time-variant manufacturing factors in the FAB.

Effects of metal impurities at the edges of cast Si ingot on crystal quality and solar cell performance

In this study, the effects of metal impurity diffusion at the edges of cast crystalline Si on crystal quality and solar cell performance were investigated and analyzed. The metal impurity diffusion resulted in a decrease of the minority carrier lifetime within Si crystal, low luminous intensity in photoluminescence (PL) images for wafers, high density leakage points in electroluminescent (EL) images and the decrease of photoelectric conversion efficiency(η) for solar cells. The study reveals that the region of low minority carrier lifetime (i.e., red-zone) in Si wafers can be narrowed down by using annealing treatment, in a temperature range of 500–600 °C. However, the annealing treatment on Si wafers had little effect on the efficiency of solar cells. A novel slicing direction for Si wafers, along to the crystal orientation (ACO), allowed the fabrication of Si wafers with non-red zone or with complete red-zone from the same side Si block. The η of the solar cells based on Si wafers with non-red zone was 1.7 % higher than that of the solar cells based on Si wafers with complete red zone. In addition to that, while being sliced from the same side Si block, the mean η of cells, based on wafers from the ACO slicing method was calculated to be 0.11 % higher than that of cells, which based on wafers from the traditional perpendicular crystal orientation (PCO) slicing method.

Restricted Relevance Vector Machine for Missing Data and Application to Virtual Metrology

In semiconductor manufacturing, virtual metrology (VM) is a method of predicting physical measurements of wafer qualities using in-process information from sensors on production equipment. The relevance vector machine (RVM) is a sparse Bayesian kernel machine that has been widely used for VM modeling in semiconductor manufacturing. Missing values from equipment sensors, however, preclude training an RVM model due to missing kernels from incomplete instances. Moreover, imputation for such kernels can lead to a loss of model sparsity. In this work, we propose a restricted RVM (RRVM) that selects its basis functions from only complete instances to handle incomplete data for VM. We conduct the experiments using toy data and real-life data from an etching process for wafer fabrication. The results indicate the model’s competitive prediction accuracy with massive missing data while maintaining model sparsity. Note to Practitioners—In recent decades, virtual metrology (VM) has focused on wafer fabrication in semiconductor manufacturing due to its advantages for process monitoring and automation. Typically, signals from production process equipment can predict wafer qualities in VM, which often leads to high data dimensionality. The relevance vector machine (RVM) is an algorithm that can provide a sparse solution to a Bayesian kernel method for a prediction model. Missing components in incomplete data due to sensor failures in wafer fabrication processes, however, hinder model training, and the existing approaches to handling missing data using imputation may lead to a loss of model sparsity. This article proposes a new method for RVM with incomplete data to train a model built on fully available instances by incorporating the available components of incomplete instances into model training. Using the proposed method, one can predict wafer qualities building a model trained to maintain its sparsity. Experiments indicate that the proposed model achieves competitive prediction performance and maintains model sparsity when incomplete instances are used.

Preparation strategy for low-stress and uniform SiC-on-diamond wafer: A silicon nitride dielectric layer

Reducing the self-heating of SiC- and GaN/SiC-based high-powered devices by integrating diamond films offers promising performance enhancement of these devices. However, such a reduction strategy faces serious problems, such as diamond nucleation on SiC and stress accumulation greater than 10 GPa. In this work, a SiNx dielectric layer (∼50 nm) was coated onto the C polar face of a 4H–SiC wafer using microwave plasma chemical vapor deposition (MPCVD) to improve direct dense diamond nucleation and growth, significantly reduce the stress, and build Si–C(SiC)⋯Si⋯C(diamond) bond bridges. This SiNx thin layer, prepared by activating Si ions under Ar/N plasma during magnetron sputtering, gave rise to local Si3N4 crystal features and a low effective work function (EWF) for promoting surface dipoles with electronegative carbon-containing groups. In the H plasma environment during diamond growth, the local Si3N4 crystal was amorphized, and the N atoms escaped as a result of atomic H and the high temperature. At the same time, C atoms diffused into the SiNx and formed C–Si bonds (49.7% of the total C bonds) by replacing N–Si and Si–Si, thus increasing the direct nucleation density of the diamond grains. The diamond thin film grew rapidly and uniformly, with a grain size of approximately 2 μm in mixed orientation, and the stress of the 2-inch SiC-on-diamond wafer was extremely low (to ∼0.1–0.2 GPa). In comparison, partially connected diamond grains (>10 μm) on the bare SiC in the preferential (110) orientation resulted in a film with twin-grain features and significant stress, which was associated with the hexagonal lattice interface of 4H–SiC. These results are considered the material and surface/interface bases for actively controlling wafer fabrication and enhancing the heat dissipation of SiC and GaN/SiC electronics.