Wafer Deformation Research Articles

A Study of Residual Stress Effects due to Adhesive Bonding of MEMS Components

Residual stress effects in MEMS wafer adhesive bonding were investigated. A waferlevel finite element (FE) modelling approach was used, which accounted for wafer configuration and allowed the deformation of individual devices across a wafer to be considered. A specific test was carried out to determine the adhesive’s viscoelastic response, through an effective timedependent Young`s modulus, so that initial and longer-term post-curing responses could be estimated. These results are compared with predictions based on modulus values obtained from Dynamic Mechanical Analysis (DMA) testing. The predicted wafer deformations are compared with optical surface profile measurements of actual specimens. Initial response predictions using the effective modulus show excellent agreement with measurements, while the DMA modulus gives a significant underestimate. On the other hand, difficulty was found in modelling long-term relaxation, due to non-linear mechanisms such as polymer “ageing” which are harder to model.

Impact of Defects in Silicon Substrate on Flash Memory Characteristics

Floating-gate type Flash memories are fabricated on Czochralski (CZ) silicon wafers. A large amount of residual misalignment in reticle shots at photolithography process step and the programming failure are observed in the low oxygen concentration wafer. The above are explained by the plastic deformation of wafer by the relaxation of internal stress during the processes.

Variance Analysis for Overlay Errors in Semiconductor Lithography Equipment

In semiconductor lithography equipment, overlay errors are caused by various factors such as poor adjustment of the equipment, wafer deformation through the process, and environmental unstability of atmospheric pressure and temperature. To explore key factors of overlay errors, this paper proposes a method of performing detailed analysis of overlay error variance. In addition, new analysis method is explained, and an actual example of the analysis is shown.

EPS(Elementwise Patterned Stamp)를 이용한 UV 나노임프린트 공정에서 웨이퍼 변형에 따른 잔류층 분석

Imprint lithography is a promising method for high-resolution and high-throughput lithography using low-cost equipment. In particular, ultraviolet-nanoimprint lithography (UV-NIL) is applicable to large area imprint easily. We have proposed a new UV-NIL process using an elementwise patterned stamp (EPS), which consists of a number of elements, each of which is separated by channel. Experiments on UV-NIL are performed on an EVG620-NIL using the EPS with 3mm channel width. The replication of uniform sub 70 nm lines using the EPS is demonstrated. We investigate the nonuniformity of residual layer caused by wafer deformation in experiment with varying wafer thickness. Severely deformed wafer works as an obstacle in spreading of dropped resin, which causes nonuniformity of thickness of residual layer. Numerical simulations are conducted to analyze aforementioned phenomenon. Wafer deformation in the process is simulated by using a simplified model, which is a good agreement with experiments.

Hemisphere-shaped silicon crystal wafers obtained by plastic deformation and preparation of their solar cells

Hemisphere-shaped crystal wafers can be prepared by the plastic deformation of Si crystal wafers. To obtain hemispherical Si wafers, graphite convex and concave dies were used. A Si wafer was set between dies and pressed at high temperatures. The Si wafer was pressed by an overweight of 200 N at various temperatures. The deformation regions in which well-shaped (100) and (111) wafers can be obtained by plastic deformation were determined using parameters of thickness and temperature. In order to demonstrate that the shaped wafers are of sufficiently high quality to be used in the preparation of devices, solar cells were fabricated using the hemispherical Si wafers pressed at 1,120°C and 1,200°C. The conversion efficiency of the hemispherical solar cells is 8.5–11.5%. It was clarified from the conversion efficiency of solar cells that the quality of the shaped crystal wafers can be improved by a proper annealing process. Thus, the hemispherical shaped wafers are of high quality to be used in the preparation of devices.

Wafer deformation in ultraviolet-nanoimprint lithography using an element-wise patterned stamp

Nanoimprint lithography is a promising method for high-resolution, low-cost nanopatterning. In particular, ultraviolet-nanoimprint lithography (UV-NIL), which requires low imprint pressure, is effective for multi-layer processes. In this study, we investigated the non-uniformity of the residual layer thickness caused by wafer deformation in an experiment that examined different wafer thicknesses using UV-NIL with an element-wise patterned stamp (EPS). The EPS consisted of a number of elements, each separated by a channel. Experiments using the EPS were performed on an EVG620-NIL. Severe deformation of the wafer served as an obstacle to the spread of resin drops, which caused non-uniformity of the residual layer thickness. We also simulated the imprint process using a simplified model and finite element method to analyze the non-uniformity.

Dynamics of a Bonding Front

A description of the bonding front propagation between two adhesive plates is proposed. The model relates the velocity of a bonding front to the adhesion energy, with application to wafer direct bonding. Its derivation is based on a competition between the bonding energy and the viscous drag of the air flow in the gap between the two wafers. The model describes well the experimental data, including the wafer deformation profile during bonding or the dependence of the velocity on the gas viscosity, pressure, and wafer thickness.

Shaped silicon-crystal wafers obtained by plastic deformation and their application to silicon-crystal lenses

Plastic deformation is an unlikely process by which to mould pristine silicon wafers into three-dimensional shapes owing to the inevitable detrimental impact that the resulting mechanically induced defects would have on their electrical properties. However, if one were to find a way of doing so without substantial degradation of these properties, a range of new applications might be opened up. Here we report on the successful plastic deformation of silicon crystal wafers for the preparation of wafers with various shapes. A silicon wafer was set between dies and pressed at high temperatures. One application of shaped wafers is as well-shaped concave silicon crystal lenses or mirrors. The lattice plane of such a crystal lens has a curvature exactly along the surface. A concave spheroidal X-ray lens, in the form of two-dimensional Johann1,2 and Johansson's2,3 monochromators, is proposed for an X-ray optical component system. We propose and demonstrate a new solar cell system with the concave silicon crystal mirror used as both a solar cell and a focused mirror. This system can make use of the reflected photons from solar cells.

Wave-shaped Si crystal wafers obtained by plastic deformation and preparation of their solar cells

We can prepare wave-shaped crystal wafers by the plastic deformation of Si crystal wafers, and we report on the characteristics of solar cells fabricated using the wave-shaped Si wafers, in order to demonstrate whether the shaped wafers are of high quality to be used in the preparation of devices or not. To obtain wave-shaped Si wafers, graphite dies were used. The diameter of the convex and concave waves formed in the dies is 4mm. The Si wafers were pressed by an overload of 200N. A thickness versus temperature region for obtaining well wave-shaped Si wafers by plastic deformation was determined. Solar cells were prepared using wave-shaped wafers pressed at 1100 and 1200°C. The wafers were annealed at 1109 and 1209°C, respectively, for 1h in a hydrogen atmosphere. The conversion efficiency of the wave-shaped solar cells is 6.0%–10.1%. Thus, it is clarified that the wave-shaped wafers are of high quality to be used in the preparation of devices. The quality of the wafers can be significantly improved by suitable thermal treatments.

Empirical inference of in situ wafer sagging in Si epitaxy using pocket susceptor

An empirical description of wafer sagging during silicon epitaxy using a dish-shaped susceptor pocket is presented. The proposed method is based on the discovery that the process history can be retrieved from the transfer pattern on the wafer backside. The characteristic tree-ring pattern is due to the contact transfer of the susceptor coating to the sagging wafer. Each ring is uniquely identified as a process step and vice versa. The number of rings is related to the growth schedule. The size and shape of the rings are sensitive to the growth conditions. A full picture of the in situ wafer sagging can be reconstructed by examining the transfer pattern after the wafer is unloaded from the reactor. The proposed method has been used to evaluate the wafer deformation in response to changes in the key process variable such as the growth temperature, susceptor geometry and reactor design.

A study of a finite element model for the chemical mechanical polishing process

In this paper, relative velocity at a given point on the wafer was first derived. The revolutions of wafer and pad are assumed the same and the axisymmetric uniformly distributed pressure form is given. Thus, a 2D axisymmetric quasic-static model for chemical-mechanical polishing process (CMP) was established. Based on the principle of minimum total potential energy and axisymmetric elastic stress-strain relations, a 2D axisymmetric quasic-static finite element model for CMP was thus established. In this model, the four-layer structures including wafer carrier, carrier film, wafer and pad are involved. The von Mises stress distributions on the wafer surface were analysed, the effects of axial, hoop, radial and shear stresses to von Mises stress and the effects of axial, hoop, radial and shear strains to deformation of the wafer were investigated. The findings indicate that near the wafer centre, von Mises stress distribution on the wafer surface was almost uniform, then increased gradually with a small amount. However, near the wafer edge, it would decrease in a large range. Finally, it would increase dramatically and peak significantly at the edge. Besides, the axial stress and strain are the dominant factors to the von Mises stress distributions on the wafer surface and the wafer deformation, respectively.

Material removal model for chemical–mechanical polishing considering wafer flexibility and edge effects

This paper describes a two-dimensional, multiscale, material removal model for chemical–mechanical planarization that includes: (i) asperity deformation; (ii) bulk pad deformation; (iii) wafer compliance; (iv) carrier film deformation; (v) slurry flow; (vi) material removal by abrasive particles in the slurry. A finite element method is used to establish the relationship between the contact stress and the deformation of an idealized asperity made of a hyperelastic material. The total local stress due to the multitude of asperities is computed using the Greenwood–Williamson approach. The wafer deformation, bulk pad deformation, and slurry film thickness are then evaluated from the estimated contact stresses and hydrodynamic fluid pressures. The material removal rate on the wafer is computed as a function of position on the wafer. The wafer scale material removal rate results show large changes in rate near the wafer’s edges, as often seen in practice, with very uniform removal across most of the wafer surface. The computational algorithm used to calculate the contact stresses, slurry fluid pressures, material removal rates, and the global force and moment balances is summarized.

Thermoplastic Deformation and Residual Stress Topography of 4H-SiC Wafers

AbstractWe have measured thermoplastic deformation in as-received, single-side polished, 4H-SiC wafers and also residual stresses in homoepitaxially grown epilayers on wafers by radius curvature measurements. The wafers studied had n-type resistivities of 0.010-0.011 ω-cm and p-type resistivities of 4.42, 4.72, 9.57 ω-cm. In a first thermal excursion to 900 °C in vacuum, the bow height of the bare substrates in all cases decreased with temperature. Upon cooling down, however, the bow heights remained largely unchanged from their values at 900 °C. A second cyclic excursion to 900 °C did not yield any significant change in the curvature, thus indicating that the substrates had thermoplastically deformed in the first heating cycle. Epilayers having nitrogen doping between 5 × 1017 and 2 × 1019 cm−3 grown on the n- and p-type substrates resulted in compressive stresses ranging between 190 and 400 MPa in the epilayers. Transmission electron microscopy (TEM) examination of the n-type epilayer (with doping levels of 5 × 1017 cm−3 and 5 × 1018 cm−3) on the n-type substrate, revealed bands of stacking faults (SFs) confined within the epilayers after the bicrystals were further annealed at 1150°C in nitrogen for thirty minutes. These doping levels are approximately one and two orders of magnitude below the reported threshold value of 3 × 1019 cm−3 previously suggested for the onset generation of SFs in annealed n-type 4H-SiC epilayers. The calculated residual stresses in all the epilayers were above the critical stress for the motion of dislocations above 1000 °C in 4H-SiC. Thus the SFs that form by glide of pre-existing partial dislocations may actually be stress induced and occur across a much wider range of doping levels. Therefore, it is possible that a significant mechanism for formation of the stacking faults and 3C bands observed in thermally treated 4H-SiC wafer is stress relief via the generation and motion of new and pre-existing partial dislocations on the basal planes of 4H-SiC.

Strains in macroporous silicon introduced by cyclic oxidation

Regular trends of macroporous silicon wafer deformation under high-temperature oxidation are revealed, and the basic parameters describing the sample bending and subsequent stress relaxation on the oxide removal are determined. High-resolution X-ray diffractometry and topography studies have been used to deduce the sample bending radius and the lattice parameters, and to define the areas of the dislocation generation. On repeated oxidation with intermediate oxide removing, a memory effect has been observed.

Stress and Defect Generation in Si Epitaxy

ABSTRACTA quasi-static model is proposed to describe wafer deformation due to stress build up in the Si epitaxy process. The analysis takes into account temporal stress variations as the wafer sags into the dish-shaped pocket of the susceptor at a deposition temperature above 1100 °C. It is shown that the magnitude of the negative bending moment at the wafer supporting edge decreases over time. As a result, the maximum deflection at the wafer center and the tensile stress at the wafer supporting edge also decrease over time. The generation of slip defects near the wafer edge as the wafer responds the thermal, gravitational and contact stress is explored. A new test methodology is developed to track the time-varying wafer deflection. It allows for the measurement of quality of the susceptor and its fitness for use in the reactor system.

Finite element analysis for grinding and lapping of wire-sawn silicon wafers

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure on silicon wafer manufacturers to develop cost-effective manufacturing processes. A critical issue in wafer production is the waviness induced by wire sawing. If this waviness is not removed, it will affect wafer flatness and semiconductor performance. In practice, both lapping and grinding have been used to flatten wire-sawn wafers. Although grinding is not as effective as lapping in removing waviness, it has many other advantages over lapping (such as higher throughput, fully automatic, and more benign to environment) and has great potential to reduce manufacturing cost of silicon wafers. This paper presents a finite element analysis (FEA) study on grinding and lapping of wire-sawn silicon wafers. An FEA model is first developed to simulate the waviness deformation of wire-sawn wafers in grinding and lapping processes. It is then used to explain how the waviness is removed or reduced by lapping and grinding and why the effectiveness of grinding in removing waviness is different from that of lapping. Furthermore, the model is used to study the effects of various parameters including active-grinding-zone orientation, grinding force, waviness wavelength, and waviness height on the reduction and elimination of waviness. Finally, the results of pilot experiments to verify the model are discussed.

Improving the flatness of silicon backplanes for high quality FLCoS microdisplays

The flatness of silicon backplanes for ferroelectric liquid crystal microdisplays is essential for their commercial success. The various factors affecting the flatness of liquid crystal on silicon backplanes are reviewed. A flattening technique is proposed based on a promising method that employs induced stress of thin films to control the deformation of silicon wafer. Limitations of this technique are discussed.

Computer-controlled lapping system for granite surface plates

This paper describes a two-dimensional, multiscale, material removal model for chemical–mechanical planarization that includes: (i) asperity deformation; (ii) bulk pad deformation; (iii) wafer compliance; (iv) carrier film deformation; (v) slurry flow; (vi) material removal by abrasive particles in the slurry. A finite element method is used to establish the relationship between the contact stress and the deformation of an idealized asperity made of a hyperelastic material. The total local stress due to the multitude of asperities is computed using the Greenwood–Williamson approach. The wafer deformation, bulk pad deformation, and slurry film thickness are then evaluated from the estimated contact stresses and hydrodynamic fluid pressures. The material removal rate on the wafer is computed as a function of position on the wafer. The wafer scale material removal rate results show large changes in rate near the wafer’s edges, as often seen in practice, with very uniform removal across most of the wafer surface. The computational algorithm used to calculate the contact stresses, slurry fluid pressures, material removal rates, and the global force and moment balances is summarized.

314 HRTEM Studies of Plastic Deformation in Silicon Wafers due to Micro Indentation

The plastic deformation of silicon wafers caused by micro-indentation was studied by means of HRTEM. It was shown that under a low maximum indentation load (P_ ) the transformation zone is amorphous but its boundary is rough and nano-crystals of diamond silicon appear near an amorphous / crystalline border. Increasing P_ gives rise to crystalline high-pressure R8/BC8 phases in the transformation zone. The size of high-pressure phase grains varies between 3 nm and 15 nm, suggesting a coherent nucleation and growth mechanism. The micro-deformation outside the transformation zone proceeds by initial distortion of crystalline planes concentrated in nano-zones accompanied by initiation of dislocations that are advanced to slip systems. Details of the microstructure and its effect on the nano-deformation in micro -indentation are also discussed.

Study of a mechanically clamped cryo-chuck device in a high density plasma for deep anisotropic etching of silicon

This article presents a study concerning a cryo-chuck device used in an inductively coupled plasma reactor for deep anisotropic etching of narrow trenches (2 μm wide) in silicon wafers of 5 in. in diameter. Thermal mechanisms in a mechanically clamped cryo-chuck system have been studied. First, wafer deformations have been measured in the chuck device. Deformations occur because of the helium backside pressure allowing thermal transfer to cool the wafer. In a second step, these deformations have been used in calculations considering the heat transfers in the substrate. In a last step, in situ temperature measurements have been made on wafers during a process using a LUXTRON® probe. This study shows the influence of the backside helium gap variation and the clamping ring temperature on the uniformity of substrate cooling.