Wafer Defect Research Articles

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

Passivation of Phosphorus Diffused Black Multi‐Crystalline Silicon by Hafnium Oxide (Phys. Status Solidi RRL 12/2017)

Black silicon texturing formed by reactive ion etching has great promise in providing strong optical gains for multicrystalline silicon solar cells, especially when coupled with diamond wire sawing. However, the resulting nano-scale surface structures are challenging to passivate with silicon nitride by plasma enhanced chemical vapor deposition, the conventional method used in industry. Researchers from the Australian National University and Trina Solar (see article no. 1700296 by Jie Cui et al.) use hafnium oxide, which contains positive charge, appropriate to passivate the phosphorus diffused surface of solar cells, together with atomic layer deposition, to obtain a conformal coating of the sharp surface features. By optimizing the deposition and annealing conditions, the authors have achieved not only a low surface recombination, but also an effective passivation of bulk defects in multi-crystalline silicon wafers, as shown by photoluminescence imaging. They report a recombination current density of J0n+ = 98 fA cm-2 for the phosphorus diffused black silicon surface, which equates to an attainable open circuit voltage of 691 mV, thus proving that hafnium oxide offers a viable alternative for passivating the surface and the bulk of black-textured multi-crystalline silicon solar cells.

Anneal induced transformations of defects in hadron irradiated Si wafers and Schottky diodes

In this research, the anneal induced transformations of radiation defects have been studied in n-type and p-type CZ and FZ Si samples, irradiated with relativistic protons (24GeV/c) and pions (300MeV/c) using particle fluences up to 3 × 1016cm−2. The temperature dependent carrier trapping lifetime (TDTL) spectroscopy method was combined with measurements of current deep level transient spectroscopy (DLTS) to trace the evolution of the prevailing radiation defects. The contactless TDTL technique has been shown to be preferential when the radiation induced trap density approaches or exceeds the dopant concentration and when it is necessary to avoid modification of a detector structure due to annealing processes at elevated temperatures. The deep level spectra were complementarily examined by using DLTS spectroscopy on Schottky diodes made of irradiated Si wafer fragments. The dominant radiation defects and their transform paths under isothermal and isochronal anneals have been revealed. A good agreement between the DLTS and TDTL spectra has been obtained.

Defectivity and Yield Impact From the AMC Inside the FOUP in Advanced Technologies

Historically, much attention has been given to the unit processes and the integration of those unit processes to improve product yield. Less attention has been given to the wafer mini environment, either during processing or post processing. This paper contains a detailed discussion on how particles and airborne molecular contaminants (AMCs) from the wafer mini environment interact and produce undesired effects on the wafer which in turn cause devices to fail. Sources of wafer environmental contamination are the processes themselves, ambient environment, outgassing from wafers, and front open unified pod (FOUP) contamination. Establishing a strategy that reduces contamination inside the FOUP mini environment will decrease defect variability and thus increase yield. In manufacturing ecosystem, changing the FOUP or moving the wafers faster or purging with nitrogen to reduce the impact from mini environment is not always an option. Alternative to having a stop gap, it is desired to understand the AMCs and thus exploring sustainable solutions to minimize them below certain thresholds that would cause impact on wafer. NH3-based contamination, extensively discussed in this paper, is observed to cause wafer defects. Thus, explicit knowledge of AMC type is critical, as the most optimized methodology to control various AMCs might not always be the same. Three primary variables that greatly impact this strategy are FOUP contamination mitigation, FOUP material, FOUP metrology, and cleaning method.

Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned Wafers

The ability to rapidly detect both printable EUV mask adder defects as well as mask absorber defects across the entire mask image field is a key enabler for EUV lithography. Current optical wafer-based inspection techniques are only capable of detecting repeater defects on a die-to-die basis for chiplets within the image field. Larger server-type chips that encompass the entire mask image field cannot rely on such a scheme, since the presence of the defect in every die prevents their detection. In this paper, a prototype optical wafer defect inspection methodology designed to detect repeater defects over the entire image field, termed die-to-baseline reference die (D2BRD), is investigated. The sensitivity of this inspection technique is demonstrated and compared to eBeam inspection over a range of defect sizes for both opaque and clear type mask absorber programmed defects. Moreover, the D2BRD methodology is used to monitor printing defect adders present in a lithographic defect test mask, as well as 7-nm BEOL layers. Using defect repeater analysis, SEM review and patch image classification of full chip wafer inspections over several mask cycles, the D2BRD scheme is shown to allow the unambiguous identification of mask adder defects, while suppressing random process defects. This methodology has the potential to define the risk assessment of mask adder defects in the absence of an EUV pellicle, and can play an integral part of the wafer print protection strategy.

Generation and elimination of silicon pitting for 300 mm CMOS process technologies

The complementary metal oxide semiconductor (CMOS) process technology in a 300 mm wafer fab experienced wafer center yield loss. In-line wafer defect inspection revealed gross silicon pitting at the wafer center as the root cause of the yield loss. Affected dies showed pitting at the interfacial corner between the silicon substrate and the isolation oxide. The mechanism of silicon pitting involves creation of silicon microdefects during several high-temperature furnace anneal process steps (liner oxide and posthigh energy phosphorus implant anneals) because of local die and global wafer level thermally induced mechanical stress at the silicon substrate to isolation oxide interfacial corner. In addition, implant-induced silicon microdefects from a high energy (>2 MeV) phosphorus implant, extending to the silicon surface provide a further significant contribution to the silicon microdefect population. The overall microdefect population is further aggravated by Ostwald ripening during a subsequent thick silicon-oxide furnace growth process, resulting in sufficient corner silicon microstructure damage to enhance wet-etching during a subsequent wet-clean leading to gross silicon pitting. Silicon pitting is eliminated by lowering either the liner oxide or postimplant anneal temperatures or skipping the high energy phosphorus implant. Incorporating a reduced liner oxide anneal temperature into the CMOS process flow eliminated the wafer-level yield loss at the wafer center associated with gross silicon pitting defects.

Potential process design and control for solar cell lean production in future

In this paper, the correlation between wafer quality and cell efficiency was studied to identify the key impact factors, such as effective lifetime, impurities and defects. Standard (STD, 2.94E21atoms/cm3) and lightly doped emitter (LDE, 1.08E21atoms/cm3) diffusion were investigated for different qualities wafers. For high impurities wafer, cell efficiency of STD diffusion is 0.44%_abs higher than that of LDE diffusion due to the better gettering by bulk lifetime and iron concentration measurement; for high defect wafer, cell efficiency of STD and LDE are similar; for good wafer (high lifetime, low defect and low impurities), LDE diffusion is better than STD with 0.08%_abs higher cell efficiency due to the better blue wavelength response by using IQE measurement, which should be higher if optimizing firing condition for Fill Factor improvement. Therefore, the possible wafer sorting provides opportunities to design and control different cell process for different incoming wafers to enable the best possible output in a lean production in future.

Semiconductor Wafer Defect Classification Using Support Vector Machine with Weighted Dynamic Time Warping Kernel Function

Semiconductor Wafer Defect Classification Using Support Vector Machine with Weighted Dynamic Time Warping Kernel Function

Ranking process parameter association with low yield wafers using spec-out event network analysis

Abstract In the semiconductor process, the time-series process sensor data such as temperature, pressure, and voltage, are analyzed, to find suspicious process parameters associated with low yield wafers. A common approach is to compute correlation between individual spec-out events and defect ratios. However, the downside with this approach is that it ignores interactions among spec-out events, leading to each spec-out event being independently administrated. In this paper, we propose a novel approach that incorporates the interactions among spec-out events using spec-out event network analysis. We construct a weighted directed graph in which a spec-out event is represented as a node, a precedence relation between events as a directed edge, and the wafer defect ratio corresponding to the relation as an edge weight. In this graph, a more important node in the process will have more links from other succeeding nodes with high defect ratios. The PageRank algorithm run on this event network results in a ranking of association with wafer defects. We validated the performance using real-production data from a 32 nm device. The proposed method enables process engineers to determine the root causes of low yield wafers due to the interactions of the process steps.

Sensitivity enhanced FTIR investigation of defects introduced by RTA pre-treatment in Czochralski silicon wafers

The investigation of vacancy oxygen complexes in silicon wafers by FTIR is not easy because their concentration is close to the detection limit. In order to enhance the sensitivity of the FTIR measurement we investigated stacked samples of about 1 cm thickness at temperature close to liquid helium temperature. This method was applied to study the absorption bands of defects in as-grown silicon wafers, rapid thermal annealing (RTA) pre-treated wafers, and in RTA pre-treated wafers with subsequent anneals at 800 °C for short periods. We found that the RTA pre-treatment at 1250 °C could not fully annihilate the thermal double donors which were present in the as-grown wafer. By RTA at 1100 °C annihilation was possible. In the wafer pre-treated by RTA at 1250 °C we found the absorption bands of VO4 at 985 cm−1 and 991 cm−1 in the measurements carried out at room temperature and at 6 K, respectively. In this wafer we also detected an unknown band at 1030 cm−1. The VO4 band and the unknown band at 1030 cm−1 disappeared immediately after annealing at 800 °C for 10 min. Instead, the bands at 1096 and 1099 cm−1, both assigned to VO5,6, appeared. These bands are already present in the as-grown sample but their absorption coefficient decreases during RTA at 1100 °C. In samples annealed at 800 °C for 30 min or longer a new absorption band at 1053 cm−1 appears which can be also assigned to VO5,6 complexes.

Oxygen-related defects in n-type Czochralski silicon wafers studied by hyperspectral photoluminescence imaging

Oxygen-related Thermal Donors in n-type Czochralski silicon (Cz-Si) wafers have been investigated using hyperspectral photoluminescence imaging and OxyMap. Thermal Donors give rise to two photoluminescence emissions, one narrow peak at 0.767 eV, and one broad band with centre peak at 0.72 eV that is also measurable at room temperature. The spectral imaging was first carried out on the sample cooled to 90 K, then repeated at room temperature (300 K). The possibility to delimitate at room temperature defects-rich zones with hyperspectral photoluminescence imaging is evidenced.

Tolerance limits under Poisson regression based on small-sample asymptotic methodology

ABSTRACTThis article explores the calculation of tolerance limits for the Poisson regression model based on the profile likelihood methodology and small-sample asymptotic corrections to improve the coverage probability performance. The data consist of n counts, where the mean or expected rate depends upon covariates via the log regression function. This article evaluated upper tolerance limits as a function of covariates. The upper tolerance limits are obtained from upper confidence limits of the mean. To compute upper confidence limits the following methodologies were considered: likelihood based asymptotic methods, small-sample asymptotic methods to improve the likelihood based methodology, and the delta method. Two applications are discussed: one application relating to defects in semiconductor wafers due to plasma etching and the other examining the number of surface faults in upper seams of coal mines. All three methodologies are illustrated for the two applications.

Cathodoluminescence study of killer defects in GaN wafers on sapphire substrates

GaN films grown on sapphire substrates were characterized using cathodoluminescence (CL) to identify killer defects in GaN wafers. Dislocations and two types of hexagonal pit, V‐pits and U‐pits, were observed. The optical properties of these pits were clarified by planar observation. The generation and annihilation of the pits were elucidated from the cross sectional observation.The cross sectional CL image to identify generation and annihilation of pit‐type defects.

Exploration of Bulk and Epitaxy Defects in 4H-SiC Using Large Scale Optical Characterization

In this work, aggregate epitaxial carrot distributions are observed at the crystal, wafer and dislocation defect levels, instead of individual extended carrot defect level. From combining large volumes of data, carrots are observed when both threading screw dislocations (TSD) and basal plane dislocations (BPD) densities are locally high as seen in full wafer maps. Dislocation density distributions in areas of carrot formation are shown, and suggest TSD limit the formation of carrots in regions containing BPD. These data also add support for mechanisms requiring the need for both dissociated BPD and TSD for carrot formation.

Evaluation and Reduction of Epitaxial Wafer Defects Resulting from Carbon-Inclusion Defects in 4H-SiC Substrate

In this study, we investigated the epitaxial surface defects resulting from the carbon-inclusion defects in 4H-SiC substrate. Most carbon-inclusion defects developed into one of three types of epitaxial surface defects under normal epitaxial growth conditions. Among them, we found a regular hexagonal pit by high-resolution microscopy, which we regarded as a large-pit defect, and which had an adverse impact on the reverse electrical characteristics of Schottky barrier diodes. Conversion of a carbon-inclusion defect to a large-pit defect or a triangular defect could be reduced by reducing the C/Si ratio.

Enhanced Cleaning for the Point-of-Use Filter and its Effectiveness on Wafer Defectivity in Immersion ArF Lithography Process

Enhanced Cleaning for the Point-of-Use Filter and its Effectiveness on Wafer Defectivity in Immersion ArF Lithography Process

Investigation of Plane Defects in a Dielectric Wafer by Spectral-Domain Integral Equation Method

The spectral-domain volume integral equation is used to develop a computer model for investigating the scattering properties of plane objects in the form of elliptical cylinders embedded in a dielectric wafer. The features of the model are demonstrated for particles of different materials and different shapes.

Hyperspectral photoluminescence imaging of defects in solar cells

The present work is a demonstration of how near infrared (NIR) hyperspectral photoluminescence imaging can be used to detect defects in silicon wafers and solar cells. Chemometric analysis techniques such as multivariate curve resolution (MCR) and partial least squares discriminant analysis (PLS-DA) allow various types of defects to be classified and cascades of radiative defects in the samples to be extracted. It is also demonstrated how utilising a macro lens yields a spatial resolution of 30 µm on selected regions of the samples, revealing that some types of defect signals originate in grain boundaries of the silicon crystal, whereas other signals show up as singular spots. Combined with independent investigation techniques, hyperspectral imaging is a promising tool for determining origins of defects in silicon samples for photovoltaic applications.

The effect of AlN nucleation temperature on inverted pyramid defects in GaN layers grown on 200 mm silicon wafers

We have examined 200mm GaN on silicon wafers, while varying the AlN nucleation temperature, and have found that higher temperatures result in a more convex bow on the wafers. In addition, by performing full wafer defect mapping, we have found that a higher nucleation temperature results in a higher density of inverted pyramid defects, which have previously been found to reduce the breakdown voltage of GaN on silicon layers.We have performed electrical measurements on a wafer with the lowest temperature AlN layer, which is still within our bow specification, and which therefore has the lowest density of inverted pyramid defects. This wafer showed the same leakage current density for both very small and very large test structures (2×10−3 and 18.7mm2 respectively), with all but one of our large structures maintaining a breakdown voltage greater than 700V. This is a very promising result for high yield of devices on 200mm GaN on silicon wafers.

Identification of lifetime limiting defects by temperature- and injection-dependent photoluminescence imaging

Identification of the lifetime limiting defects in silicon plays a key role in systematically optimizing the efficiency potential of material for solar cells. We present a technique based on temperature and injection dependent photoluminescence imaging to determine the energy levels and capture cross section ratios of Shockley–Read–Hall defects. This allows us to identify homogeneously and inhomogeneously distributed defects limiting the charge carrier lifetime in any silicon wafer. The technique is demonstrated on an n-type wafer grown with the non-contact crucible (NOC) method and an industrial Czochralski (Cz) wafer prone to defect formation during high temperature processing. We find that the energy levels for the circular distributed defects in the Cz wafer are in good agreement with literature data for homogeneously grown oxide precipitates. In contrast, the circular distributed defects found in NOC Si have significantly deeper trap levels, despite their similar appearance.