Vth Uniformity Research Articles

Excellent Reliability Characteristics of Ovonic Threshold Switch Device with Higher‐Temperature Forming Technique

Amorphous chalcogenide‐based ovonic threshold switch (OTS) has significant potential as a selector device in high‐density memory arrays. However, to realize the ideal selector device, OTS still needs to enhance its reliability characteristics such as device uniformity and threshold voltage (Vth) drift. Herein, the effect of elevated temperature forming on the selector characteristics of an OTS device is investigated. The findings indicate that the reliability performance of the device significantly improves when the forming process is conducted at higher temperature. In particular, it shows excellent Vth uniformity (σ = 32 mV) and a notable enhancement in the Vth drift characteristics. Based on trap analysis at cryogenic temperature (77 K), it is confirmed that improved reliability characteristics can be attributed to the stability of the activated trap formed by the HT forming process.

38.1: Invited Paper: Research progress of high‐performance Metal Oxide for Micro‐LED

In this work, high‐mobility oxide backing‐plate with pulse‐hybrid‐modulation (PHM) driving circuit has been well applied in CSOT G4.5 production line. The self‐aligned top‐gate (SATG) thin film transistor (TFT) exhibits linear mobility over 30 cm2 V‐1 s‐1 , excellent Vth uniformity 0.3±0.2V and PBTS/NBTIS <1.5 V/h. The PHM driving circuit significantly improves the low‐gray uniformity and the color gamut shift of Micro‐LED (MLED) under low‐current density. In addition, a 19 inch spliced MLED panel has been demonstrated, in which color gamut >120% NTSC, pixel pitch 0.4 mm, contrast ratio >1000000:1, invisible border and splicer.

(Invited) Highly Stable Self-Aligned Top-Gate Indium Gallium Zinc Oxide Thin-Film Transistors for High-Resolution OLED TV and Mobile Displays

Indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted much attention because of their high electron mobility values (> 10 cm2/Vs) and because they can be processed at low temperature to produce large-area displays with the potential of low production costs. The IGZO TFTs require smaller RC signal delay with shorter channel length for high-resolution display applications. Therefore, it’s necessary to use self-aligned top-gate (TG) oxide TFT structure with smaller channel length for high-resolution, high-speed, low-power, and narrow-bezel displays. The IGZO TFTs also need good electrical stability under positive/negative bias temperature stress (P/NBTS) with decent TFT properties for peripheral gate driver integrated large size organic light emitting diode (OLED) TVs. TG IGZO TFTs for display applications such as OLED TVs typically use longer channel length (> 4 µm) due to negative threshold voltage (Vth) shift and Vth non-uniformity issues with smaller channel length, which is mainly caused by hydrogen diffusion near source/drain regimes during device integration. We fabricated TG IGZO TFTs by using Applied Material’s CVD/PVD tools to achieve excellent electrical stability and Vth uniformity by balancing oxygen and hydrogen diffusion into oxide channel layer such as IGZO. Suppressing carrier densities at the interface between gate insulator (GI) and IGZO by increasing oxygen diffusion with IGZO pre-annealing in air and TFT post anneal in air, and by minimizing vacuum annealing impact during GI deposition makes the IGZO TFTs more resistive with more positive Vth shift. On the other hands, more hydrogen diffusion into IGZO from GI, ILD, and passivation layers during device integration or TFT post annealing makes the IGZO TFTs more conductive with more negative Vth shift and worse Vth uniformity, but it helps to improve electrical stability with smaller Vth shift under PBTS by passivating defects inside IGZO. Therefore, there is trade-off between Vth uniformity and electrical stability due to the dominance of the diffusion between oxygen and hydrogen. By balancing the diffusion of oxygen and hydrogen, the IGZO TFTs can minimize negative Vth shift even with shorter channel for high-resolution display applications and achieve good electrical stability for pixel and peripheral gate driver circuits integrated in display panel. We successfully demonstrated excellent electrical properties such as high mobility (µFE), low sub-threshold slope (SS), good threshold voltage (Vth) position, and low off-leakage current from TG IGZO TFTs. The positions of Vth can be optimized by controlling carrier densities at the interface between GI and IGZO during device integration even with different GI temperature and power (Fig. 1). Here, GI type A is deposited at a low temperature of 225 ºC with a high RF power of 2400 W. GI type B is deposited at a high temperature of 270 ºC with a high RF power of 2400 W. GI type C is deposited at a high temperature of 270 ºC with a low RF power of 1600 W. In order to investigate the channel length dependency of Vth, Vth values were extracted from transfer characteristics at VDS = +1 V with various TFTs by fixing channel width of 12 µm and varying the channel length from 10 µm down to 3 µm. The differences between maximum Vth and minimum Vth, Vth (Max–Min), from GI type A, B, and C are 0.35 V, 0.48 V, and 1.20 V, respectively. Total resistance in TFTs was extracted from the measured IDS values by varying VGS from 12 V to 20 V with channel length from 10 µm down to 5 µm by transmission line method. Extracted 2∆L, the difference between mask channel length and effective channel length, from GI type A, B, and C are 0.78 µm, 0.87 µm, and 1.05 µm, respectively. The IGZO TFTs with higher GI power show better TFT uniformity than lower power GI without notable negative Vth shift and non-uniformity even with shorter channel length from 10 µm down to 3 µm by minimizing hydrogen diffusion into IGZO (Fig. 2). The IGZO TFTs with lower GI power show better stability under PBTS due to more hydrogen diffusion into IGZO. On the other hands, the IGZO TFTs show better stability under both PBTS and NBTS with higher GI temperature than lower temperature GI due to more hydrogen diffusion into IGZO (Fig. 3). Therefore, high power/high temperature GI is preferred for high-resolution mobile/VR displays considering short channel length effect and low power/high temperature GI is preferred for gate driver integrated OLED TVs considering stability, especially PBTS. Figure 1

P‐1.16: Top‐gate Self‐aligned InGaZnO TFTs with Copper Light Shield Layer

In this paper, top‐gate self‐aligned a‐IGZO TFTs with copper light shield layer were fabricated. In order to prevent Cu oxidation phenomenon, a SiNx buffer interlayer layer was added. TFT with SiNx buffer interlayer shows excellent VTH uniformity on Gen. 4.5 glass and good PBTS and NBTIS reliability. After these optimization of the thickness of SiNx layer, the Vth shift of PBTS and NBTIS could be improved to 0.5 V and ‐0.8 V.

15.4: Fabrication of 5.5‐inch AMOLED Panel using IGZO TFTs

We have sucessfully developed 5.5‐inch AMOLED display by utilizing IGZO (Indium‐Gallium‐Zinc‐Oxide) transistor. In order to verify the metal oxide TFTS for AMOLED applications, the OLED evaporation and further processes are employed to complete the display panel. This IGZO TFT device with excellent Vth uniformity on a Gen6 glass.The Vth deviation of TFTs in panel is only 0.65V.

P‐4: Reliability Analysis and Improvement of Self‐aligned Coplanar a‐IGZO TFTs for OLED Display

A TG‐SA a‐IGZO TFT technology is demonstrated with a good VTH uniformity in the whole 14” OLED panel and a high reliability of +0.03V and −0.52V under PBTS and NBTIS, respectively. Mechanisms for device instability and the relative relationship between PBTS and NBTIS have been systematically analyzed. Finally, the prototype 14″ FHD OLED display with an excellent brightness uniformity using TG‐SA a‐IGZO TFTs backplane have been made successfully. Besides, the high reliability of devices have been confirmed through a longtime RA test without no obvious defects generated, which indicates excellent mass‐production prospect.

P-2: Novel High Mobility Oxide TFT with Self-Aligned S/D Regions Formed by Wet-etch process

In this paper, we investigated the high mobility InGaSnO TFTs with self-aligned source/drain regions (n+−IGTO) formed by wet etch process. We compared the electrical characteristics of n+−IGTO formed by dry-etch and wet-etch. The resistivity and thermal stability of n+−IGTO by wet-etch was comparable to the conventional dry-etch, 5.3x10-3Ω·cm and 109%. The proposed IGTO TFTs exhibited high mobility of ∼20cm2/Vs, 0.47V of Vth uniformity on Gen.2 and 0.9V of PBTS 1hr reliability.

P-11: Development of IGZO ESL Type TFTs at G8.5 for 55” AMOLED TVs

The ESL type IGZO oxide semiconductor TFTs with high Vth uniformity of delta Vth less than 1V, and high reliability has been developed at BOE G8.5 for 55inch AMOLED TVs. The mobility was ~10 cm2/Vs, the threshold voltage (Vth) shifts of BTS were successfully reduced to less than 1V and the Vth shifts of hysteresis were less than 0.1V. Furthermore, 55inch AMOLED TVs based on ESL type IGZO TFTs were produced with external compensation circuits.

51.2: The Development of a High Mobility Zinc Oxynitride TFT for AMOLED

TFTs with zinc oxynitride (ZnON) as active layer were developed, and a saturation mobility over 50 cm2/Vs was achieved. The ZnON TFTs show superior I‐V performance and Vth uniformity. A 14 inch WOLED panel driven by ZnON TFT was demonstrated. The reliability of ZnON panels was evaluated at high‐temperatureoperation and low‐temperature‐operation conditions, and satisfied results were achieved.

Normally off AlGaN/GaN HEMT on Si substrate with selectively dry-etched recessed gate and polarization-charge-compensation δ-doped GaN cap layer

We demonstrate a recessed-gate normally off AlGaN/GaN high-electron-mobility transistor (HEMT) on a silicon substrate that provides a precisely controllable threshold voltage (Vth). To ensure Vth uniformity, dry-etching of GaN with high etching selectivity between GaN and AlGaN is developed. Furthermore, to introduce selective dry-etching in the HEMT fabrication process, we propose a delta-doped GaN cap structure that enables negative polarization charges between the GaN cap and the AlGaN barrier to be compensated. Combining these two technologies, we fabricate recessed-gate normally off metal–insulator–semiconductor HEMTs with a subthreshold slope of 130 mV/dec and an on–off drain current ratio exceeding 107.

Effect of Grain Growth Control by Atmospheric Micro-Thermal- Plasma-Jet Crystallization of Amorphous Silicon Strips on TFT Characteristics

INTRODUCTION.For large area electronics on glass substrate, improvement of thin film transistor (TFT) performance is a key technological issue because higher resolution and functionality, such as 500 pixels per inch (ppi) displays, are required. Low temperature poly-silicon (LTPS) technology is quite promising in terms of high mobility (μFE ), high reliability and CMOS capability. However, present LTPS technology, based excimer laser annealing (ELA) technique, must solve the cost and variability issues. We have proposed micro-thermal-plasma-jet (µ-TPJ) technique for crystallization of amorphous silicon (a-Si) films [1]. Because of its simple structure and atmospheric pressure process, µ-TPJ enables low cost fabrication compared with ELA technique. We have demonstrated zone-melting recrystallization (ZMR) of a-Si by µ-TPJ irradiation [2]. However, ZMR forms random grain boundaries (GBs), which cause characteristic variability in TFTs. To solve these issues, we have attempted to control the grain growth by µ-TPJ crystallization of a-Si strip pattern and demonstrated CMOS circuit operation with high integrity and high frequency for peripheral circuit of displays [3]. In this work, we investigated in detail characteristics of TFTs with conventional and strip pattern. EXPERIMENTAL.A 200-nm-thick a-Si films were formed on quartz substrate and were patterned to form source, drain and channel. Then, 3×1012/cm2 phosphorus ions and boron ions were implanted in PMOS and NMOS respectively, because non-doped channel behaved as intrinsic P-type nature by this fabrication process [3]. After dehydrogenation at 450 °C, a-Si patterns were crystallized by µ-TPJ irradiation. In this condition, ~200 μm wide molten zone is formed and rapid re-crystallization to lateral direction is induced by the fast movement of molten Si. Here, we formed conventional and 1μm wide strip channel patterns before crystallization. After fabrication process [3], we compared electrical property and channel crystallinity. Crystallographic orientations and GBs were investigated by electron backscattering diffraction (EBSD) method. And TFT characteristics with respect to channel width (W) of both patterns were investigated. RESULTS AND DISCUSSION. In conventional pattern TFT, reduced field effect mobility (μFE ) and threshold voltage (Vth ) shift with respect to W were observed (Fig.1 (a)). On the other hand, strip pattern showed stable characteristics in all W (Fig.1 (b)). As shown in Fig.2, random GB were formed in W>3µm, but were clearly suppressed in narrow strips. In addition, strip pattern suppressed off leak current and showed high on current compared to conventional pattern. While μFE and Vth varied by increasing of W in conventional pattern, stable characteristics of μFE > 350 cm2/Vs, Vth = 3.6 ± 0.1V and outputs were obtained in strip pattern. In consideration of drawback of area loss by strip pattern, high μFE , low Vth and stable outputs are sufficient to compensate it as understood by the output characteristics (Fig.3). In addition, although the kink effect increased by degradation of Vth in conventional pattern (Fig.3 (a)), they were significantly suppressed in strip pattern by its uniformity of Vth (Fig.3 (b)). Thus, strip pattern is quite promising for layout and operation of CMOS circuit with high reliability. CONCLUSIONS.The µ-TPJ irradiation to a-Si strip pattern is quite effective for grain growth control. TFTs with proposed pattern showed high performance and low characteristics variability. This enabled us to operate CMOS circuit on insulating substrate under low supply voltage and high frequency. ACKNOWLEDGEMENTS. A part of this work was supported by Research Institute for Nanodevice and Bio Systems (RNBS), Hiroshima University and Funding Program for Next Generation World-Leading Researchers (NEXT Program) from the Japan Society for the Promotion of Science (JSPS). REFERENCES. [1] S. Hayashi, et al., Appl. Phys. Express 3(2010) 061401.[2] Y. Fujita, et al., Jpn. J. Appl. Phys. 51(2012) 02BH05.[3] S. Morisaki, et al., 10th Int. Thin-Film Transistor Conf. (2014) 15.

Normally-off GaN MOSFETs on insulating substrate

Several types of GaN MOSFETs with normally-off operation have been fabricated on insulating substrate and evaluated. In recessed-gate GaN MOSFET, the threshold voltage (Vth) can be easily controlled, but the current drivability is modest and needs to be improved by adopting appropriate device structure and/or process. We achieved enhanced performance by combining the recessed-gate technology with additional processes, such as: (i) the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, (ii) the post-deposition annealing of gate oxide to decrease the gate leakage current, (iii) the re-growth of n+-GaN layer for source/drain to improve the access resistance and Vth uniformity, (iv) the stress-control technology to secure high 2-D electron–gas density (2DEG) on source/drain and decrease the series resistance, and (v) the use of the p-GaN back-barrier to decrease the buffer leakage current. We also present the characteristics of GaN-based FinFETs with very narrow fin.

RECESSED-GATE NORMALLY-OFF GaN MOSFET TECHNOLOGIES

We have fabricated and investigated several types of GaN MOSFETs with normally-off operation. The recessed-gate GaN MOSFET is preferred for normally-off operation, because the threshold voltage (Vth) of the device can be easily controlled, but it suffers from relatively modest current drivability which must be improved by adopting appropriate device structure and/or process. Enhanced performances have been achieved in this work by combining the recessed-gate technology with additional processes, such as: the post-recess tetramethylammonium hydroxide (TMAH) treatment to remove the plasma damage, the post-deposition annealing of gate oxide to decrease the gate leakage current, the re-growth of n+ GaN layer for source/drain to improve the access resistance and Vth uniformity, the stress control technology to achieve extremely high 2-D electron-gas density (2DEG) on source/drain and decrease the series resistance, and the use of the p- GaN back-barrier to decrease the buffer leakage current. The GaN -based FinFET with very narrow fin was also investigated as a possible candidate for high performance normally-off GaN MOSFETs.

Effect of Buffer or Barrier Layer on Bistability for Nonvolatile Memory Fabricated with Al Nanocrystals Embedded in α-NPD

ABSTRACTRecently, low molecular organic non-volatile memories have been developed as a next generation of non-volatile memory because of nano-meter device-feature size and nano-second access and store-time. We developed a non-volatile memory fabricated with the device structure of Al/ α-NPD/Al nano-crystals surrounded by Al2O3/α-NPD/Al, where α-NPD is N,N'-bis(1-naphthyl)-1,1'biphenyl4-4”diamine. One layer of Al nano-crystals with ∼20 nm-width ∼20 nm length was uniform produced between α-NPD layers, confirmed by 1.2MV high voltage transmission-electron-microscope. This device showed Vth of 3.0 V, Vprogram of 4.3 V, and Verase of 6.3 V. Particularly, this device exhibited an excellent non-volatile memory behavior performing the bi-stability (Iprogrm/Ierase) of >1×102, program/erase cycles of >1×105 and multi-levels. In addition, previous reports about low molecular organic non-volatile memories have showed a bad reproducible memory characteristic. However, this issue was completely solved via isolating Al nano-crystals embedded in α-NPD by O2 plasma oxidation. The uniformity of Vth, Vp, and Ve were 9.91%, 6.94% and 7.92%, respectively. Furthermore, the effect of buffer or barrier layer on non-volatile memory characteristics was investigate to examine the control ability for Vth, Vp, and Ve. The 0.5-nm LiF showed a barrier layer behavior suppressing the bi-stability of non-volatile memory. Otherwise, 15-nm CuPc exhibited a buffer layer behavior enhancing the bi-stability of nonvolatile memory.

RIE gate-recessed (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs double doped-channel FETs using CHF3+BCl3 mixing plasma

BCl/sub 3/+CHF/sub 3/ gas mixtures for the reactive ion etching process were applied to the gate-recess for fabricating (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P quaternary heterostructure double doped-channel FET's (D-DCFET), where a high uniformity of Vth was achieved. With the merits of this wide bandgap (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer, microwave power performance of this heterostructure D-DCFET demonstrates a compatible performance for devices fabricated on AlGaAs/InGaAs heterostructures.

High-performance Ka-band monolithic low-noise amplifiers using 0.2-μm dry-recessed GaAs PHEMTs

Ka-band ultra-low-noise amplifiers fabricated with a manufacturable dry-recess process are presented. Low-damage selective dry etching was used for gate recess to achieve uniform threshold voltage (Vth) and saturation current (I/sub dss/). Threefold improvement in Vth uniformity was achieved in comparison with the wet recess process. Fabricated PHEMT low-noise amplifiers (LNAs) employing 0.2-μm mushroom gates showed an average noise figure of 2.2 dB from 31-36 GHz with an associated gain of 22.5 dB. At the design frequency of 35 GHz, the noise figure was less than 2 dB. This is among the best results ever reported for Ka-band LNA's.

High uniformity of threshold voltage for GaAs/AlGaAs high electron mobility transistors grown on a Si substrate

We report on a study of microscopic distribution of threshold voltage ( Vth) for GaAs/AlGaAs high electron mobility transistors (HEMTs) on a Si substrate grown by metal-organic chemical vapor deposition (MOCVD). Using selective dry etching, the superior microscopic distribution of Vth comparable to that for GaAs substrates is obtained, namely the standard deviation of threshold voltage (σ Vth) of 8.96 mV with the Vth of −101.3 mV for 150 points of the HEMT in a 1.95×1.9-mm2 area. From the evaluation of macroscopic (full wafer) and microscopic Vth distribution, high-density dislocations in the GaAs/Si are found not to affect the uniformity of Vth. This result indicates that HEMT/Si technology has a potential to lead the GaAs/Si to GaAs integrated circuit applications in which large-diameter wafers are beneficial.

Annealing technology under arsenic overpressure for GaAs LSI–influence on dislocation and threshold voltage

AbstractSince the microscopic uniformity of the threshold voltage (Vth) of an FET is important to obtain GaAs LSI, the cause of the threshold voltage uniformity was researched by investigating the annealing dependencies of the dislocations in the semiinsulating substrate of LEC GaAs and the microscopic uniformity of Vth. Annealing under arsenic overpressure decreased the dislocation density on the substrate surface and formed a uniform distribution of dislocations. This is believed to be caused by the supply of arsenic to the substrate surface. When annealing was carried out under low arsenic pressure, Vth shifted toward the negative direction at the area with clustered pits, and a clear dislocation network was formed. On the other hand, when annealing was carried out under arsenic overpressure using arsene, the shift of Vth in a negative direction becomes small and Vth was distributed uniformly. When annealing was carried out using a protective PCVD SiNx film, the distribution of Vth was consistently uniform, regardless of the dislocation distribution. As described in the preceding, it was found that a high concentration of AsGa exists in the area of the clustered pits, the uniformity of Vth is independent of the dislocation density but dependent on the stoichiometry of the substrate prior to or after annealing, and the distribution of Vth becomes more uniform with an increase of arsenic concentration.