Volume Trap Density Research Articles

Impact of Gate Oxide Thickness on Flicker Noise (1/f) in PDSOI n-channel FETs

This work reports the impact of gate oxide thickness on flicker noise (1/f) in 45-nm RFSOI NFET devices. In addition, the effect of finger width scaling on 1/f noise parameters is studied in linear region. The dominant source of 1/f noise is also analyzed. It is observed that thin oxide devices show carrier number fluctuation; however, for thick oxide devices, correlated number-mobility govern the noise. Extracted trap densities using 1/f noise show higher volume trap densities in thin oxide devices. Moreover, trap distribution behavior is analyzed using frequency exponent. Further, GLOBALFOUNDRIES PDK is utilized to model 1/f noise behavior of the devices.

Observation of interface trap reduction in fluoropolymer dielectric organic transistors by low-frequency noise spectroscopy

This study examines the low-frequency noise characteristics of the 2,7-dioctyl[1] benzothieno[3,2-b][1] benzothiophene organic thin-film transistor (OTFT) having a CYTOP dielectric layer. Specifically, the fabricated OTFT exhibits 1/f noise, and its behavior is explained via a carrier number fluctuation model. Additionally, the volume trap density (NT) of the gate dielectric is quantitatively evaluated and compared with its counterpart having SiO2 dielectric layer. The analysis of the results shows that the hydrophilic entities of the dielectric layer strongly influence the NT, while the CYTOP having hydrophobic properties provides less NT than that of SiO2.

Impact of Charge-Trapping Effects on Reliability Instability in AlxGa1-xN/GaN High-Electron-Mobility Transistors with Various Al Compositions.

In this study, we present a detailed analysis of trapping characteristics at the AlxGa1-xN/GaN interface of AlxGa1-xN/GaN high-electron-mobility transistors (HEMTs) with reliability assessments, demonstrating how the composition of the Al in the AlxGa1-xN barrier impacts the performance of the device. Reliability instability assessment in two different AlxGa1-xN/GaN HEMTs [x = 0.25, 0.45] using a single-pulse ID-VD characterization technique revealed higher drain-current degradation (∆ID) with pulse time for Al0.45Ga0.55N/GaN devices which correlates to the fast-transient charge-trapping in the defect sites near the interface of AlxGa1-xN/GaN. Constant voltage stress (CVS) measurement was used to analyze the charge-trapping phenomena of the channel carriers for long-term reliability testing. Al0.45Ga0.55N/GaN devices exhibited higher-threshold voltage shifting (∆VT) caused by stress electric fields, verifying the interfacial deterioration phenomenon. Defect sites near the interface of the AlGaN barrier responded to the stress electric fields and captured channel electrons-resulting in these charging effects that could be partially reversed using recovery voltages. The quantitative extraction of volume trap density (Nt) using 1/f low-frequency noise characterizations unveiled a 40% reduced Nt for the Al0.25Ga0.75N/GaN device, further verifying the higher trapping phenomena in the Al0.45Ga0.55N barrier caused by the rougher Al0.45Ga0.55N/GaN interface.

Implementation of High‐Performance Solution‐Processed Amorphous Indium–Gallium–Zinc–Oxide Thin‐Film Transistors with Low Charge Traps by Microwave Heat Treatment of Low Thermal Budget

Herein, high‐performance solution‐processed amorphous indium–gallium–zinc–oxide (a‐IGZO) thin‐film transistors (TFTs) with low trap densities due to post‐deposition annealing (PDA) are processed with a low‐thermal‐budget microwave (MW) heat treatment. To verify the MW effectiveness, the composition ratio of a‐IGZO thin films and the electrical characteristics of TFTs prepared by conventional thermal annealing (CTA) are compared. An X‐ray photoelectron spectroscopy (XPS) analysis reveals that MW annealing (MWA) improves the film quality more effectively than CTA. a‐IGZO TFTs treated by MWA or CTA are fabricated to evaluate their electrical characteristics. MWA is more effective than CTA in improving the performance, such as hysteresis, subthreshold swing (SS), field effect mobility (μ FE), and on/off current ratio (I on/I off). MWA provides lower interfacial trap density (D it) and volume trap density (N t) than CTA. To evaluate instability, the threshold voltage (V TH) shift is monitored using positive and negative gate‐bias stress tests. MWA demonstrates better reliability than CTA. In conclusion, high‐performance solution‐based a‐IGZO TFTs can be implemented by lowering the charge traps in the a‐IGZO channel using MWA.

Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities

In this work a discussion on the estimated volume trap densities (NT) compared to surface traps densities (Neff) related to identified traps in the Si fin of Si/SiGe superlattice I/O n-channel FinFETs using low frequency noise spectroscopy is made. The investigated devices present a fin width of 10 nm, a fin height of 10 nm and four fins in parallel, leading to an equivalent channel width of 120 nm. The equivalent oxide thickness (EOT) is 5.6 nm. More details on the device fabrication and experimental setup may be found in [1,2]. The noise spectra and the estimated surface traps densities are provided in [3]. In this work, focus is only on the identified T4 trap, for which using the linear dependence that should exist between A0i and t0i related to the same trap, without any other assumption, a surface trap density of 2.8∙1012cm-2 is obtained [3]. It should be noted that from the 1/f flat-band noise level an interface trap density value of about 1.9∙1018 eV-1cm-3 is obtained at 300 K.However, as the traps in the Si film are related to a volume phenomenon, two methodologies to estimate the volume trap densities are employed: one using the relationship between the surface trap density and volume trap densitiy [4], where B is a coefficient estimated to be 1/3 [4,5]; and a second one from the temperature (T) evolution at fixed frequency of the Lorentzian plateau level associated to the same trap (from equation 34 in [4]). Using the first method leads to a volume trap density of T4 of about 1.7∙1019 cm-3.The second method consists to use the maximum of the measured Svg_Lor(f 0,T) dependence with temperature. Indeed, the Svg_Lor(f 0,T) of Lorentzians associated to the same trap are proportional with ti(T)/{1 + [2pf 0ti(T)]2}. For a given frequency f 0, if 2pf 0ti(T) ≫ 1, SVg_Lor(f 0,T) ∝ ti(T)]-1, and SVg_Lor(f 0,T) increases with increasing temperature because ti decreases. If 2pf 0ti(T) ≪ 1, then SVg_Lor(f 0,T) ∝ ti(T) and SVg_Lor(f 0,T) decreases with increasing temperature, as explained in detail in [4]. The evolution of the Svg_Lor(f 0,T)∙f 0 in a temperature range where T4 traps are active is illustrated in Figure 1 and presents a bell-shaped behavior, as expected. Using this method, volume trap densities of about 1.25∙1018 cm-3 for f 0 = 10 kHz and of about 1.1∙1018 cm-3 for f 0 = 14 kHz are obtained. It may be observed that the estimated volume trap densities of the T4 defect are about one decade lower than when using the first method. This overestimation by the first method is related to the fact that the theoretical B coefficient was determined for conventional planar devices with one gate [4,5]. Moreover, it may be noticed that the second method is dependent on the fixed f 0 selected.The paper will present a discussion with more details, considering all identified traps in [1] and considering additional new low frequency noise spectroscopy results.References :[1] Hellings, H. Mertens, A. Subirats, E. Simoen, T. Schram, L.-A. Ragnarsson et al., “Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology”, in Tech. Dig. Symp. on VLSI Technology, The IEEE New York, 2018, p.p. 85-86, DOI: 10.1109/VLSIT.2018.8510654.[2] Boudier, B. Cretu, E. Simoen, R. Carin, A. Veloso, N. Collaert, and A. Thean, “Low frequency noise assessment in n- and p-channel sub-10 nm triple-gate FinFETs: Part I: Theory and methodology,” Solid State Electron., vol. 128, pp. 102-108, 2017, DOI: 10.1016/j.sse.2016.10.012.[3] Boudier, B. Cretu, E. Simoen, G. Hellings, T. Schram, H. Mertens and D. Linten, “Low frequency noise analysis on Si/SiGe superlattice I/O n-channel FinFETs”, In Proceedings of EUROSOI-ULIS’2019.[4] Lukyanchikova, “Noise and Fluctuations Control in Electronic Device”, edited by A. Balandin, American Scientific, Riverside, CA, 2002, pp. 201-233.[5] Yau and C-T. Sah, “Theory and experiments of low-frequency generation-recombination noise in MOS transistors”, IEEE Trans. Electron Dev., 1969, vol.16, pp. 170-177.Figure 1 : SVg_Lor(f 0,T)·f 0 versus temperature for the T4 trap identified in [3]; on the secondary Oy axis the characteristic frequency f 0i of the Lorentzians is displayed in function of temperature. Figure 1

Discussion on the Figures of Merit of Identified Traps Located in the Si Film: Surface Versus Volume Trap Densities

The aim of this work is a discussion on the figures of merit of identified traps located in the depletion zone (Si film) of advanced MOSFET devices. Two methodologies to estimate the volume trap densities are investigated, one using the relationship between the surface trap density and volume trap density and a second one based on the temperature evolution at fixed frequency of the generation-recombination plateau level associated to the same trap. By comparing the volume trap densities estimated using these two methods, the results are not agreeing with each other, suggesting that these methods can no longer be used with accuracy in multi-gate devices. Moreover, they may lead in certain cases to results physically not correct. Even about of the volume defects, the linear evolution between the plateau and the characteristic frequency of the generation-recombination contributions associated to the same trap give us the surface trap density without any additional assumption.

Conduction mechanisms in hydrogenated amorphous silicon carbide

We report on the conduction mechanisms at room temperature of hydrogenated amorphous silicon carbide (a-Si1-xCx:H) films deposited by 13.56 MHz plasma-enhanced chemical vapor deposition (PECVD). By analysing the current-voltage (J-V) characteristic of films with different thicknesses, it was possible to prove that space charge limited current (SCLC) enhanced by the Poole-Frenkel effect is the dominant charge transport mechanism for high electric fields. In addition, films with a variation of the Si–C ratio x (between 0.5 and 0.8) showed that higher Si content decreases the volume trap density. This result was in accordance to an observed decrease of the Urbach energy, indicating less long-range disorder.

Reliability characterization of SiON and MGHK MOSFETs using flicker noise and its correlation with the bias temperature instability

Bias temperature instability (BTI) is one of the critical device degradation mechanisms in poly-Si/SiON and metal gate/high-k complementary metal-oxide-semiconductor (CMOS) technologies. Using the pre- and post-BTI flicker noise measurements, we investigated the bulk trap density, Nt, in both of these technologies. The low-frequency noise spectra were predominantly of 1/fγ type with γ<1 for NMOS and ∼1 for PMOS. For SiON based technologies, the lower VTH degradation due to PBTI was noticed while considerable VTH degradation was observed for NBTI in both SiON and MGHK technologies. Both MGHK and SiON pFETs show a clear increase in the effective volume trap density, Nt, after NBTI. The increase in Nt in MGHK n-MOSFETs during PBTI is markedly higher than that in MGHK p-MOSFETs during NBTI.

Space charge limited conduction in ultrathin PbS quantum dot solid diodes

As a simple and direct characterization of carrier transport in nanocrystal quantum dot (NQD) solids, current-voltage characterization of ultrathin diodes is proposed. We found the space charge limited conduction (SCLC) behavior in ultrathin PbS NQD diodes with active layer thickness half of the full depletion width; and extracted hole concentrations in the order of 1015 cm−3, hole mobilities from 10−4 to 10−5 cm2/Vs, trap energy depths varying from 140 meV to 200 meV, and volume trap density around 1017 cm−3 for thin films with NQDs of diameters 3.3 and 3.6 nm, respectively. We further discuss the validity of applying SCLC to the NQD solids based diodes and the implications of the extracted parameters extensively. Proposed characterization method here is a direct measure of carrier transport in solar cell structures which could provide exact directions in NQD solids based solar cell fabrication and modeling.

Modulation phenomena in Si nanowire field-effect transistors characterized using noise spectroscopy and gamma radiation technique

High-quality silicon nanowire (NW) field-effect transistors (FETs) were designed and fabricated. Features of transport and modulation phenomena of the structures were studied using a number of techniques, including noise spectroscopy. Using the 1/f noise component level, the values of the volume trap densities in gate dielectric are estimated to be around 1 × 1017 cm−3 eV−1. This result proves high quality of the investigated structures. Analysis of Lorentzian noise components of NW samples is used to characterize single trap and its parameters. A strong modulation of carrier concentration in the conducting channel under influence of even single carrier capture event has been revealed. Possibility of fine tuning of the transport properties of the sample with low-dose gamma irradiation has been shown. The gamma radiation treatment of the NW samples was applied as an effective technique to confirm the strong influence of trap charges on conductivity behavior in the channel of NW FETs. The results demonstrate that the modulation effects at the nanoscale enable effective changing of the channel conductivity by single capture events and thus are promising for future information technologies and ultra-sensitive single-molecular sensor applications.

An Electronic Model for Solar Cells Including Active Interfaces and Energy Resolved Defect Densities

We introduce an electronic model for solar cells taking into account heterostructures with active interfaces and energy resolved volume and interface trap densities. The model consists of continuity equations for electrons and holes with thermionic emission transfer conditions at the interface and of ODEs for the trap densities with energy level and spatial position as parameters, where the right-hand sides contain generation-recombination as well as ionization reactions. This system is coupled with a Poisson equation for the electrostatic potential. We show the thermodynamic correctness of the model and prove a priori estimates for the solutions to the evolution system. Moreover, existence and uniqueness of weak solutions of the problem are proven. For this purpose we solve a regularized problem and verify bounds of the corresponding solution not depending on the regularization level.

Characterization and Modeling of 1/$f$ Noise in Si-nanowire FETs: Effects of Cylindrical Geometry and Different Processing of Oxides

In this paper, the volume trap densities Nt are extracted from gate-all-around silicone-nanowire FETs with different gate oxides, using a cylindrical-coordinate-based flicker noise model developed. For extracting Nt, the drain-current power spectral densities were measured from a large number of identical devices and averaged over, thereby mimicking the spatial distribution of trap sites inducing 1/f curve. Also, effective mobility and threshold voltage were simultaneously extracted with the series resistance to characterize the 1/f noise in terms of intrinsic values of these two channel parameters. The volume trap densities thus extracted from different oxides (in situ steam-generated oxide/rapid thermal oxide/nitride-gated oxide) are compared and further examined using hot-carrier stress data. Finally, radius dependence of the cylindrical 1/f model developed is discussed.

Low-frequency noise in junctionless multigate transistors

Low-frequency noise in n-type junctionless multigate transistors was investigated. It can be well understood with the carrier number fluctuations whereas the conduction is mainly limited by the bulk expecting Hooge mobility fluctuations. The trapping/release of charge carriers is related not only to the oxide-semiconductor interface but also to the depleted channel. The volume trap density is in the range of 6–30×1016 cm−3 eV−1, which is similar to Si–SiO2 bulk transistors and remarkably lower than in high-k transistors. These results show that the noise in nanowire devices might be affected by additional trapping centers.

Effects influencing electron and hole retention times in Ge nanocrystal memory structures operating in the direct tunneling regime

We present an experimental study of the electron and hole charging and discharging processes in the direct tunneling regime of Ge nanocrystals (NCs) embedded in the SiO2 of metal/oxide/semiconductor transistors. A specific aim was to verify theoretical predictions of very long hole retention times for Ge NCs embedded in SiO2 with thin (direct) tunneling barriers which could be harnessed for fast nonvolatile memories. While we observed longer electron retention times than theoretically predicted, we did not find experimentally the expected long hole retention times. To explain the discrepancies between our results and the theoretical predictions, several nonideal properties of the real Ge–NC:SiO2/Si system were investigated. In particular, a Ge NC preparation-induced increase in the volume trap density in the tunnel oxide and an increase in the trap density at the interface between the tunnel oxide and the Si substrate were detected. However, this moderate increase in the trap densities by about one order of magnitude (as compared to reference samples without any Ge NCs) does not provide a plausible explanation for the short hole retention times observed. Rather, an electron current into the NCs during hole retention seems to limit the retention times. This effect should already occur in the ideal Ge–NC:SiO2/Si system, thus preventing the non-volatile memory applications of Ge NC based devices operating in the direct tunneling regime.

Low-frequency noise in strained SiGe core-shell nanowire p-channel field effect transistors

Low-frequency noise has been studied in compressively strained Si0.8Ge0.2 core-shell nanowire (NW) p-channel transistors compared with unstrained NWs. The noise has been well interpreted using the carrier number with correlated mobility fluctuation model. The volume trap density, Nt, lies in the range of 2.9×1018–4.3×1019 cm−3 eV−1, which is similar to standard high-k planar devices. The impact of Coulomb and surface roughness scatterings is more significant in unstrained SiGe NWs. This result can be explained by the better carrier confinement at the central region of SiGe NWs due to the additional band offset in the compressively strained NWs.

A quantum mechanical mobility model for scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

A quantum mechanical model of electron mobility for scaled NMOS transistors with ultra-thin SiO2/HfO2 dielectrics (effective oxide thickness is less than 1nm) and metal gate electrode is presented in this paper. The inversion layer carrier density is calculated quantum mechanically due to the consideration of high transverse electric field created in the transistor channel. The mobility model includes: (1) Coulomb scattering effect arising from the scattering centers at the semiconductor–dielectric interface, fixed charges in the high-K film and bulk impurities, and (2) surface roughness effect associated with the semiconductor–dielectric interface. The model predicts the electron mobility in MOS transistors will increase with continuous dielectric layer scaling and a fixed volume trap density assumption in high-K film. The Coulomb scattering mobility dependence on the interface trap density, fixed charges in the high-K film, interfacial oxide layer thickness and high-K film thickness is demonstrated in the paper.

1/ f noise performance of MOSFETs with HfO 2 and metal gate on Ge-on-insulator substrates

The low frequency (1/ f) noise performance of n- and p-MOSFETs with HfO 2 and TiN–TaN metal gate on GeOI substrates has been investigated. The LF noise spectra are of the 1/ f γ type, with γ>1. The current noise spectral density is typically one decade higher than for silicon counterparts. The behavior of the noise characteristics points to carrier trapping as the prevailing 1/ f noise mechanism. Using a tunneling coefficient α=6.5×10 7 cm −1 for the Ge/HfO 2 system, the extracted volume and surface trap densities are in the range of 1×10 20/cm 3 eV and a few 10 12/cm 2 , respectively. This is of the same order as the interface trap densities, obtained from charge pumping. It is believed that the Ge/interfacial layer (IL) quality could be responsible for the significantly higher trap densities and noise, compared with Si/HfO 2/ TiN–TaN MOSFETs.

Low-Frequency ( 1 ∕ f ) Noise Performance of n- and p-MOSFETs with Poly- Si ∕ Hf -Based Gate Dielectrics

The low-frequency (LF) noise performance of n- and p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with different Hf-based gate oxides, deposited by metallorganic chemical vapor deposition (MOCVD) on the same interfacial oxide layer and using polysilicon (poly-Si) as a gate material has been investigated. Independent of the gate oxide, the LF noise spectra of n- and p-MOSFETs are predominantly of the type, with the frequency exponent γ close to 1. For nMOSFETs, the noise spectral density of devices is two orders of magnitude higher than for or (silicates), where , most likely due to trapping by defects in the high- layer. For the silicates with different , no significant differences are noticed for n- and p-MOSFETs. It is shown that the noise characteristics behave as can be expected for a number fluctuations mechanism. The extracted volume and surface trap densities are significantly higher for pure than for the devices. In the latter case, trap densities comparable with the values for the reference transistors are obtained. Hooge’s parameter , as an alternative figure of merit, shows that the devices with MOCVD gate dielectric have the noisiest performance, while MOSFETs yield the lowest , even better than for .

Identification of TSC peaks and surface-voltage stability in Teflon FEP

In this paper we examine the stability of corona- and electron-beam-charged 25-μm FEP-A in open circuit by using thermally stimulated (TSC) measurements. We show that electrets charged with electron beams of 10 keV or higher are more stable than corona-charged foils. The inferior stability of corona-charged samples is due to the filling of surface traps as opposed to volume traps in electron-beam-charged samples. A peak at 155 °C was attributed to surface traps located at a depth of 0–0.5 μm, while a peak at 170 °C is due to charge stored 0.5–1.8 μm beneath the nonmetallized surface. The volume traps yield a peak at 200 °C. The total volume trap density was estimated to 1.4×1014 traps/cm3.