Voltage-frequency Islands Research Articles

Multi‐objective GA to schedule task graphs on heterogeneous voltage frequency islands

SummaryEnergy consumption of multiprocessor's system is increasing day by day. The capability of multiprocessor systems and high compute‐intensive tasks play a major role in increasing energy consumption. Voltage frequency island (VFI) architecture partitioned the cores into groups for which voltage/frequency can be controlled by a single switch. VFI plays a major role in optimizing the energy consumption. We have generated the initial population by using the slot technique to VFI architecture. The genetic algorithm studied by many researchers to solve scheduling problems. So we combined the genetic algorithm with the VFI‐enabled architecture and slot approach called VFIGen. Then apply the VFIGen algorithm to optimize the energy consumption. When comparing the results of the proposed one with the existing state‐of‐art we achieved the performance gain by to .

Energy Efficient Heuristics to Schedule Task Graphs on Heterogeneous Voltage-Frequency Islands

For energy and cost-efficient computing, many desktops and embedded computing devices these days use voltage frequency islands (VFIs) based processors. An island in VFIs consists of multiple homogeneous cores; however, multiple islands are generally heterogeneous in nature. In contrary to architectures (non-VFI) with per-core dynamic voltage frequency scaling (DVFS), in VFI, all the cores in an island run on the same voltage/frequency at the same time. The energy-aware scheduling of task graphs on VFI architectures is challenging and different from non-VFI architectures in which task-based DVFS is possible. However, in VFI scheduling, the time slot for which an island runs on a particular voltage will be decided. In this paper, we analyse 20 different scheduling heuristics for VFI architectures by varying the size of this time slot based on the workload properties and also by varying the voltage/frequency of the time slots. We also propose a heuristic OptSlotVFI to utilize all the slots optimally. The results show that the VFI scheduling heuristics are able to generate schedules which improve energy consumption up to 25% with an equivalent or shorter schedule length than the state-of-the-art approaches.

Design automation system synchronization for cyber physical system with dynamic voltage and frequency scaling in industry 5.0

Recent innovations in determining power—including the Internet of Things, M2M, online services, computational AI, and ARM-based big little multicores for encased applications—have aided in developing industrial process automation. Advanced IP-enabled, the fifth edition of Industry guidelines, are being implemented via actuators, sensing devices, and processors in machinery automation. This allows for increased degrees of competence with less human participation. Because of these novel innovations, the SCPS (Smart et al.) will be pivotal in the next industrialization phase. Multiple integrated systems with varying software are interconnected in an SCPS to perform tasks such as calculation, interaction, supervision, and action. Based on our findings, we propose an inconsistent structure for SCPS that facilitates the execution of composite workflow dynamics via electrical, pneumatic, and hydrodynamic operations. By modeling system problems, instrument postponement, operator interruption, and translation interruption, the proposed design allows for the separation of all components of an operational change, including calculation, oversight, interactions, and activation. This allows us to disentangle these many components. Voltage frequency islands (VFI) with an elevated level of flexibility are used to allocate intellectually integrated components to the many different physical operations, with the amount of flexibility varying from procedure to procedure. All modeled process parameters are fine-tuned using the Variable Volt and Fundamental Shifting methods. In the coming era of manufacturing 5.0, where human involvement is also a part of the procedure in different industries like fuel, compost, paper goods, concrete, space travel, and motor vehicle manufacturing, the suggested layout would be best suited for implementation.

Multiobjective Approach to Schedule DAG Tasks on Voltage Frequency Islands

Scheduling a Directed Acyclic Graph (DAG) on voltage frequency islands involves dividing the available processing units into multiple islands with varying voltage and frequency levels, and then mapping the tasks of the DAG to the islands while minimizing the makespan and overall energy consumption. In this research work, a novel DAG task scheduling model is introduced with the assistance acquired from the deep learning paradigm. The proposed model includes four major phases: (a) DAG modelling, (b) Voltage frequency island partitioning, (c) core temperature prediction and (d) scheduling optimization. Initially, the Directed Acyclic Graph (DAG) model is designed. The nodes of DAG represent tasks and the edges represent dependencies between tasks. Then, in the Voltage frequency island partitioning, the available processing units into multiple voltage frequency islands. This can be done based on the power consumption of each unit, and the task requirements. Subsequently, the Recurrent Neural Network (RERNN) is trained to predict the core temperature of each voltage frequency island based on the multi-objectives like execution time, makespan, overall energy consumption. Then, the scheduling of the DAG on the voltage frequency islands is optimized using the Self-Improved Pelican Optimization Algorithm (SI-POA). The proposed SI-POA model is an extended version of the standard POA model. The SI-POA model is inspired by the behavior by the natural behavior of pelicans during hunting. In the scheduling optimization phase, the SI-POA algorithm to optimize the scheduling of the DAG on the voltage frequency islands while taking into account the predicted core temperature of each island based on the Recalling-enhanced recurrent neural network (RERNN) model. The goal is to minimize the makespan and overall energy consumption of the DAG while keeping the core temperature of each island within safe limits.

A Fast Heuristic for Improving the Energy Efficiency of Asymmetric VFI-Based Manycore Systems

Voltage/Frequency Islands (VFIs) are practically used in multicore systems. VFIs cluster cores that share the same Voltage/Frequency (V/F) level for the entire application runtime. Using VFIs, switching V/F levels has less overhead per-core while saving more energy in exchange for tolerable execution delay. This paper targets the well-known K-means algorithm for clustering cores, where each cluster contains cores with similar computational workloads across applications phases. K-means produces sub-optimal clusters when cores workloads do not have the same variation across all phases. Furthermore, the workload variations require running a VFI with a different V/F level per-phase. This paper presents a fast heuristic that facilitates clustering by sorting computational workloads per-phase before applying K-means. The VFIs V/F levels are dynamically adjusted to meet energy budget constraints. This framework provides a guideline for users to choose a number of clusters that satisfies system configurations and energy efficiency preferences. Three parameters are evaluated to represent the computational workloads: utilization, Instruction-Per-Cycle (IPC), and execution time. For an application with highly varying workload, execution time achieves 52 and 65% more energy efficiency compared to utilization and IPC, respectively. Results show that the degree of workload variations for different applications impacts changing or fixing VFIs V/F levels.

Emerging architecture for heterogeneous smart cyber-physical systems for industry 5.0

Industrial process automation is becoming more advance due to the new technological revolutions like Industrial Internet of things (IIoT), Machine to Machine Communication (M2M), cloud computing, cognitive computing, artificial intelligence, and big little multicore-based ARM processors for embedded applications. Modern IP-enabled sensors, actuators, and controllers are transforming industrial automation into industry 5.0 compliances to attain full autonomy with minimal human intervention. With these emerging technologies, Smart Cyber-Physical System (SCPS) is the most important part of the fourth industrial revolution, where diffident programmed embedded systems are networked together to perform, computation, communication, control, and actuation. In this paper, we proposed a heterogeneous architecture for SCPS, where different electrical, pneumatic, and hydraulic processes can be integrated to execute hybrid process dynamics. The proposed architecture is enabled to separate all aspects like computation, control, communication, and actuation, of a process dynamic by estimating the process disturbances, sensor delay, actuator delay, and conversion delay. The allotment of computational embedded cores to different physical processes is done through voltage frequency islands (VFI) with high modularity which is different for different processes. All the mapped process dynamics are optimized through Dynamic Voltage and Frequency Scaling (DVFS). The best implementation of the proposed architecture is the upcoming era of industry 5.0 where human intervention is also in a fold in various industries like petroleum, fertilizer, paper, cement, space exploration, and automobile manufacturing.

Energy-Aware Scheduling of Streaming Applications on Edge-Devices in IoT-Based Healthcare

The reliance on Network-on-Chip (NoC)-based Multiprocessor Systems-on-Chips (MPSoCs) is proliferating in modern embedded systems to satisfy the higher performance requirement of multimedia streaming applications. Task level coarse grained software pipeling also called re-timing when combined with Dynamic Voltage and Frequency Scaling (DVFS) has shown to be an effective approach in significantly reducing energy consumption of the multiprocessor systems at the expense of additional delay. In this article we develop a novel energy-aware scheduler considering tasks with conditional constraints on Voltage Frequency Island (VFI)-based heterogeneous NoC-MPSoCs deploying re-timing integrated with DVFS for real-time streaming applications. We propose a novel task level re-timing approach called R-CTG and integrate it with non linear programming-based scheduling and voltage scaling approach referred to as ALI-EBAD. The R-CTG approach aims to minimize the latency caused by re-timing without compromising on energy-efficiency. Compared to R-DAG, the state-of-the-art approach designed for traditional Directed Acyclic Graph (DAG)-based task graphs, R-CTG significantly reduces the re-timing latency because it only re-times tasks that free up the wasted slack. To validate our claims we performed experiments on using 12 real benchmarks, the results demonstrate that ALI-EBAD out performs CA-TMES-Search and CA-TMES-Quick task schedulers in terms of energy-efficiency.

Power Management of Monolithic 3D Manycore Chips with Inter-tier Process Variations

Voltage/frequency island (VFI)-based power management is a popular methodology for designing energy-efficient manycore architectures without incurring significant performance overhead. However, monolithic 3D (M3D) integration has emerged as an enabling technology to design high-performance and energy-efficient circuits and systems. The smaller dimension of vertical monolithic inter-tier vias (MIVs) lowers effective wirelength and allows high integration density. However, sequential fabrication of M3D layers introduces inter-tier process variations that affect the performance of transistors and interconnects in different layers. Therefore, VFI-based power management in M3D manycore systems requires the consideration of inter-tier process variation effects. In this work, we present the design of an imitation learning (IL)-enabled VFI-based power-management strategy that considers the inter-tier process-variation effects in M3D manycore chips. We demonstrate that the IL-based power-management strategy can be fine-tuned based on the M3D characteristics. Our policy generates suitable V/F levels based on the computation and communication characteristics of the system for both process-oblivious and process-aware configurations. We show that the proposed process-variation-aware IL-based VFI implementation for M3D manycore chips lowers the overall energy-delay-product (EDP) by up to 16.2% on average compared to an ideal M3D system with no M3D process variations.

Energy-efficient scheduling of streaming applications in VFI-NoC-HMPSoC based edge devices

Energy-aware high-performance computing is becoming a challenging facet for streaming applications at edge devices in Internet-of-Things (IoT) due to the high computational complexity involved. Therefore, the number of processors has increased significantly on the multiprocessor system subsequently, Voltage Frequency Island (VFI) recently adopted for an effective energy management mechanism in the large scale multiprocessor chip designs. In this paper, energy-aware scheduling of real-time streaming applications on edge-devices is investigated. First, an innovative re-timing based technique is developed to transform the dependent workload into an independent task model to avail resources and the wasted slack in the processors with a possible minimal prologue. Moreover, unlike the existing population-based optimization algorithms, a novel population-based algorithm, ARSH-FATI is proposed that can dynamically switch between explorative and exploitative search modes at run-time for performance trade-off. Finally, a communication contention-aware Earliest Edge Consistent Deadline First (EECDF) scheduling algorithm is presented. Our static scheduler ARHS-FATI collectively performs task mapping and ordering. Consequently, its performance is superior to the existing state-of-the-art approach proposed for homogeneous VFI based MPSoCs.

Energy-efficient Static Task Scheduling on VFI-based NoC-HMPSoCs for Intelligent Edge Devices in Cyber-physical Systems

The interlinked processing units in modern Cyber-Physical Systems (CPS) creates a large network of connected computing embedded systems. Network-on-Chip (NoC)-based Multiprocessor System-on-Chip (MPSoC) architecture is becoming a de facto computing platform for real-time applications due to its higher performance and Quality-of-Service (QoS). The number of processors has increased significantly on the multiprocessor systems in CPS; therefore, Voltage Frequency Island (VFI) has been recently adopted for effective energy management mechanism in the large-scale multiprocessor chip designs. In this article, we investigated energy-efficient and contention-aware static scheduling for tasks with precedence and deadline constraints on intelligent edge devices deploying heterogeneous VFI-based NoC-MPSoCs (VFI-NoC-HMPSoC) with DVFS-enabled processors. Unlike the existing population-based optimization algorithms, we proposed a novel population-based algorithm called ARSH-FATI that can dynamically switch between explorative and exploitative search modes at run-time. Our static scheduler ARHS-FATI collectively performs task mapping, scheduling, and voltage scaling. Consequently, its performance is superior to the existing state-of-the-art approach proposed for homogeneous VFI-based NoC-MPSoCs. We also developed a communication contention-aware Earliest Edge Consistent Deadline First (EECDF) scheduling algorithm and gradient descent--inspired voltage scaling algorithm called Energy Gradient Decent (EGD). We introduced a notion of Energy Gradient (EG) that guides EGD in its search for island voltage settings and minimize the total energy consumption. We conducted the experiments on eight real benchmarks adopted from Embedded Systems Synthesis Benchmarks (E3S). Our static scheduling approach ARSH-FATI outperformed state-of-the-art technique and achieved an average energy-efficiency of ∼24% and ∼30% over CA-TMES-Search and CA-TMES-Quick, respectively.

Optimality of dynamic voltage/frequency scaling in many-core systems with voltage-frequency islands

In today’s multicore systems, depending on an application’s computational demand, cores are either operated individually at different Voltage/Frequency (V/F) levels or grouped into multiple Voltage-Frequency Islands (VFIs) to reduce system energy consumption. This paper formulates a task scheduling and VFI partitioning problem whose optimization goal is to minimize the task set (application) execution time (makespan) for a given energy budget. First, the constrained optimization problem is formulated with integer Linear Programming (ILP) to obtain per-core, per-task dynamic V/F levels in a fine-grain VFI-based system with single-core islands. Next, static task scheduling on coarse-grain VFI-based systems, where an island can contain several cores operated at the same V/F level, is formulated with Mixed integer Linear Programming (MILP), considering the energy budget and task set’s precedence constraints. As an extension of this work and to address varying computational workload of the applications at runtime, this paper proposes a DVFS-enabled VFI system, which forms the VFIs based on the cores’ workload similarities and dynamically adjusts the VFIs’ V/F levels over the applications’ execution phases. The experimental results show that under different energy budget constraints, fine-grain, dynamic task allocations provide on average 1.35x speedup over static coarse-grain scheduling and partitioning methods. Also, the results show that while our dynamically tuned VFI system’s performance is comparable to the fine-grain V/F assignment technique, compared to the static task scheduling/VFI partitioning method, it achieves on average 1.5x speedup across the applications considered in this study.

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture

The emergence of three-dimensional (3D) network-on-chip (NoC) has revolutionized the design of high-performance and energy efficient manycore chips. However, in general, 3D NoC architectures still suffer from high power density and the resultant thermal hotspots leading to functionality and reliability concerns over time. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage Frequency Island (VFI)-based power management strategy and Reciprocal Design Symmetry (RDS)-based floor planning. In this paper, we undertake a detailed design space exploration for 3D NoC by considering power-thermal-performance (PTP) trade-offs. We specifically consider a small-world network-enabled 3D NoC (3D SWNoC) in this performance evaluation due to its superior performance and energy-efficiency compared to any other existing 3D NoC architectures. We demonstrate that the VFI-enabled 3D SWNoC lowers the energy-delay-product (EDP) by 57.3% on an average compared to a 2D MESH without VFI. Moreover, by incorporating VFI, we reduce the maximum temperature of 3D SWNoC by 15.2% on an average compared to the non-VFI counterpart. By complementing the VFI-based power management with RDS-based floor planning, the 3D SWNoC reduces the maximum temperature by 25.1% on an average compared to the non-VFI counterpart.

Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems

Manycore chips are widely employed in high-performance computing and large-scale data analysis. However, the design of high-performance manycore chips is dominated by power and thermal constraints. In this respect, voltage–frequency island (VFI) is a promising design paradigm to create scalable energy-efficient platforms. By dynamically tailoring the voltage and frequency of each island, we can further improve the energy savings within given performance constraints. Inspired by the recent success of imitation learning (IL) in many application domains and its significant advantages over reinforcement learning (RL), we propose the first architecture-independent IL-based methodology for dynamic VFI (DVFI) control in manycore systems. Due to its popularity in the EDA community, we consider an RL-based DVFI control methodology as a strong baseline. Our experimental results demonstrate that IL is able to obtain higher quality policies than RL (on average, 5% less energy with the same level of performance) with significantly less computation time and hardware area overheads (3.1X and 8.8X, respectively).

VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs

The emergence of 3D network-on-chip (NoC) has revolutionized the design of high-performance and energy-efficient manycore chips. However, the anticipated performance gain can be compromised due to the degradation and failure of vertical links (VLs). The Through-Silicon-Via (TSV)-enabled VLs may fail due to workload-induced stress; the failure of a VL can affect the neighboring VLs, thereby causing a cascade of failures and reducing the lifetime of the chip. To enhance the reliability of 3D NoC-enabled manycore chips, we propose to incorporate a voltage-frequency island (VFI)-based power management strategy that helps to reduce the energy consumption and hence, the workload-induced stress of the highly utilized VLs. The adopted power-management strategy relies on control decisions about the voltage/frequency (V/F) levels on VLs. We demonstrate that compared to the well-known spare TSV allocation and adaptive routing strategies, power management is more effective in enhancing the reliability of a 3D NoC. VFI-based power management improves the reliability of the 3D NoC by one order of magnitude compared to both adaptive routing and spare allocation while running popular SPLASH-2 and PARSEC benchmarks. The principal benefit of power management is that it is capable of reducing the operating temperature of the system, which in turn enhances the Mean-Time-To-Failure (MTTF) of the VLs and reliability of the overall 3D NoC.

Energy Efficiency for Clustered Heterogeneous Multicores

Heterogeneous multicore systems clustered in multiple Voltage Frequency Islands (VFIs) are the next-generation solution for power and energy efficient computing systems. Due to the heterogeneity, the power consumption and execution time of a task changes not only with Dynamic Voltage and Frequency Scaling (DVFS), but also according to the task-to-island assignment, presenting major challenges for power management and energy minimization techniques. This paper focuses on energy minimization of periodic real-time tasks (or performance-constrained tasks) on such systems, in which the cores in an island are homogeneous and share the same voltage and frequency, but different islands have different types and numbers of cores and can be executed at other voltages and frequencies. We present an efficient algorithm to minimize the total energy consumption while satisfying the timing constraints of all tasks. Our technique consists of the coordinated selection of the voltage and frequency levels for each island, together with a task partitioning strategy that considers the energy consumption of the task executing on different islands and at different frequencies, as well as the impact of the frequency and the underlying core architecture to the resulting execution time. Every task is then mapped to the most energy efficient island for the selected voltage and frequency levels, and to a core inside the island such that the workloads of the cores in a VFI are balanced. We experimentally evaluate our technique and compare it to state-of-the-art solutions, resulting in average in 25 percent less energy consumption (and up to 87 percent for some cases), while guaranteeing that all tasks meet their deadlines.

A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications

An energy-harvesting wireless sensor node (WSN) integrates a 14-nm, 0.79-mm2, 32-b Intel Architecture core-based near-threshold voltage (NTV) microcontroller (MCU) that provides 17- $\mu \text{W}$ /MHz always-ON, always-sensing (AOAS) capability. The MCU implements four independent voltage-frequency islands, managed by an integrated power management unit and features a subthreshold voltage capable on-die oscillator and 42-nm fin-pitch, 8.3-pA leakage-per-bit SRAM. The MCU operates across a wide frequency (voltage) range from 297 MHz (1 V) to 0.5 MHz (308 mV), dissipating 23.5 mW to 21 $\mu \text{W}$ , and achieves $4.8\times $ better energy efficiency at an optimum supply voltage ( $V_{\text {OPT}}$ ) of 370 mV, 3.5 MHz, and 17 pJ/cycle. A functional AOAS WSN incorporating the NTV MCU shows promise for sustained $\mu \text{W}$ operation.

Energy-efficient Custom Topology Generation for Link-failure-aware Network-on-chip in Voltage-frequency Island Regime

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty

Multiple voltage frequency island (VFI)-based designs can reduce the energy dissipation in multicore platforms by taking advantage of the varying nature of the application workloads. Indeed, the voltage/frequency (V/F) levels of the VFIs can be dynamically tailored by considering the workload-driven variations in the application. Traditionally, mesh-based networks-on-chip (NoCs) have been used in VFI-based systems; however, they have large latency and energy overheads due to the inherently long multihop paths. Consequently, in this paper, we explore the emerging paradigm of wireless NoC (WiNoC) and demonstrate that by incorporating WiNoC, VFI, and dynamic V/F tuning in a synergistic manner, we can design energy-efficient multicore platforms without introducing noticeable performance penalty. Our experimental results show that for the benchmarks considered, the proposed approach can achieve between 5.7% and 46.6% energy-delay product (EDP) savings over the state-of-the-art system and 26.8% and 60.5% EDP savings over a standard baseline non-VFI mesh-based system. This opens up a new of class of codesign approaches that can make WiNoCs the communication technology of choice for future multicore platforms.

Statistical energy optimization on voltage–frequency island based MPSoCs in the presence of process variations

Energy efficiency has become a primary design concern for embedded multiprocessor system-on-chips (MPSoCs). Recently, voltage–frequency island (VFI)-based design paradigm was proposed to optimize system energy by combining with task scheduling. However, the ever-increasing variations cause large uncertainty for delay and power of the processors, resulting in performance parameters of the VFIs also manifesting as statistical distribution. As a result, it is more difficult for the deterministic energy optimization to achieve desirable performance yield, defined as the probability of the design meeting timing constraints of the system. In this paper, we propose a variation-aware statistical energy optimization framework which takes account of performance yield constraints in the overall optimization flow. We observed that statistical features of parameter distributions in homogeneous and heterogeneous platforms are different. We hence define two effective metrics, namely energy optimization sensitivity (EOS) and lowest operating voltage (LOV), to make our framework adapt to both of the platforms. Experimental results demonstrate that on average our framework achieves performance yield improvement of 45% than the deterministic scheme. In respect of energy optimization, on average our framework achieves energy reduction of 33% than the existing statistical task scheduling algorithm.