Scaling of supply voltage is one of the well-known methods for reducing leakage power. Data Retention Voltage (DRV) is the lower limit for the scaled voltage of SRAM. In this paper, we propose a modified analytical model for estimating the DRV of a 6T SRAM cell. The model is based on the sub-threshold current equations of the SRAM cell. The DRV of the 6T SRAM cell is computed using this model which is verified with the simulations carried out using the Cadence Virtuoso Tool. GPDK 45 nm, UMC 130 and 65 nm technology files are used for the validation of the model. The simulations are carried out for the 6T cell with different cell ratios and pull-up ratios. For each case, the DRV estimated from the model is nearly equal to the expected DRV calculated from simulations. The results matched well with the simulated results around 93%–79% whereas Qin’s model which matches only 75%–74%. This model shows better results than Qin’s model in terms of complexity and computation time. Furthermore, the proposed model is also validated for the calculation of DRV during process variation and shows better results.