Comparative study of decoupled read buffer SRAM memory cell for improve read noise margin

Abstract

The demand for portable devices is increasing day by day for which on-chip memory plays an important role to define the performance of the overall system. The various memory cell architectures are proposed by many researchers, but not a single memory cell architecture fulfills all design constraints. The various applications require optimized parameters of memory design such as low-power memory applications requiring low leakage power, high stable memory requiring higher noise margins, and high performance requiring high speed of operation. The conventional 6 T SRAM cell is most suitable for small size memory and high speed circuits. But it fails to achieve higher read stability at lower supply voltage, so various other memory cells are proposed to improve the read stability in memory cells such as 8T, SHO10TP1, WANG9T, KIM10T, and SUL10T. This work presents the comparative analysis of various available SRAM cell architectures under various design constraints. This work also shows the effect of supply voltage scaling over the various memory cells. The presented comparative work is useful for researchers to select the appropriate memory cell according to their requirements. The presented work is simulated using a 90 nm technology file and the simulated results shows that for low power application, 8T memory cell is the most prominent memory cell, for higher stability SHO 10TP1, WANG 9 T, KIM10T is found to be most suitable memory cells, and for high performance & smaller size system requirement, 6T memory cell is found most suitable.