Voltage Roll Off Research Articles

Optimizing dielectric constants for enhanced performance in nanoscale DG-FinFETs: A comprehensive study on short channel effects

This study explores how variations in fin and gate dielectric constants impact nanoscale, DG-FinFETs’ sensitivity to Short Channel Effects (SCEs). Various fin (channel) materials; Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si), are considered. PADRE simulation environment is used to investigate the threshold Voltage (Vth) Roll-off, a crucial performance parameter. GaAs-FinFET, with a gate dielectric and fin dielectric constant values of 15 and 45 shows the lowest threshold voltage of 0.412 V. The study concludes that FinFETs with a higher fin dielectric constant than gate dielectric constant exhibit reduced SCEs, leading to lower power consumption, faster switching, and improved efficiency. This underscores the importance of optimizing dielectric constants, especially the fin dielectric constant, for enhanced DG-FinFET performance.

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

An inversion charge-based threshold voltage model is proposed for 10 nm channel length Tri-gate (TG) FinFET. The variation threshold voltage has been studied with respect to fin width for different fin height and channel length The effect of width quantization has been explained with the help of the quantum mechanical effect (QME). A precise comparison of threshold voltage in terms of classical mechanics and quantum mechanics depicts the presence of width quantization in short channel device. The improvement of the short channel effects (SCEs), like subthreshold swing (SS), drain-induced barrier lowering (DIBL) and threshold voltage roll off have been studied. The impact of channel length to fin width ratio on DIBL and has been examined. The improvement of the SCEs at the same oxide thickness has been observed for high-k dielectric material. The potential and effect of hafnium oxide (HfO2) have been discussed and validated using technology computer-aided design (TCAD) simulation.

Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression

Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (VT), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µFE) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current–voltage (I–V), VT roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (VO) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as VT, SCE, SS, and µFE, of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of VO and O in two-step oxygen anneal process.

Highly Efficient White Organic Light-Emitting Diodes Based on Phosphorescent Iridium Complexes with Multi-Light-Emitting Layers

White organic light-emitting diodes (WOLEDs) incorporating a blend of blue, green and red phosphorescent small molecular materials are presented in this article. 4,4′,4″-Tris(carbazol-9-yl)triphenylamine (TcTa) and 9-(4-tert-Butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole (CzSi) with different transmission characteristics were selected as hosts for different emitting layers aim to promote holes transport, which will reinforce carriers’ balance and broaden carrier composite. On account of adaptive energy levels of the utilized dopants and hosts, secured phosphorescent WOLED displayed high efficiencies, low operating voltage and slow efficiency roll-off. In addition, distribution of carriers’ recombination zone and spectral of change were studied in detail to further understand the light-emitting mechanisms of obtained WOLEDs. Finally, by majorizing the dosage concentration of (fbi)2Ir(acac) (bis(2-(9,9-diethyl-9H-fluoren-2-yl)-1-phenyl-1H-benzoimidazol-N,C3)iridium(acetylacetonate)) and the architectures of WOLEDs, the optimal device exhibited the maximum efficiencies of 44.92 cd A−1, 42.85 lm W−1, 16.8%, respectively, turn on voltage of 2.6 V and Commission International de l’Eclairage coordinates of (0.337, 0.458) at the brightness level of 3000 cd m−2.

A Comprehensive Analysis of Short Channel Effects on Carbon Nano Tube Field Effect Transistors

As the direction of World health organization (WHO) report the diseases like male infertility, brain tumor, hearing impairment, fetus issues, effect on eyes and other various parts of the human body caused by harmful radiations released by portable electronic devices. To reduce radiation and size, a deep scaling has been applied on MOSFETs. Due to this aggressive scaling MOSFET devices are affected by Short Channel Effects (SCE) in Nanometer regime (<10 nm). The Short Channel Effects Such as Subthreshold Swing (SS), Drain Induced barrier Lowering (DIBL) and threshold voltage roll-off (VT), plays a key role in determining the performance of CMOS devices. At Nano-meter scale Carbon Nano Tube FETs (CNTFETs) devices might be furnished with good control on leakage current and power consumption. The comparative analysis of Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL) and Ion/Ioff ratio on Conventional Single Gate MOSFET (C-MOSFET), Double Gate MOSFET (DG-MOSFET) and CNTFET devices are presented in this paper. The results of comparative analysis show that CNTFET exhibits 133% times more Ion/Ioff ratio than MOSFET and very less change in Subthreshold swing and DIBL.

Bipolar host materials comprising carbazole, pyridine and triazole moieties for efficient and stable phosphorescent OLEDs

Achieving an excellent device performance with slow roll-off efficiency is still a crucial requirement for phosphorescent OLEDs in displays and white lighting applications. Three bipolar host materials comprised of carbazole, pyridine and triazole units, namely o-CzTPy, p-CzTPy, and 3-CzTPy were synthesized and developed. They are designed by selecting the pyridine and triazole groups together as an electron-transporting unit, and varying the different linking modes of the functional groups to optimize performance. These materials possessed high triplet energies (2.66 eV–2.69 eV), and good bipolar charge transporting abilities. FIrpic and Ir(ppy)3 based blue and green PhOLEDs incorporating these bipolar hosts show low turn-on voltage, high efficiencies and slow efficiency roll-off. Among them, a maximum efficiency of 22.25% (41.98 cd A−1) was achieved for o-CzTPy based blue device. More importantly, the o-CzTPy based green device achieved the desirable high efficiency of 29.08% (96.98 cd A−1), which is among the highest values for PhOLEDs with dopant Ir(ppy)3 ever reported in public scientific literatures. These excellent results demonstrated that these bipolar hosts possess high practical value for application in commercial PhOLEDs.

Efficient green electroluminescent devices with low operation voltage and slow efficiency roll-off by utilizing hole transport material as host

We reported efficient electroluminescent (EL) devices with low operation voltage and slow efficiency roll-off based on green emitter Ir1 by utilizing hole transport material TAPC as host. Experimental results revealed our designed single light-emitting layer (EML) devices exhibit even lower operation voltage and slower efficiency roll-off compared with double-EMLs devices attributed to the reduced carriers' injection barriers, balanced carriers' distribution and well confined recombination zone. Ultimately, efficient green EL device realized the highest current efficiency (CE), power efficiency (PE), external quantum efficiency (EQE) and brightness of 71.6 cd/A, 75.0 lm/W, 22.9% and 36600 cd/m2, respectively. Excitedly, turn-on voltage was only 2.5 V. Even at a given brightness of 1000 cd/m2 (3.4 V), CE of 67.2 cd/A (EQE = 21.5%) and PE of 65.8 lm/W can still be retained. Our work offers a method to prepare efficient devices with slow efficiency roll-off, low operation voltage and simultaneously simple device structure.

Physics based model for potential distribution and threshold voltage of gate-all-around tunnel field effect transistor (GAA-TFET)

In this paper, we propose physics based modeling for p-type surrounding gate TFET with single material gate. The surface potential is modeled from 2-D Poisson’s equation using Parabolic Approximation method. From the surface potential equation threshold voltage, threshold voltage roll off, drain current and Subthreshold Swing is modeled. The simulation of the model provides the threshold of 0.4 V, threshold voltage roll off less than 0.1 and Subthreshold Swing of 41 mV/dec. The model is validated using ATLAS TCAD Simulation Tool.

Explicit Threshold Voltage Modeling Insight for Short Channel Characterization of a WFE Elliptical GAA Strained-Si MOSFET

This paper presents explicit analytical modeling of a gate all around (GAA) strained silicon metal-oxide-semicondutor field-effect transistor (MOSFET) with elliptical cross section by incorporating the popular gate work function engineering (WFE) concept of lateral mole fraction variation from source to drain end. Surface potential and threshold voltage formulation of the proposed structure based on a quasi-three-dimensional scaling equation have been introduced. The derived model is further used to investigate the short channel characteristics of the device in terms of hot carrier effect (HCE), drain-induced barrier lowering (DIBL), threshold voltage roll off (TVRO), and subthreshold slope. The impact of device parameter variation including gate oxide thickness, effective radius, channel doping concentration, germanium (Ge) mole fraction variation in the strained silicon channel along with applied gate to source and drain biases are evaluated on device performance to justify its efficiency in comparison to its single gate material (SM) MOSFET equivalent. Our analytical analysis is further validated by ATLAS-3D device simulated data to verify the precision of the derived model.

A new analytical approach to threshold voltage modeling of triple material gate-all-around heterojunction tunnel field effect transistor

This paper presents a novel threshold voltage model for triple material gate-all-around TFET based on its surface potential that also includes the device depletion regimes. Analytical expressions for surface potential are derived using 2D Poison’s equation and parabolic approximation method. Electric Field and threshold voltage of the device are derived by considering the surface potential of source channel depletion regime. Threshold voltage roll off is then obtained by subtraction between short channel TFET and long channel TFET. Drain-induced barrier lowering of the proposed device is achieved using threshold voltage values for two different drains to source voltage values. Threshold voltage lies in a range between 0.6 and 0.8 V for different doping concentrations as obtained from simulation, which is less in comparison with other available TFET devices. The validity of the device model is tested using TCAD ATLAS Simulation tool.

Modeling source/drain lateral Gaussian doping profile of DG-MOSFET using Green’s function approach

Present work has used Green’s function approach to derive a two-dimensional analytical model of the double gate (DG) MOSFET at the subthreshold regime of operation that considers the effect of inevitable source/drain (S/D) lateral Gaussian doping profile. The non-integrable Gaussian term has been converted into an integrable function for accurate Fourier coefficient calculation which is then used to determine the potential equations of all three regions. These equations are then utilized to formulate channel current (Isub), the threshold voltage (Vt) roll off and subthreshold slope (SS) of the device. The effects of lateral Gaussian profile at different gate length (L), and for devices with different combinations of oxide thickness (tox) and channel thickness (tsi) have been investigated. The results show that the S/D Gaussian doping profile has severe effects at scaled gate lengths, where gate electrostatic control is of paramount importance.

Facile access to isocoumarin-based D-A-D triad: A thermally activated delayed-fluorescence host for efficient red phosphorescent OLEDs

Abstract Isocoumarin (ICO) is a natural occurring and well-documented π-conjugated structure due to its electron-withdrawing property and thermal stability. Herein, a novel donor-acceptor-donor (D-A-D) triad type of TADF host using ICO as the acceptor has been developed for the first time via a facile Ru(II) catalytic self-annulation of α-benzoyl sulfoxonium ylides. The high electron-deficiency and planar geometry of ICO structure may also be in favour of compact π-π stacking, thus providing fast transporting pathways for electrons, while the lone pair electrons of oxygen atom in ICO structure would offer a favourable condition to form intramolecular C–H⋯O hydrogen bonding, thus potentially reducing exciton quenching due to the inhibited structural relaxation. The resulting D-A-D triad (PXZ-ICO) exhibits significant thermally activated delayed fluorescence and well-balanced bipolar transporting property. The OLED devices utilizing this triad as a host exhibit outstanding electroluminescence with low driving voltage, high efficiency and small efficiency roll-off. This work would probably give us helpful inspiration for discovering organic functional materials using ICO derivatives.

Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

This article is discussing about threshold voltage roll off effect in Ultra Thin Fully Depleted Silicon on Insulator MOSFET. The device performance is improved due to the reduction in threshold voltage roll off. The thickness of oxide layer is optimized to 2nm which also have a vital role in improvement of device’s throughput. The effect of oxide thickness on parasitic parameter also discussed. Device conductance and transconductance also take in account on simulating the ultra thin fully depleted SOIMOSFET.

Efficient blue organic light-emitting diodes with low operation voltage by improving the injection and transport of holes

In this work, we reported the highly efficient organic electroluminescent (EL) devices based on blue phosphorescent material FIr6. By utilizing p-type dopant HAT-CN as hole injection layer material, the injection of holes from the anode was significantly improved. In addition, doping HAT-CN into hole transport layer (HTL) and inserting thin TcTa film between HTL and light-emitting layer (EML) improved the transport of holes. The stepwise energy levels between functional layers reduced the injection barriers of carriers, thus improving the balance of carriers within EML. Finally, highly efficient blue EL device realized the maximum current efficiency, power efficiency, external quantum efficiency (EQE) and brightness up to 39.14 cd/A, 38.68 lm/W, 24.6% and 17201 cd/m2, respectively. Even at the high brightness of 1000 cd/m2 (3.7 V), current efficiency and EQE as high as 36.73 cd/A and 23.1%, respectively, can still be retained by the same device. Our investigation provides an idea for the design of high-performance devices with low operation voltage and slow efficiency roll-off.

Sensitivity control of carbon nanotube-based piezoresistive sensors by drain-induced barrier thinning

The sensor characteristics of a membrane-based carbon nanotube (CNT) sensor showing maximum gauge factors of up to 810 is analyzed by a device study combining technological and theoretical approaches. Drain-induced barrier thinning (DIBT) is found to contribute significantly to this high sensitivity by a modification of the Schottky barrier width at the CNT-metal junctions. A high threshold voltage roll-off of (1370±130) mV⋅V-1 and degradation of subthreshold swing is observed even for channel length of 200 nm. The piezoresistive behavior of the CNT sensor running in the DIBT regime shows up as a complex and input-voltage dependent interplay of strain-dependent Fowler-Nordheim tunneling and the intrinsic thermionic resistance change. We demonstrate, that this interplay can be controlled by the applied bias voltages VGS and VDS in such a way, that the overall gauge factor is enhanced up to 150% with respect to the intrinsic effect. The control of the gauge factor via VDS is enabled by the DIBT effect, which appears for our CNT device at remarkably long CNT-channels.The experimental findings are retraced by a simplified transport model, which combines a numerical device solver with an electronic charge transport model for strained carbon nanotube based field-effect transistors (CNT-FETs) considering thermionic as well as tunneling contributions to the overall conductance. Strain dependent tunneling through the Schottky barriers appears to be the key contribution to the strain sensitivity in our model. Device characteristics have been derived from the model which reproduce the experimental findings emphasizing the significance of tunneling processes in combination with DIBT for the superior strain sensitivity of our device.

Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric Double Gate MOSFET

This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage

Threshold Voltage Modelling of Linearly Graded Binary Metal Alloy Gate Electrode with DP MOSFET

Two-dimensional (2D) analytical threshold voltage model for Linearly Graded Binary Metal Alloy (LGBMA) gate electrode with Dielectric Pocket (DP) Metal Oxide Semiconductor (MOSFET) has been developed by solving 2-D Poisson’s equation using evanescent mode analysis technique. In this proposed model, first time the idea of work function engineering is incorporated for DP MOSFET to bring an improvement over different short channel effects (SCEs). In present paper, the expressions for surface potential and threshold voltage are derived along with drain current, transconductance and drain conductance. Moreover, this model also predicts the variations of different SCEs like threshold voltage roll off, Drain-induced Barrier Lowering (DIBL) and sub-threshold swing along the channel length correctly. All analytical results are verified by ATLAS-2D simulator.

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

The Role of Charge Balance and Excited State Levels on Device Performance of Exciplex-based Phosphorescent Organic Light Emitting Diodes

The design of novel exciplex-forming co-host materials provides new opportunities to achieve high device performance of organic light emitting diodes (OLEDs), including high efficiency, low driving voltage and low efficiency roll-off. Here, we report a comprehensive study of exciplex-forming co-host system in OLEDs including the change of co-host materials, mixing composition of exciplex in the device to improve the performance. We investigate various exciplex systems using 5-(3–4,6-diphenyl-1,3,5-triazin-2-yl)phenyl-3,9-diphenyl-9H-carbazole, 5-(3–4,6-diphenyl-1,3,5-triazin-2-yl)phenyl)-9-phenyl-9H-3,9′-bicarbazole, and 2-(3-(6,9-diphenyl-9H-carbazol-4-yl)phenyl)-4-phenylbenzo[4,5]thieno[3,2-d]pyrimidine, as electron transporting (ET: electron acceptor) hosts and 9,9′-dipenyl-9H, 9′H-3,3′-bicarbazole and 9-([1,1′-biphenyl]-4-yl)-9′-phenyl-9H,9′H-3,3′-bicarbazole as hole transporting (HT: electron donor) hosts. As a result, a very high current efficiency of 105.1 cd/A at 103 cd/m2 and an extremely long device lifetime of 739 hrs (t95: time after 5% decrease of luminance) are achieved which is one of the best performance in OLEDs. Systematic approach, controlling mixing ratio of HT to ET host materials is suggested to select the component of two host system using energy band matching and charge balance optimization method. Furthermore, our analysis on exciton stability also reveal that lifetime of OLEDs have close relationship with two parameters; singlet energy level difference of HT and ET host and difference of singlet and triplet energy level in exciplex.

Analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET)

In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET with the conventional RingFET device architectures has been performed. Various important performance metrics such as surface potential, transfer characteristic (Ids-Vgs), ION/IOFF ratio, Threshold voltage roll off, Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Trans-conductance Generation Efficiency (gm/Ids), have been investigated.