Voltage Regulator Module Research Articles

A Dual Active Bridge Derived Hybrid Switched Capacitor Converter Based Two-Stage 48 V VRM

This article proposes a two-stage 48-V voltage regulator module using a hybrid switched-capacitor converter in the first stage. Apart from being compact in nature, this first-stage converter has several other advantages such as efficient regulation ability and hence scalability, inherent full/partial soft switching for most of the switches, reduced switch voltage and current stresses, and the possibility of wide range variable switching frequency operation. These combined features together help to obtain a flat high-efficiency curve for the first stage. The second-stage multiphase buck converter also exhibits flat high-efficiency characteristics through phase shedding. Steady-state circuit operation and analysis of the first-stage converter is presented in this article. An accurate discrete-time model of the first-stage converter is also developed. Thereafter, a design guideline for the two-stage converter is discussed. Finally, experimental results from an 80-W laboratory prototype show that the proposed converter possesses a relatively flat high-efficiency profile and exhibits a faster load transient response compared to that of the state-of-the-art solutions.

A New Single-Stage 48-V-Input VRM Topology Using an Isolated Stacked Half-Bridge Converter

A buck-derived transformer-isolated converter topology has been proposed in this article for the single-stage 48-V voltage regulator module (VRM) application. The proposed converter uses a switched-capacitor voltage divider derived stacked half-bridge circuit in the primary side of the transformer. This simplifies the transformer structure and reduces device voltage ratings compared to the conventional half-bridge or a full-bridge circuit. Detailed circuit operation, analysis, and design of the proposed converter are presented. Further circuit modification is proposed to avoid unequal average inductor current sharing due to unequal resistances of the inductors in the secondary-side current doubler rectifier and consequent load-dependent dc shift in the transformer magnetizing current. An averaged small-signal ac equivalent circuit model of the converter is derived and validated against SIMPLIS simulation results. Finally, experimental results from a GaN device-based 45-A laboratory prototype demonstrates a maximum efficiency of 92.7%, which is higher than that of the state-of-the-art solution for the selected specifications, and exhibits faster dynamic response against load step variations.

Design criterion and guidelines for three‐phase asymmetric coupled inductors in interleaving DC/DC converter for VRM in data centres and POL

Multiphase interleaving buck DC/DC converters (BCs) with magnetically coupled inductors (CIs) have been researched to improve the performance of voltage regulator module (VRM) and point-of-load (POL). Commercial three or more phase CIs are asymmetric CIs (ACIs) offering unequal phase self-inductance and unequal coupling between phases. By analysing the steady-state current ripple and transient current response speed of three-phase interleaving BCs with three-phase ACIs, the design criterion and design guidelines for three-phase ACIs are presented to simultaneously improve the steady-state performance and transient performance of three-phase interleaving BC with three-phase ACIs. A three-phase interleaving BC prototype with three-phase ACIs is constructed. The experimental results show that three-phase interleaving BC's steady-state phase current ripple can reduce 45%, and its transient output current response speed can increase 63.9% simultaneously by using three-phase ACIs instead of three-phase discrete inductors, and with a smaller total core volume and higher efficiency. The results of this study can be used to design VRM in data centres and POL with smaller steady-state phase current ripple, faster transient output current response speed, and higher efficiency.

Reliability Analysis of Capacitors in Voltage Regulator Modules With Consecutive Load Transients

Capacitors are critical in voltage regulator modules (VRMs), which contribute to store energy and stabilize the output voltage during load transients. Usually, VRMs work with consecutive load transients, which would bring more electrothermal stress to capacitors and affect the reliability of capacitors compared with the steady-state operation. Recently, some efforts have been made to investigate the reliability of capacitors in power electronic converters. Unfortunately, transient processes are commonly ignored, which can impair the accuracy of the lifetime estimation. Regarding this issue, this letter investigates the influence of transients on the damage of capacitors in VRMs. A 150-W VRM is introduced as a case study. First, the electrothermal stresses during steady state and transients are analyzed. Then, the lifetime calculation is considered from a single capacitor to hybrid capacitor banks. In addition, a suitable capacitor configuration of capacitor banks is also provided in order to maximize its lifetime.

Modeling and Control of Laptop Computer Voltage Regulator Module with Multiple Power Sources

Modeling and Control of Laptop Computer Voltage Regulator Module with Multiple Power Sources

Reducing Beat Frequency Oscillation in a Two-phase Sliding Mode-controlled Voltage Regulator Module

During static and dynamic loading conditions, voltage regulator modules (VRMs) are expected to provide regulated voltage with minimal ripple even at high current requirement. Compared to regular power supplies, VRMs repetitively experience high-frequency loading conditions that is greatly dependent on the software running in the processor utilizing them. In the scenario that when the transient load frequency is near the VRM’s switching frequency, high-magnitude and low-frequency oscillations are observed at the phase currents. This phenomenon is called the beat frequency oscillation. In this study, the sliding mode control principle is employed to both the voltage and current share loops of the VRM to reduce the phase currents’ beat frequency oscillations. A fixed frequency sliding mode controller is derived and extensively evaluated using the PSIM simulator. Our results show that while maintaining equal load sharing among VRMs at less than 5% sharing error and various types of loading conditions, the sliding mode controller can reduce the beat frequency oscillation phenomenon to 20 kHz at maximum with reduced peak current values. The output voltage is also regulated within the desired ± 1.65% band.

Reducing Beat Frequency Oscillation in a Two-phase Sliding Mode-controlled Voltage Regulator Module

During static and dynamic loading conditions, voltage regulator modules (VRMs) are expected to provide regulated voltage with minimal ripple even at high current requirement. Compared to regular power supplies, VRMs repetitively experience high-frequency loading conditions that is greatly dependent on the software running in the processor utilizing them. In the scenario that when the transient load frequency is near the VRM’s switching frequency, high-magnitude and low-frequency oscillations are observed at the phase currents. This phenomenon is called the beat frequency oscillation. In this study, the sliding mode control principle is employed to both the voltage and current share loops of the VRM to reduce the phase currents’ beat frequency oscillations. A fixed frequency sliding mode controller is derived and extensively evaluated using the PSIM simulator. Our results show that while maintaining equal load sharing among VRMs at less than 5% sharing error and various types of loading conditions, the sliding mode controller can reduce the beat frequency oscillation phenomenon to 20 kHz at maximum with reduced peak current values. The output voltage is also regulated within the desired ± 1.65% band.

Two-Stage 48-V VRM With Intermediate Bus Voltage Optimization for Data Centers

In this article, a high-efficiency and power-density unregulated inductor-inductor-capacitor (LLC) converter (DCX) is proposed for a first-stage converter in a two-stage 48-V voltage regulator module (VRM) for data center applications. The intermediate bus voltage in the two-stage architecture is evaluated by designing two LLC-DCX converters with fixed transformation ratios of (4:1) and (8:1). The overall efficiency of the two-stage architecture is evaluated, and the optimal bus voltage is selected. The LLC-DCX is designed using gallium nitride (GaN) devices and an optimized integrated magnetic structure. An enhanced primary and secondary termination method, as well as a printed circuit board (PCB) winding structure for equal current sharing among all transformer layers, is proposed, A significant reduction in the total conduction loss for the high-frequency transformer is achieved. The designed LLC-DCX can provide a continuous output power of 900 W with maximum efficiencies of 98.4% for the (4:1) conversion, and 98.0% for the (8:1) conversion, with high-power densities of 1600 and 1200 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , respectively. The overall efficiency of the two-stage VRM was evaluated, and the results show a superior performance when using a lower bus voltage of 6 V.

Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management

In today's manycore processors, the energy loss of more than 20% may result from inherent inefficiencies of conventional power delivery system (PDS) design. By stacking multiple voltage domains in series to lower the step-down conversion ratio of the off-chip voltage regulator module (VRM) and reduce the energy loss along the path of the power delivery network (PDN), voltage stacking (VS) offers a novel alternative power delivery technique to fundamentally improve power delivery efficiency (PDE). However, VS suffers from aggravated supply voltage noise from the current imbalance, which hinders its adoption. In this article, we investigate practical VS implementation in manycore processors to improve PDE and achieve reliable performance, while maintaining compatibility with advanced power management techniques. We first present the system configuration of a voltage-stacked manycore processor. We then systematically characterize supply voltage noise in VS, identify global, and residual differential currents as its dominant contributors, and calculate the possible worst supply voltage noise. We next propose a hybrid voltage regulation solution, based on a charge-recycling off-chip voltage regulator and distributed integrated voltage regulators, to mitigate supply voltage noise effectively. We also study the compatibility of VS with higher-level power management techniques. Finally, the performance of a voltage-stacked GPU system is comprehensively evaluated. The simulation results show that our approach can achieve 93.5% PDE, reducing the power loss by 13.6% compared to conventional single-layer PDS.

High-Step-Down DC–DC Converter With Continuous Output Current Using Coupled-Inductors

This paper proposes a high-step-down dc–dc converter with continuous output current which utilizes coupled-inductors. Another main feature of this converter is applying the same number of switches as the synchronous buck converter. The introduced converter is suitable for non-isolated low-voltage high-current applications, especially voltage regulator modules (VRMs) with 12-V-input. Owing to extension of the duty cycle, the main mosfet current stress and the synchronous rectifier switch voltage stress are significantly reduced. However, the discharge of the leakage inductance energy increases the main mosfet voltage stress. By employing a simple lossless clamp/snubber circuit the leakage inductance energy is recovered, the voltage spike across the main mosfet is clamped, and the turn- off switching losses are reduced. There is at least one inductor in all current paths which creates an intrinsic protection against current shoot-through and provides zero-current-switching (ZCS) turn- on for the main mosfet. High efficiency is attained by the proposed converter due to extended duty cycle, low number of switches, and soft switching operation while the converter driver is just like the conventional buck converter. Due to the single-phase structure of the proposed converter, this converter is a viable alternative to the buck VRM. Similar to the other converters using coupled-inductors, the complexity of coupled-inductors design and the space occupied by coupled-inductors can be considered as drawbacks. A prototype of the proposed converter is implemented to verify the converter operation and the theoretical analysis.

High-Current Switched Capacitor Converter for On-Package VR With PDN Impedance Modeling

Digital ASIC devices are widely used in networking and computing applications. This kind of devices is implemented with a short-channel technology requiring high peak currents for high complexity systems and a low supply voltage. Digital ASICs are powered by an external voltage regulator with specifications similar to modern microprocessors’ power supply [voltage regulation modules (VRMs)]. In order to reduce the number of power pins and to reduce the power distribution network (PDN) issue, Intel’s Fourth-Generation Core integrates the voltage regulators. Moreover, many on-package conversion systems are present in the literature. In this article, a conversion solution based on a switched resonant tank is presented, yielding currents up to 300 A at 0.8 V, in an area of 10 cm2, with a resonant-driving technique. The novel converter is used to validate a new linear time-periodic (LTP) system modeling approach that can be applied to generic switched topologies; this contribution yields a mathematical description of the conversion chain, in particular enabling the precise calculation of the output impedance when a switched topology is used as the last stage.

A Dual-Switch Discontinuous Current-Source Gate Driver Overcoming the Current Diversion Problem for a Buck VRM

In this article, a novel dual-switch discontinuous current-source gate driver (CSD) suitable for driving the high-side mosfet (HS mosfet ) of buck voltage regulator module (VRM) is presented. The proposed gate driver completely solves the gate current diversion problem, which most of the previous CSDs suffer from, during turn- off transition. Thus, in comparison to most of the previous CSDs, the proposed gate driver achieves to turn- off the power mosfet considerably faster and with much higher effective gate current, which leads to significant reduction of turn- off losses. Whereas, turn- on losses of buck VRM HS mosfet driven by the proposed CSD and the previous CSDs are equal. Furthermore, the introduced gate driver consists of the minimum number of control switches and circuit elements, compared to previous CSDs. The proposed gate driver is analyzed and a prototype of the driver operating at 1 MHz is implemented in order to validate the theoretical analysis.

Modeling and Analysis of On-Chip Power Noise Induced by an On-Chip Linear Voltage Regulator Module With a High-Speed Output Buffer

In this paper, analytical models of on-chip power noise induced by an on-chip linear voltage regulator module (VRM) circuit with a high-speed output buffer are proposed. Based on the piecewise linear approximated mosfet I – V curve model, closed-form equations for the on-chip power noise induced by an on-chip low-dropout regulator are derived. The accuracy of the proposed analytical model is validated by SPICE simulation with a 110-nm CMOS technology library. Based on the proposed analytical models, the impacts of VRM design parameters on VRM output noise induced by load current and external noises are analyzed. Because self-impedance at the VRM output and external noise transfer functions share a common resonant frequency, the on-chip power noise is minimized by avoiding the resonant frequency from peak frequencies of noise source spectrums. The larger on-chip decoupling capacitance at load reduces, the overall on-chip VRM output noise. While the larger pass transistor size reduces the on-chip VRM output noise induced by the reference voltage fluctuation, it increases the noise generated by off-chip power fluctuation. The reference voltage node needs to be carefully designed, as opposed to an off-chip power distribution network, due to its dominant impact on the on-chip VRM output noise. The analysis results based on the proposed model provide an in-depth understanding of and useful design guidance for on-chip power noise induced by the on-chip linear VRM with a high-speed output buffer.

Magnetic Core Solenoid Power Inductors on Organic Substrate for System-in-Package Integrated High-Frequency Voltage Regulators

In this paper, the design, modeling, fabrication, and characterization of System-in-Package (SiP) solenoid power inductor using a NiZn ferrite composite magnetic core material is demonstrated. A novel fabrication process has been developed for integrating the inductor into the buck-type integrated voltage regulator (IVR) module. The process uses stencil printing to deposit and pattern the magnetic core material. Photolithography and copper electroplating are used to form the windings. The electrical parameters of the fabricated inductors were extracted from measurements. The inductors had an average dc resistance of 19 $\text{m}\Omega $ , average inductance of 28.3 nH, and average ac resistance of $2.28~\Omega $ at 100 MHz, which is the operating frequency of the IVR. The organic substrate parasitic effect led to an average shunt capacitance of 2.31 pF and an average parasitic conductance of 0.12 mS at 100 MHz. The 10% saturation current was 11.53 A. The electrical parameters of the fabricated inductors were modeled and showed good accuracy with measured data. The inductors showed an inductance to dc resistance ratio of 1613 nH/ $\Omega $ . The area and volume energy densities were 158.4 nJ/mm2 and 283.0 nJ/mm3, respectively. These are the highest reported values for a solenoid magnetic core power inductor at 100 MHz.

An Isolated Multilevel Quasi-Resonant Multiphase Single-Stage Topology for 380-V VRM Applications

In order to increase the efficiency of modern microprocessor power supplies used in data centers, 380-V dc power distribution systems have been attracting attention due to their high efficiency and high reliability. This paper presents an innovative single-stage approach for 380-V voltage regulator modules (VRMs) based on a quasi-resonant multilevel topology constant on -time operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light-load conditions. This is a unique advantage, which is not possible to establish in the two-stage approach, which is very important in server architectures, and where high efficiency is required even at light-load conditions. This paper analyzes the circuit topology and proposes a control architecture for fast transient response, including current-sharing capabilities. The digital controller has been implemented in 0.16- $\mu$ m lithography together with a digital pulsewidth modulation with a 195-ps resolution and a 40-MS/s 7-bit analog-to-digital converter. Experimental results show an efficiency of 93% for a 120-A 380–1.8-V VRM power supply.

Modelling, simulation and control of a fuel cell-powered laptop computer voltage regulator module

An air-breathing fuel cell was investigated as an alternate power source for a laptop computer application. An empirical model was developed to include the phenomena of activation and ohmic polarisation as well as mass transport effects in order to simulate the behaviour of an air-breathing fuel cell. The model was used as the input source for a quadratic buck converter, which is used to power the central processing unit (CPU) core at 1 V. To achieve tight voltage regulation and good dynamic performance, the quadratic buck converter was implemented with average current mode control. The quadratic buck converter hardware setup has been developed with a fabricated fuel cell module in order to validate the model of the air-breathing fuel cell as well as the voltage regulator module.

DC-DC converter with GaN transistor and coupled with monolithic ICT sintered by PECS/SPS

ABSTRACTThis paper presents an implementation of the voltage regulator module (VRM) DC-DC converter operating at 2 MHz using three interleaved switching cells whose outputs are magnetically coupled by monolithic intercell transformers (ICT). The innovation comes from the manufacturing of the ICTs. Spinel ferrite is sintered around two copper windings by pulsed electric current sintering (PECS), also called spark plasma sintering (SPS). The manufacturing processes are detailed in this paper, and the ICTs magnetic properties are measured. The high-frequency operation of the converter has been possible thanks to the implementation of GaN components. The power density of the converter is 15 kW/dm3.

A Dual-Edge Pulsewidth Modulator for Fast Dynamic Response DC–DC Converters

Voltage regulator modules are dc–dc converters that power modern microprocessors. They must exhibit a fast dynamic response, in order to achieve satisfactory regulation performance in spite of the rapid load current variations. The pulsewidth modulator is one of the elements that determine the converter transient response. This letter introduces a dual-edge modulator that outperforms conventional modulation schemes in terms of both small- and large-signal dynamic performances: first, its small-signal transfer function exhibits a phase boost action in the high-frequency range, enabling the design of robust, wide-bandwidth control loops. Furthermore, it introduces a reduced expected delay in response to a large-signal perturbation. The modulator transfer function is derived in this letter using the describing function approach, and it is validated by comparing its predictions to SIMPLIS simulations and to the measured loop transfer function of a synchronous buck converter, designed in a 130 nm CMOS technology.

An Isolated Quasi-Resonant Multiphase Single-Stage Topology for 48-V VRM Applications

In order to increase the efficiency of modern microprocessors power supplies used in data centers, the 48-V dc distribution bus is gaining growing attention. For such applications, voltage regulation modules (VRMs) are currently obtained using two-stage conversion systems with an intermediate 12-V dc bus. This paper presents an innovative single-stage approach for the 48-V VRM based on a quasi-resonant constant on-time (COT) operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light load conditions. This is a unique advantage, usually not available in the two-stage approach, that is very important in server architectures, where high efficiency is required even at light load conditions. The paper analyses the circuit topology, and proposes a control architecture for fast transient response, including the current sharing capabilities, and a solution for implementing the integrated magnetics. The digital controller has been implemented in 0.16- $\mu$ m lithography together with a digital pulse-width-modulation with a 195 ps resolution, and a 40 MS/s, 7-bit ADC. Experimental results show an efficiency of 93.1% for a 250 A, 1.8 V VRM, and of 93.2% for a 102 A, 1.2-V double data rate (DDR) power supply.

Fully Integrated Digital Average Current-Mode Control Voltage Regulator Module IC

This paper introduces a fully integrated 12-to-1.xV voltage regulator module IC. A fully synthesizable digital two-loop controller has been realized through hardware description language tools. Several new IP blocks have been developed and described in detail: a window delay-line-based analog to digital converter (DL-ADC), two independent PI compensators with shared hardware for calculations, high-resolution digital pulsewidth modulation (PWM), and a programmable dead-time module. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, all units of the digital controller have been designed through asynchronous architecture, eliminating the need of high-speed clock. High-performance synchronized, fixed frequency, PWM operation is enabled by a digital programmable time-base generator and system governor, which has been developed as well. In addition, to extend the capabilities of the window DL-ADC to support the full range of the load with minimal hardware penalty, adaptive reference of the current compensation is introduced. The mixed-signal IC has been fabricated on a 0.18- $\mu \text{m}$ 5-V CMOS process. It incorporates the digital controller and periphery as well as a synchronous buck power stage, including a drive circuitry that enables operation up to several megahertz from a 12-V input. The digital core has been realized by an automated synthesis process and place-and-route tools, resulting in an effective silicon area of 0.16 mm2. Experimental results of the fabricated IC operating in closed loop are provided, demonstrating the performance and benefits of the new controller for meeting the requirements of tight output voltage regulation over wide load range.