Abstract

During static and dynamic loading conditions, voltage regulator modules (VRMs) are expected to provide regulated voltage with minimal ripple even at high current requirement. Compared to regular power supplies, VRMs repetitively experience high-frequency loading conditions that is greatly dependent on the software running in the processor utilizing them. In the scenario that when the transient load frequency is near the VRM’s switching frequency, high-magnitude and low-frequency oscillations are observed at the phase currents. This phenomenon is called the beat frequency oscillation. In this study, the sliding mode control principle is employed to both the voltage and current share loops of the VRM to reduce the phase currents’ beat frequency oscillations. A fixed frequency sliding mode controller is derived and extensively evaluated using the PSIM simulator. Our results show that while maintaining equal load sharing among VRMs at less than 5% sharing error and various types of loading conditions, the sliding mode controller can reduce the beat frequency oscillation phenomenon to 20 kHz at maximum with reduced peak current values. The output voltage is also regulated within the desired ± 1.65% band.

Highlights

  • The growing demands for high-speed and high-performance processors because of ubiquitous computing have dictated the digital market growth and provided various design challenges for the processors’ voltage regulator modules (VRMs)

  • Static Loading Condition Results To determine the design and control robustness, the two-phase VRM is subjected to static loading where the output voltage, steady state ripple and current sharing are the parameters to be observed

  • The sliding mode control (SMC)-based controller has been evaluated on various extensive simulations with different types of load conditions

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Summary

Introduction

The growing demands for high-speed and high-performance processors because of ubiquitous computing have dictated the digital market growth and provided various design challenges for the processors’ voltage regulator modules (VRMs). VRMs have lower voltage outputs (0.6V to 1.5V) while providing higher output currents (130A to 150A) to satisfy the processor’s speed and performance needs while operating at a switching frequency range of 0.2 – 1 MHz [2] Another issue influenced by the processor speed and the various running softwares is the dynamic loading of the VRMs ranging from several kHz to several MHz while the load transient duration can be randomly fixed at one value for a certain period. Another challenge is the high output current requirement of the VRM [3]. The ripple current is significantly smaller because the interleaved current phases cancel each other in magnitude

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