Voltage Overshoot Research Articles

Modular Design of Functional Glucose Monomer and Block Co-Polymer toward Stable Zn Anodes.

Aqueous Zn batteries employing mildly acidic electrolytes have emerged as promising contenders for safe and cost-effective energy storage solutions. Nevertheless, the intrinsic reversibility of the Zn anode becomes a focal concern due to the involvement of acidic electrolyte, which triggers Zn corrosion and facilitates the deposition of insulating byproducts. Moreover, the unregulated growth of Zn over cycling amplifies the risk of internal short-circuiting, primarily induced by the formation of Zn dendrites. In this study, a class of glucose-derived monomers and a block copolymer are synthesized through a building-block assembly strategy, ultimately leading to uncover the optimal polymer structure that suppresses the Zn corrosion while allowing efficient ion conduction with a substantial contribution from cation transport. Leveraging these advancements, remarkable enhancements are achieved in the realm of Zn reversibility, exemplified by a spectrum of performance metrics, including robust cycling stability without voltage overshoot and short-circuiting during 3000 h of cycling, stable operation at a high depth of charge/discharge of 75% and a high current density, >95% Coulombic efficiency over 2000 cycles, successful translation of the anode improvement to full cell performance. These polymer designs offer a transformative path based on the modular synthesis of polymeric coatings toward highly reversible Zn anode.

SiC MOSFET Active Gate Drive Circuit Based on Switching Transient Feedback

Due to the influence of parasitic internal parameters and junction capacitance, the silicon carbide (SiC) power devices are frequently marred by significant overshoots in current and voltage, as well as high-frequency oscillations during the switching process. These phenomena can severely compromise the reliability of SiC-based power electronic converters during operation. This study delves into the switching transient of the SiC MOSFET with the goal of establishing a quantitative correlation between the gate driving current and the overshoot in both the drain-source voltage and the drain current. In light of these findings, the innovative active gate drive (AGD) circuit, which features an adjustable gate current, is introduced. Throughout the switching process, the AGD circuit employs a dynamic monitoring and feedback mechanism that is responsive to the gate voltage and rate of change in the drain-source voltage and drain current of the SiC MOSFET. This adjustment enables gate driving current to be actively modified, thereby effectively mitigating the occurrence of overshoots and oscillations. To empirically validate the efficacy of the proposed AGD circuit in curbing voltage and current overshoots and oscillations, a double-pulse experimental setup was meticulously constructed and tested.

Mitigating reverse recovery power losses in MOSFET switching cell using extra Schottky diodes—Application to voltage source inverter

This article introduces a comparative study of the losses in Voltage Source Inverter (VSI) based on Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) depending on whether or not the latter are associated with antiparallel diodes. These diodes are optional because MOSFETs have an intrinsic diode capable of conducting reverse currents when their channel is in OFF state. However, it induces additional reverse recovery losses and damaging voltage overshoots. This undesired circumstance occurs during the mandatory switching cell dead-time and is accurately modelled and assessed in this study. Conversely, Schottky diodes feature almost zero reverse recovery losses. Hence, combining each MOSFET with an antiparallel Schottky diode may reduce the converter overall losses. To assess this strategy, an analytical model of the charge stored within the body diode is developed and then compared to experiments using the Double Pulse Test (DPT). It reveals accurate and well suited because it requires only two constant macro parameters which permits to forecast the reverse recovery losses over a wide range of operating conditions, namely switched current, current slope and dead time duration. The selected model is applied in the case where a Schottky diode is placed antiparallel to the MOSFET. It then appears clearly that the interest of such a combination depends on the static characteristics of both the MOSFET and the Schottky diode. This output is a noteworthy point for power electronics designers. Finally, the developed model is applied in the standard use case of the Voltage Source Inverter (VSI). The results reveal the advantage of the suggested model in this use case because the current evolves significantly over time. The outcome of this VSI analysis shows that a significant recovery losses decrease is achieved with good sizing fit between the MOSFET transistor and the additional Schottky diode.

Design of 3-level LLC converter voltage controller for wide input voltage fluctuations

The auxiliary power supply unit for railway vehicles delivers various power to the passenger car. Maintaining isolation between the catenary power line and the auxiliary power in the compartment is typically essential. To ensure electrical isolation, an efficient LLC resonant converter is utilized among isolated DC-DC converters. Generally, LLC resonant converter primarily employ PFM control method. However, there is a limitation in increasing the switching frequency at high input voltages, making it difficult to handle wide input voltage fluctuations from the overhead catenary power line. To overcome this limitation, the PFM control method is introduced alongside the existing PFM control method, resulting in the presence of two controllers. However, since these two controllers regulate the output voltage differently, there is a potential for output voltage overshoot due to significant input voltage fluctuations. This paper proposes a method that combines PFM and PWM controllers, along with feed-forward compensation, to address these issues. The effectiveness of this proposed method is validated through PSIM simulation and experimentation.

Digital Close-Loop Active Gate Driver for Static and Dynamic Current Sharing of Paralleled SiC MOSFETs

SiC power devices have been extensively for the high-power density application scenarios. To increase the current rating, SiC devices are usually connected in parallel. However, the mismatching current brought by unbalanced electrical parameters can increase the current stress of a device and pose reliability concern of the converter system. Aiming at addressing the current imbalance for paralleled SiC devices, this paper reports the application of an improved active gate driver (AGD) on the paralleled SiC MOSFETs to address the current imbalance problems. The three-level driver voltage can minimize the overshoot voltage and current. The adjustable turn-on voltage and gate signal delay time can realize the current sharing of both static and dynamic process. Current sensors and a digital controller are utilized for close-loop control. The functionality of the proposed AGD is validated in continuous operating experiment.

Three novel machine learning-based adaptive controllers for a photovoltaic shunt active power filter performance enhancement

This study develops three new machine learning-based algorithms using the SVR prediction approach. The overall objective is to enhance the performance of the PV shunt active power filter (PV-SAPF) in order to successfully fulfil its multi-functionality in terms of PV power generation along with power quality upgrades. The first technique, named "SVR-INC MPPT", incorporates an ML-based duty cycle prediction function, which is intended to speed up the MPP finding process. The algorithm then switches to the INC approach, guaranteeing an accurate steady-state response. The second and third techniques are the ML-based Adaline for DC voltage regulation, and the ML-based Adaline SRF strategy for reference currents generation. The adopted approaches are based on the prediction of two weights performing the actions of the proportional and integral of DC voltage controller, and nine weights for the fundamental currant extraction. The advantage lies in overcoming the Adaline-based algorithm's limitations, requiring an on-line large number of iterations. Three simulation scenarios along with six controllers based on classical and intelligent techniques, are adopted to prove the effectiveness of the proposed ML-controllers. The results display (i) an accurate and immediate ML-based harmonics identification (minimizing the extraction error by up to 99% compared to the Adaline approach). (ii) a response time reduction range from 65% to 100%, of the ML-based DC voltage output controller compared to the PI-based one. (iii) a THD range from 2.41% to 4.45%. (iv) 20 ms and 0% of PV power response time and overshoot, respectively (v) DC voltage overshoot range from 0.04% to 1.1%. Consequently, these three ML-based controllers offer the best options for a powerful PV-SAPF system in terms of performance tracking and harmonic attenuation. Moreover, the obtained metrics comply with IEEE-519 standard.

Thickness Effect of Copper Clips on Power Module Packaging Design

The superior switching performance of SiC MOSFETs compared to Si devices is limited by packaging-related issues. High electromagnetic parasitics which lead to high voltage overshoots, and higher power losses are the main challenges of high frequency operation. Hence, packaging design modification and optimisation are necessary to accommodate faster switching. Copper clips replacing the bonding wires show promising results in reducing stray inductances, while enhancing the current conduction and heat dissipation since the clip are in contact with a larger area of the semiconductor chip. Silver sintering instead of soldering further improves the electrothermal behaviour. This paper investigates numerically various thicknesses of the copper clips and their effect on double-sided silver sintering, half-bridge 1200V/400A SiC MOSFET power module. Moreover, the silver layer thickness is varied to reduce th maximum stresses on the chip - silver interface.

Optimal Adaptive Fractional Order Integral Sliding Mode Controller-Energy Management Strategy for Electric Vehicles Based on Bald Eagle Search Algorithm

This research presents an optimal energy management system (EMS) for a lithium-ion battery-supercapacitor hybrid storage system used to power an electric vehicle. The storage systems are connected in parallel to the DC bus by bidirectional DC-DC converters and feed a synchronous reluctance motor through an inverter. The proposed energy management strategy is built on the idea to take full benefits of two combined methods: the bald eagle search algorithm and fractional order integral sliding mode control. To evaluate the effectiveness of the suggested optimal energy management strategy, an urban dynamometer driving schedule (UDDS) driving cycle is considered. The obtained results are compared to a classical fractional order integral sliding mode control-based energy management strategy in terms of voltage ripples, overshoots, and battery final state of charge. The ultimate results approve the ability of the proposed energy management system to enhance the power quality and enhance battery power consumption at the same time. Comprehensive processor-in-the-loop (PIL) cosimulations were conducted on the electric vehicle using the C2000 launchxl-f28379d digital signal processing (DSP) board to assess the practicability and effectiveness of the proposed EMS.

Resonant Gate Drive Circuit with Active Clamping to Increase Efficiency and Reliability

In power converters with high switching frequency, drive losses constitute a significant portion of the overall power losses. Resonant gate drivers can reduce drive losses, thereby enhancing the efficiency. However, resonant drivers suffer certain challenges: parameter drifts lead to the mismatch between the resonant frequency and the control frequency, and this mismatch can cause gate-to-source voltage overshoot. Moreover, the resonant driver is susceptible to external interference. This paper proposes a resonant circuit structure and control timing scheme aimed at overcoming these limitations. By incorporating a half-bridge clamp circuit, the proposed design achieves voltage clamping, thereby insulating the system from disturbances caused by mains power fluctuations. When there is a mismatch in resonant frequencies, the strategy employs a combination of hardware circuit diodes and control system timing to prevent overvoltage issues. Additionally, the utilization of MOSFETs minimizes the loss caused by prolonged current flow through body diodes, further reducing the resonant driving losses. Simulations have demonstrated the system’s stability under varying resonant parameters and its effective anti-interference capabilities in voltage clamping. Experiments achieved a power saving of 83.3% at a 1 MHz operating frequency. Both simulations and experimental validations confirm the feasibility of the proposed solution, its effectiveness in interference suppression, handling of resonant mismatches, and its role in further augmenting power conservation.

Innovative Test Bench for RF and High-Voltage Component Characterization for MRI Applications: A Comprehensive Review

This scientific paper presents a detailed exploration of the electrical characterization of commercially available trimmers, conducted in collaboration with Siemens Medical. The study encompasses the establishment of a specialized measurement bench for impulse mode electrical tests, involving the adaptation of the signal generator with an adjustable supercapacitor and variable inductance. For precise measurements, a carefully designed filtering system prevents voltage overshoots. Given the critical sensitivity of voltage and frequency measurements for passive components in RF and high-voltage applications, the methodology is further refined to achieve optimal compromises across various parameters. The primary objective remains the determination of the voltage across the evaluated capacitor using the proportionality coefficient 𝛼, essential for accurate trimmer characterizations. In this paper, useful insights are provided into the electrical characterization of trimmers, as well as a refined methodology designed for RF and high-voltage applications. The findings presented herein enhance our understanding of trimmer behavior, offering potential implications for improved component selection and performance in a range of electrical systems.

An improved state‐space average model of the ultra‐high voltage inverter based on wavelet decomposition and reconstruction

SummaryUltra‐high voltage inverters are widely used as grid‐connected devices in new energy grids, and the state‐space average model is the most practical modeling method for the inverter. However, the accuracy of this modeling method is significantly reduced because it ignores the high‐frequency switching process, which contains overshoot voltage and other factors that affect system stability. Moreover, the amplitude of the overshoot voltage in the ultra‐high voltage inverter will be huge, which may lead to the damage to switching devices, circuit overheating, and even the collapse of the system. Therefore, the wavelet decomposition and reconstruction methods are used in this paper to extract the transient characteristics of the inverter and integrate them into the state‐space average model. Compared with the traditional state‐space average model, the improved model method can obtain a more accurate overshoot voltage peak value with the same simulation step size. Then, it can provide a more precise reference for the withstand voltage in the device selection of a high voltage level system. The single‐phase full‐bridge inverter is taken as an example to illustrate the construction process based on the wavelet decomposition and reconstruction method. Finally, the simulation waveform is verified to be in good agreement with the experiment.

Optimization of DE-QG TFET using novel CIP and DCT techniques

In this paper, two novel techniques Channel-Intermediate-Pocket (CIP) and Dual-Channel-Type (DCT) are proposed to optimize the Drain Engineered-Quadruple Gate TFET (DE-QG TFET). The proposed DCT technique is realized by making half of the channel area with lightly doped n- and the other half with the lightly doped p- channel. The CIP technique is implemented by inserting a pocket exactly at the junction of lightly doped n- &p- channel regions. Using the proposed techniques, the Ioff is reduced by ∼3.3 times (2 × 10-17 A/μm), the Iamb is reduced by a magnitude of two orders (2.39 × 10-17 A/μm) and by using the Dual-Oxide technique, the Ion is increased by 5 times (0.641 mA/μm) that of the conventional DE-QG TFET. Also, a steeper subthreshold swing (SS) of ∼57 mV/dec and one order of magnitude increase in the Ion/Ioff ratio of 3.19 × 1013 is achieved. Further, the peak overshoot voltage is suppressed by 86%, the transconductance (gm) is increased by ∼3 times (757 μA/V), and both the cut-off frequency (fT) and the Gain Bandwidth Product (GBW) are increased by ∼2.3 times (49 GHz & 5.2 GHz) respectively. The proposed device is mainly targeted towards Analog/RF applications.

Universally Applicable DC-Link RC Snubber Design Method for Switching Voltage Overshoot Reduction

Universally Applicable DC-Link RC Snubber Design Method for Switching Voltage Overshoot Reduction

Mechanism of gate voltage spike under digital gate control at IGBT switching operations

This paper reports the mechanism of gate voltage spike in the turn-off operation by a digital gate control. In the previous work, it was clarified that the gate voltage spike Vg_spike was generated by parasitic inductance and a large gate current change due to the digital gate control. However, the main cause of resonance leading to Vg_spike generation has never been clear. Three types of IGBT modules, which have the same gate inductance and different input capacitance, were tested under three-step digital gate control. It was found that the Vg_spike was independent of input capacitance in IGBT. As for the stray capacitance in the digital gate driver, external capacitors Cex were connected in parallel with the gate driver, and the Vg_spike decreased with increasing Cex. Furthermore, the second vector of the digital control, which was applied for suppressing the overshoot in collector-emitter voltage by a small value, needed to be set as a large value to suppress the Vg_spike. From these results, output impedance of gate driver is a key factor for the Vg_spike, and the second vector must be optimized for not only the collector voltage overshoot but also Vg_spike suppression for safety operation.

Characterizing the Dynamic Response and Start-up Process of the Electrolyzer for Operation Optimization in Renewable Energy Applications

The current water electrolyzer industry is experiencing rapid growth due to the increasing demand for renewable hydrogen as a clean energy. The application in renewable energy demands the dynamic operation of the electrolyzer, while the dynamic and start-up response of the electrolyzer is not comprehensively studied. This study focuses on characterizing the dynamic response, as well as the start-up process of electrolyzers. The dynamic response of the electrolyzer is analyzed using an alternating input current step, and the electrochemical response is correlated with the dynamic control of the electrolyzer. The overshoot voltage during the alternation process is taken as the indicative response under different baseline current, current change amplitude and frequency. The start-up process of the electrolyzer is also explored and analyzed with respect to the start-up time, energy cost, and the initial status of the electrolyzer as well as the liquid circulation rate. The overall energy cost, as well as the start-up time, across the start-up process possesses a strong linear relationship towards the initial temperature of the start-up. Besides, the liquid circulation rate has an impact on start-up power, because higher circulation rate brings more uniform temperature distribution of the electrolyzer. Tuning the liquid circulation rate can help to reduce the elapsed time, and hence accelerate the response speed. The findings provide a framework for testing the electrolyzer and optimizing the start-up process. This paper offers valuable insights that can be applied in the development and design of large-scale electrolyzers, thereby ensuring more efficient and sustainable production of hydrogen. Overall, this paper constitutes an important contribution to the study of electrolyzer and has the potential to shape future research in the area of electrolyzer development and operation optimization. Figure 1

Detailed Controller Synthesis and Laboratory Verification of a Matching-Controlled Grid-Forming Inverter for Microgrid Applications

Grid-forming inverters are the essential components in the effort to integrate renewable energy resources into stand-alone power systems and microgrids. Performance of these inverters directly depends on their control parameters embodied in the controller. Even the most conscientiously designed controller will exhibit suboptimal performance upon implementation due to the presence of parasitic elements in the existing hardware. Hence, the controller has to be tuned and optimized. In the present article, the process of implementation, laboratory verification, and tuning of a matching-controlled grid-forming inverter is presented. In order to assess the efficiency of the grid-forming controller, its operation has been tested and analyzed in blackstart, steady state, and transient operation. For this purpose, a systematic sensitivity analysis has been conducted and the control parameters have been tuned in laboratory tests. The laboratory results verify proper operation of a 7 kW grid-forming inverter in all three test scenarios. After applying the proposed method on the tested grid-forming inverter in steady state operation, total harmonic distortion (THD) of the output voltage is less than 0.5% for its practical loading range (maximum THD is less than 1% in no-load condition). The system is able to blackstart and supply the loads. Finally, the studied grid-forming inverter is stable in the presence of severe step load changes and disturbances, i.e., voltage overshoot is managed well and compensated for with a low settling time using this approach.

Resistor-less power-rail ESD clamp circuit design with adjustable NMOS gate biased voltage

Based on the 0.18 μm CMOS process, proposed a new power-rail electrostatic discharge clamp circuit. The proposed circuit can adjust the voltage biased to the big clamp NMOS (Mbig) gate by adjusting the width of one MOS transistor, and the feedback path is designed to prolong the response time of Mbig. The simulation results demonstrated that the voltage biased to the Mbig of the proposed circuit has a relatively steady state and the Mbig has a longer response time, which can effectively reduce the damage to the gate oxide layer of the Mbig with large voltage overshoot. The transmission line pulse test results show that compared to the Mbig of the conventional circuit, the Mbig of the proposed circuit has higher trigger voltage, lower on-resistance, and better robustness.

Design and analysis of multiple input single output converter for hybrid renewable energy system with energy storage capability

This paper proposes the design and analysis of a multiple-input-single-output (MISO) DC-DC converter suitable for a hybrid renewable energy system with energy storage capability. The converter design and control strategy validated in this research can be used to regulate the output dc voltage obtained from multiple-source renewable energy systems. The design is realized using a non-isolated double boost converter as it can handle bidirectional power flow at the storage port and has other advantages like compact structure, reduced number of components, and double boosting capability. The converter can also work without transformers, enabling the input renewable energy sources to operate individually. An inverted decoupler control strategy is adopted in the design of this novel converter. Mathematical models were developed to obtain the decoupler matrix, and the proposed control strategy is utilized to analyze the output. Simulations were performed on MISO converters with load and reference variations and is validated with the prototype. The current ripple percentage at the dual source side is found to be reduced by 2.6%. Also, the rise time, settling time, and percent overshoot of the output voltage were reduced by 0.03 s, 45 ms, and 3.6%, respectively. The performance of the proposed MISO converter is validated on a 50 W hardware prototype. The results validate the MISO converter's superior dynamic performance, output voltage regulation and reduced dual source ripple current, all of which are in agreement to the results of the simulation. A comprehensive comparison with the traditional controller is also conducted to further illustrate the advantages of the proposed inverted decoupler. The inverted decoupler validated in this work can be effectively used in hybrid renewable energy systems with energy storage capability, as it is found to be immune to the disturbances from the source end.

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

An improved coupled inductor‐based quadratic step‐up DC–DC converter with a high step‐up factor and reduced voltage overshoot on the power switch

AbstractMost coupled inductor‐based step‐up DC–DC converters encounter a significant voltage overshoot on their power switch due to the leakage inductance of the coupled inductor. So, they need additional bulky snubber circuits or a sophisticated procedure for coupled inductor design to reduce that effect. This paper proposes an improved coupled inductor‐based DC–DC converter, which provides a high quadratic voltage conversion ratio without excessive voltage stresses on the power switch. An active clamp circuit that operates with the zero‐voltage switching (ZVS) feature has been utilized for this aim. This feature allows the main power switch to be selected from low voltage ratings and low on‐resistance MOSFETs, which reduces conduction loss. The topology also benefits from continuous input current, high gain, high efficiency, and an appropriate number of components compared with the produced gain. In this article, the theory and operation of this converter are described by proposing the dc and small‐signal models, loss model, and continuous and discontinuous current modes (CCM and DCM) relations. Experimental results are represented to evaluate the performance of the proposed topology. For this purpose, a 240 V/240 W prototype has been designed and fabricated. Results confirm the above claims.