Optimization of DE-QG TFET using novel CIP and DCT techniques

Abstract

In this paper, two novel techniques Channel-Intermediate-Pocket (CIP) and Dual-Channel-Type (DCT) are proposed to optimize the Drain Engineered-Quadruple Gate TFET (DE-QG TFET). The proposed DCT technique is realized by making half of the channel area with lightly doped n- and the other half with the lightly doped p- channel. The CIP technique is implemented by inserting a pocket exactly at the junction of lightly doped n- &p- channel regions. Using the proposed techniques, the Ioff is reduced by ∼3.3 times (2 × 10-17 A/μm), the Iamb is reduced by a magnitude of two orders (2.39 × 10-17 A/μm) and by using the Dual-Oxide technique, the Ion is increased by 5 times (0.641 mA/μm) that of the conventional DE-QG TFET. Also, a steeper subthreshold swing (SS) of ∼57 mV/dec and one order of magnitude increase in the Ion/Ioff ratio of 3.19 × 1013 is achieved. Further, the peak overshoot voltage is suppressed by 86%, the transconductance (gm) is increased by ∼3 times (757 μA/V), and both the cut-off frequency (fT) and the Gain Bandwidth Product (GBW) are increased by ∼2.3 times (49 GHz & 5.2 GHz) respectively. The proposed device is mainly targeted towards Analog/RF applications.