Voltage-controlled Oscillator Research Articles

Trigger waves in an oscillator loop and their applications in voltage‐controlled oscillation with high tuning gain

SummaryTrigger waves, propagating in a loop of a one‐dimensional lattice of tunnel‐diode (TD) oscillators, can be effectively applied to voltage‐controlled oscillation with high tuning gain. The lattice under investigation can generate both phase and trigger waves by varying the bias voltage to the TD. We demonstrate a voltage‐controlled oscillator (VCO) achieving high tuning gain through the utilization of rotating trigger waves. As the loop size decreases, the trigger wave becomes bound to itself or to adjacent waves. At this point, the excitation motion of the individual lattice cell is constrained by the global interaction caused by the trigger wave(s), leading to coherent behavior. Consequently, the bifurcation curve of the trigger wave seamlessly connects to that of the phase wave with changes in the TD bias voltage. Owing to the trigger wave's property of significantly increasing velocity with the TD bias voltage, a VCO with very high tuning gain can be developed, leveraging the seamless dependence of the oscillation frequency on the TD bias voltage.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

Dissemination of UTC(NIST) over 20 km of commercial optical fiber with active phase stabilization.

We demonstrate the transfer of a cesium frequency standard steered to UTC(NIST) over 20 km of dark telecom optical fiber. Our dissemination scheme uses an active stabilization technique with a phase-locked voltage-controlled oscillator. Out-of-loop characterization of the optical fiber link performance is done with dual-fiber and single-fiber transfer schemes. We observe a fractional frequency instability of 1.5 × 10-12 and 2 × 10-15 at averaging intervals of 1 s and 105 s, respectively, for the link. Both schemes are sufficient to transfer the cesium clock reference without degrading the signal, with nearly an order of magnitude lower fractional frequency instability than the cesium clocks over all time scales. The simplicity of the two-fiber technique may be useful in future long-distance applications where higher stability requirements are not paramount, as it avoids technical complications involved with the single-fiber scheme.

Compact active analog device for novel applications useful for sensing and measurement

The presented research introduces a novel approach to modern modular active device and provides various practical application examples tailored for industrial sensing readouts. Straightforward implementation of single active device-based topologies in frequency bands from kHz up to MHz is presented. These applications include: an electronically linearly tunable special band-pass filter that can be easily modified into a voltage-controlled oscillator, a two-port quadratic transformer, an amplitude modulator, and an equalization circuit (which serves as a fractional-order differentiator and integrator). These circuits benefit from high-impedance voltage input and low-impedance output (easily matched to 50 Ω), high processed signal levels (often reaching hundreds of mV), and simplified topologies without redundant passive elements. These features are especially valuable in tunable and configurable solutions for modern communication, sensing, audio, and consumer electronic systems, as well as in modeling various physical and biological systems. The experiments have been provided by simulations and measurements using device VCA824.

Near-Field Probing of Microwave Oscillators with Josephson Microscopy.

Voltage-controlled oscillators, serving as fundamental components in semiconductor chips, find extensive applications in diverse modules such as phase-locked loops, clock generators, and frequency synthesizers within high-frequency integrated circuits. This study marks the first implementation of superconducting Josephson probe microscopy for near-field microwave detection on multiple voltage-controlled oscillators. Focusing on spectrum tracking, various phenomena, such as stray spectra and frequency drifts, were found under nonsteady operating states. Parasitic electromagnetic fields, originating from power supply lines and frequency divider circuits, were identified as sources of interference between units. The investigation further determined optimal working states by analyzing features of the microwave distributions. Our research not only provides insights into the optimization of circuit design and performance enhancement in oscillators but also emphasizes the significance of nondestructive near-field microwave microscopy as a pivotal tool in characterizing integrated millimeter-wave chips.

Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced charging and discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90-nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0 us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be −100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (−27 °C, 0 °C, 27 °C, 84 °C) and at various corners (NN, FS, SF, SS, FF) making it reliable in adverse circumstances.

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

High data rate and energy efficient configurable IR-UWB transmitter with an integrated balun

This paper presents a novel, digitally configurable, switching oscillator-based impulse radio ultra-wideband (IR-UWB) transmitter that is robust to process variations. The pulse width and pulse position properties of the output waveform are configurable to ensure operation for the desired bandwidth and output pulse energy values. The architecture is based on a cross-coupled LC voltage-controlled oscillator (LC VCO) implemented with a custom-designed on-chip balun at a center frequency of 2.4 GHz. With the usage of this on-chip balun, the need for an extra buffer stage is eliminated, and the highest possible efficiency is achieved with the proper turns ratio selected. The generated digital control pulse signals are also used to ensure fast start-up and UWB operation while maintaining low power consumption with an implemented on/off tail switching scheme. The presented IR-UWB transmitter that occupies a total area of 0.35 mm2 is fabricated in the United Microelectronics Corporation (UMC) 180-nm mixed-mode/radio frequency (RF) CMOS process. The measured output voltage swing of the fabricated transmitter is 0.812 V on a 50-Ω load for the 200 Mb/s data rate, and the bandwidth is measured as 902 MHz. The achieved frequency tuning range is 1 GHz and the fabricated transmitter can drive 50 Ω, 75 Ω and 100 Ω loads with measured efficiency values 4.16%, 5.76%, and 4.05%, respectively. Compared to other works in the literature, this design achieves a higher output pulse energy at a higher data rate while maintaining low power consumption and, thus, high efficiency.

Design and Simulation of VCO for RF Transceivers with Low Power, Low Phase Noise and Wider Tuning Range using Silterra 130nm CMOS Technology

The performance of low-power transceivers is required to meet stringent specifications for an advanced wireless radio frequency (RF) application. The design topology in this paper is simulated to meet the specifications and operation of VCO for low power, low phase noise and wide tuning range in complementary metal oxide semiconductor (CMOS) 130nm technology for RF transceivers. The relationship between the phase noise, power consumption and frequency turning range is fully analyzed to further improve the performance of the voltage-controlled oscillator (VCO). The architecture of the VCO employs two sets of symmetrical cross-couple split NMOS and PMOS with biased current sources operating in the triode region, and a resonator tank that achieves the desired low phase noise performance of about -110 dB/Hz at a tuning range of 4.1 to 4.5 GHz with a supply of 0.9 V. The control of the DC bias point reduces the conduction angle, which improves the current efficiency, power consumption and phase noise. The topology generates sufficient –gm for the oscillator incorporation to mitigate the start-up issue of the VCO. At the center frequency of 4.38 GHz, the VCO serves as a promising solution for improving low power and low phase for wireless communication systems and RF transceiver applications. The design consumes a very low power of 0.138 mW, achieves a phase noise of -110.53 dBc/Hz at 1 MHz offset, and a figure of merit (FoM) of -191.90 dBc/Hz.

Design and simulation optimization of phase-locked loop structure for phase-shifting power supply

A phase-locked loop (PLL) of a phase-shifting power supply for the power system is designed in this paper. Taking the industrial frequency current as the reference signal, the input and output characteristics of the phase-frequency detector with charge pump are analyzed. In addition, the transfer function of the PLL system is analyzed by combining the passive second-order low-pass filter and the voltage-controlled oscillator. As a result, the influence of parameters such as charge pump current, phase margin, and loop bandwidth on the performance of the PLL is investigated, and the optimal parameters of each section are obtained. The results show that the optimized PLL has a locking time of 0.75 s, a pull-out range of 63.16 Hz, and a locking range of 43.82 Hz, with high stability and noise immunity.

A Direct Current-Sensing VCO-Based 2nd-Order Continuous-Time Sigma-Delta Modulator for Biosensor Readout Applications.

A second-order voltage-controlled oscillator (VCO)-based continuous-time sigma-delta modulator (CTSDM) for current-sensing readout applications is proposed. Current signals from the sensor can directly be quantized by the proposed VCO-based CTSDM, which does not require any extra trans-impedance amplifiers. With the proportional-integral (PI) structure and a VCO phase integrator, the capability of second-order noise shaping is available to reduce the in-band quantization noise. The PI structure can be simply realized by a resistor in series with the integrating capacitor, which can reduce the architecture complexity and maintain the stability of the system. The current-steering digital-to-analog converter with tail and sink current sources is used on the feedback path for the subtraction of the current-type input signal. All the components of the circuit are scaling friendly and applicable to current-sensing readout applications in the Internet of Things (IoT). The proposed VCO-based CTSDM implemented in a 0.18-μm standard CMOS process has a measured signal-to-noise and distortion ratio (SNDR) of 74.6 dB at 10 kHz bandwidth and consumes 44.8 μw only under a supply voltage of 1.2 V, which can achieve a Figure-of-Merit (FoM) of 160.76 dB.

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operating at 135 GHz in 80-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR, a 405 GHz push-push voltage controller in 38-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR with an on-chip patch antenna, a 128 GHz Schottky diode frequency doubler, a 170 GHz Schottky diode detector, a 600 GHz plasma wave detector in 122-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR and a 40 GHz phase-locked loop with a frequency doubled output at 110 GHz. Given this and the trends in performance of n METAL OXIDE SEMICONDUCTOR transistors and Schottky diodes produced in complementary metal-oxide semiconductors, we lay out a plan for terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR systems and circuits, highlighting critical challenges that need to be addressed. With the advent of terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

Non-destructive Moisture Content Testing for Soil Brick Using Capacitive Measurement With 50 MHz Radio Frequency

This research paper presents a soil brick moisture measurement by capacitive measurement with radio frequency of 50 MHz and the soil brick as the dielectric material sandwiched between the conductive plates of the capacitor. The moisture content of the soil brick was considered from the capacitance storage capacity of the capacitor. The proposed measurement consisted of a voltage-controlled oscillator, capacitance measurement circuit, radio frequency amplifier, radio frequency detector, and microcontroller unit. After that, a circuit was built and assembled to the radio frequency soil moisture meter of soil bricks for evaluate the soil brick with width of 20 cm, length of 40 cm and the thickness of 20 cm. There are four types of soil brick with moisture of 10% to 30% and 10 times of iterations. From measured results, it was found that the dielectric constant and capacitive value are directed variation with moisture content of soil bricks. Therefore, the moisture content of soil bricks can be found by capacitive measurement. From the measured results, it accurate when comparing the standard measurement with an error of 4–16%.

Frequency doubler utilizing hetero gate dielectric tunnel field-effect transistor

With the rapid advancements in wireless communication and high-density integrated circuits, the demand for high-frequency sources has become paramount for transmitting vast amounts of information. Modern communication systems often utilize low-frequency sources at the transmitting end, converting them into high-frequency carriers through Intermediate Frequency (IF) for transmission to the receiving end. However, challenges arise in stabilizing high-frequency Voltage Controlled Oscillators (VCOs), leading to the necessity of Frequency Multipliers (FMs) in high-frequency circuits. While existing FMs face issues like harmonic distortion due to internal nonlinear devices, this paper proposes a single-device Frequency Doubler (FD) operation using Hetero-Gate Tunnel Field Effect Transistor (HG-TFET) with ambipolar characteristics. HG-TFET integrates high-κ (HK) materials and an HG structure in the gate dielectric, achieving independent control of tunneling distances and synchronous operation of source-to-channel and channel-to-drain tunneling currents (I SC and I CD) to facilitate FD operation. The paper presents the HG-TFET structure, process flow, and simulation models, followed by an exploration of its operating mechanism and characteristics. The FD circuit configuration, operational principles, and conditions for normal operation are detailed, emphasizing the importance of aligning I SC and I CD. The impact of adjusting HK lengths on I SC and I CD is analyzed, demonstrating the ability to independently control these currents through HG-TFET. Simulation results for FD operation under varying HK lengths (1–10 nm) validate the proposed approach. Additionally, the paper investigates the influence of dielectric constant (10–32) and gate dielectric thickness (2–5 nm) on FD performance, highlighting the potential for further optimization. In conclusion, this study establishes a foundation for normal FD operation through the symmetrical control of ambipolar and on currents using HG-TFET. The proposed structure and techniques open avenues for improving the efficiency and reliability of frequency-doubling applications in high-frequency circuits.

An Ultra-Low-Power 65 nm Single-Tank 24.5-to-29.1 GHz Gm-Enhanced CMOS LC VCO Achieving 195.2 dBc/Hz FoM at 1 MHz

A low-power single-core 24.5-to-29.1 GHz CMOS LC voltage-controlled oscillator (VCO) is presented. The proposed VCO uses an innovative differential cross-coupled architecture in which an additional pair is connected to the main pair to increase the effective transconductance, resulting in lower power consumption and reduced phase noise (PN). The proposed VCO is fabricated in a 1P9M standard CMOS process and sustains oscillation at 29.14 GHz with power consumption as low as 455 μW (650 μA from a 0.7 V supply), which is ~20% lower than a conventional CMOS LC VCO without Gm-enhanced differential pairs built through the same process (700 μA from 0.8 V supply). When consuming 880 μW (1.1 mA from 0.8 V), the proposed VCO exhibits a tuning range of 4.6 GHz (from 24.5 GHz to 29.1 GHz). Moreover, it exhibits a measured phase noise (PN) better than −106.5 dBc/Hz @ 1 MHz and −132.0 dBc/Hz @ 10 MHz, with figure-of-merit (FoM) results of 195.2 dBc/Hz and 200.3 dBc/Hz, respectively.

A Low-Intensity Pulsed Ultrasound Interface ASIC for Wearable Medical Therapeutic Device Applications

Low-intensity pulsed ultrasound (LIPUS) is a non-invasive medical therapy that has attracted recent research interest due to its therapeutic effects. However, most LIPUS driver systems currently available are large and expensive. We have proposed a LIPUS interface application-specific integrated circuit (ASIC) for use in wearable medical devices to address some of the challenges related to the size and cost of the current technologies. The proposed ASIC is a highly integrated system, incorporating a DCDC module based on a charge pump architecture, a high voltage level shifter, a half-bridge driver, a voltage-controlled oscillator, and a corresponding digital circuit module. Consequently, the functional realization of this ASIC as a LIPUS driver system requires only a few passive components. Experimental tests indicated that the chip is capable of an output of 184.2 mW or 107.2 mW with a power supply of 5 V or 3.7 V, respectively, and its power conversion efficiency is approximately 30%. This power output capacity allows the LIPUS driver system to deliver a spatial average temporal average (SATA) of 29.5 mW/cm2 or 51.6 mW/cm2 with a power supply of 3.7 V or 5 V, respectively. The total die area, including pads, is 4 mm2. The ASIC does not require inductors, improving its magnetic resonance imaging (MRI) compatibility. In summary, the proposed LIPUS interface chip presents a promising solution for the development of MRI-compatible and cost-effective wearable medical therapy devices.

A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a Gm−C filter is proposed. The reference spur is improved by 7 dB when compared with one without any Gm−C filter. The wideband integer-N PLL is designed and fabricated in UMC 65-nm CMOS process. The Gm−C filter block consumes 200 μA current. The wideband voltage-controlled oscillator (VCO) oscillates from 1.6 GHz to 3.2 GHz having a tuning range (TR) of 40%, achieving a best and worst phase noise of ≈−122 dBc/Hz and ≈−116 dBc/Hz at a 1 MHz offset, respectively.

Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient

This work suggests an all-digital temperature sensor with a high sampling rate that is based on a time-to-digital converter (TDC). Two on-chip voltage-controlled oscillators (VCOs) are used in the design of the sensor core, which senses temperatures between [Formula: see text]C and 200[Formula: see text]C. For digital code conversion, the outputs of the VCO are fed into two asynchronous counters. In both low- and high- resolution modes, the error following two-point calibration is observed between [Formula: see text]C and [Formula: see text]C. The sensor’s ability to function in both high- and low-resolution modes based on conversion time is an important feature. At a sampling frequency of 0.19[Formula: see text]MHz, the maximum resolution achieved is 0.18[Formula: see text]C. Additionally, the sensor has control logic built in to turn off the sensing as soon as the conversion is complete. At 90-nm process, 1.1[Formula: see text]V supply voltage and 27[Formula: see text]C, the proposed sensor occupies [Formula: see text] and consumes [Formula: see text].

Design of low power and low phase noise LC-VCO for Bluetooth/WLAN applications

The proposed Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) prototype design generates 2.45 GHz to 4.58 GHz of frequency using the Cadence UMC 180 nm process with a 1.8V supply. This architecture carried a new viewpoint on tank design put forth by enhancing the varactor tuning. Here, the circuit employs a CMOS differential cross-coupled pair, and rail-to-rail DC biasing achieves a higher voltage swing. Simulation analysis parameters are measured at 2.45 GHz frequency, phase noise is −123.5 dBc/1 MHz offset, power is 3.5 mW, jitter is 0.232 fsec, and it occupies 0.118 μm2 layout area. Additionally, the simulations have been extended for analysis under Process Voltage and Temperature Corners, Monte-Carlo, and Worst-Case Corners. This study obtained a better FoM of -200.94 dBc/Hz. The simulation results and FoM of the proposed design show a considerably improved than state-of-the-art framework. This LC-VCO circuit study will be suitable for implementing the sub-6 GHz charge pump phase-locked loops (CP-PLLs) system for 5G applications.