Voltage-controlled Oscillator Research Articles

A low-power quadrature voltage-controlled oscillators with LC emitter degeneration phase shift technique

This paper introduces a novel phase-shifting technique for quadrature voltage-controlled oscillators (QVCOs) utilizing an LC emitter degeneration architecture. The proposed technique enables a phase shift of up to ±90°in the transconductance of the coupling path while also generating a negative input resistance. This innovative approach avoids phase ambiguity, mitigates the trade-off between phase noise and phase error, and substantially reduces QVCO power consumption. Moreover, compared to conventional capacitance emitter degeneration methods, the LC emitter degeneration structure has a lower equivalent input capacitance, expanding the QVCO’s frequency tuning range. The designed QVCO is implemented using a 180 nm SiGe BiCMOS technology, occupying a compact area of 0.037 mm2. Post-layout simulation evaluations under various process, voltage, and temperature (PVT) conditions validate the robustness and reliability of the design. Results indicate a phase noise of 102.7 dBc/Hz at a 1 MHz offset from a 22.1 GHz carrier, a frequency tuning range of 25.2%, a phase error of 0.9°, and a power consumption of 12 mW from a 1.1 V supply, achieving a figure of merit (FoM) of 178.8 dBc/Hz.

Reduction in Optical Feedback Noise of Atomic Force Microscopy by High-Frequency Current Modulation

Introduction: With the advancement of technology, nanotechnology has emerged as a prominent research field. The Atomic Force Microscope (AFM) serves as a vital tool in nanoscience and technology, playing an indispensable role across various domains. Method: However, in the AFM photoelectric sensing system, the optical feedback noise from the beam deflection method can lead to inaccuracies in signal identification and analysis, impacting the accuracy and reliability of AFM measurements. To mitigate this interference, this study proposes a highfrequency current superposition system aimed at reducing optical feedback noise. By superimposing high-frequency currents, the semiconductor laser transitions from a single-mode to a multi-mode operational state, thereby altering its mode of operation and consequently reducing optical feedback noise during sensing. Initially, mathematical modeling and simulation analysis were conducted on the high-frequency current superposition noise reduction system to examine the impact of high-frequency current on the intensity noise of the semiconductor laser. Subsequently, the design of the high-frequency current superposition noise reduction system was outlined, encompassing the development of a constant current drive circuit, a voltage-controlled oscillator circuit, and a biasing circuit. Finally, the high-frequency current superposition noise reduction system underwent testing. Results: During the high-frequency current superposition noise reduction test, the system's Signal-to-Noise Ratio (SNR) increased from 15.57 dB to 17.81 dB, and the system's noise peak-to-peak value decreased from 8 mV to 6 mV. Analysis of the superposition frequency and noise reduction effect determined the optimal superposition frequency of the AFM photoelectric sensor system to be 400 MHz. Characterization experiments of the high-frequency superposition noise reduction system compared the clarity of Escherichia coli images before and after noise reduction. Conclusion: The aforementioned experimental results demonstrated that high-frequency current superposition is an effective noise reduction method capable of mitigating optical noise in the AFM photoelectric sensing system.

A progressive phase multiple-injection locking technique for jitter suppression in voltage-controlled ring oscillator

ABSTRACT This paper presents a jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is useful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL), and various time-based circuits whose performance is severely degraded by jitter accumulation, an inherent property of VCRO. In the proposed technique, a 1-bit time-to-digital converter (TDC) is used to extract information about jitter with a sensitivity of 4ps/bit. The rise in phase detector output bit leads VCRO to work in Progressive Phase Multi-Injection Locking (PPM-IL) mode until VCRO gets jitter-free. The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. After enabling the proposed technique, the RMS jitter reduces from 7.436 ps to 1.198ps for VCRO running at 63 MHz and consumes a total power of 1.112 mW.

Frequency linearization of voltage controlled oscillator (VCO) for 2 µs frequency modulated continuous wave (FMCW) reflectometer.

Frequency modulated continuous wave reflectometers have been widely used to measure plasma density profiles in many magnetic fusion devices. The frequency modulation (FM) time of the KSTAR reflectometer was 20 µs, that is, the FM rate was 50kHz. However, the edge density of the KSTAR tokamak fluctuates typically over the frequency range of 20-50kHz in the ELMy H-mode plasmas. Therefore, the density profile changes significantly during the FM time, causing significant distortion in the density profile measurements. The FM rate must be increased at least ten times faster than the density fluctuation frequency. A new voltage controlled oscillator (VCO) driver is designed based on the AD8067 operational amplifier to achieve a FM time of 2 µs. The VCO output frequency is linearly modulated by predistorting the tuning voltage of VCO using a 400 MSamples/s arbitrary waveform generator. The resulting output frequency of the VCO is measured by mixing the VCO output with a fixed frequency synthesizer signal and measuring the mixer intermediate frequency using a 2.5 GSamples/s digitizer. The tuning voltage is adjusted to minimize the amount by which the measured frequency deviates from the linearly modulated frequency. A simple linear adjustment proportional to the deviation does not effectively suppress the nonlinearity in FM. The response time of the VCO driver and the VCO input interface should be taken into account by solving the entire circuit equation. In this paper, the developed VCO driver circuit and the frequency linearization method are described.

A low power low phase noise wide frequency range PLL

This paper presents a low-noise, low-power, wide output frequency range phase-locked loop (PLL) for WLAN/WiFi transceivers. By employing a dual-symmetric CMOS cross-coupled pair differential inductor voltage-controlled oscillator (VCO), the design achieves low phase noise. In addition, an improved phase frequency detector (PFD) and a programmable low-mismatch charge pump (CP) with feedback compensation bias control are used to mitigate bandwidth and noise variations caused by different reference frequencies. The improved charge pump PLL (CPPLL) is designed in 65 nm CMOS process, and the chip layout occupies an area of 0.28 mm2. Post-layout simulation results indicate that the PLL has a tuning range of 4.6 GHz to 6 GHz, a phase noise of 111.7 dBc/Hz at 1 MHz offset at 5 GHz, a total power consumption of 7.14 mW, and a lock time of about 9μs.

A Highly Linear Ultra-Low-Area-and-Power CMOS Voltage-Controlled Oscillator for Autonomous Microsystems.

Voltage-controlled oscillators (VCOs) can be an excellent means of converting a magnitude into a readable value. However, their design becomes a real challenge for power-and-area-constrained applications, especially when a linear response is required. This paper presents a VCO for smart dust systems fabricated by 65 nm technology. It is designed to minimize leakage, limit high peak currents and provide an output whose frequency variation is linear with the input voltage, while allowing rail-to-rail input range swing. The oscillator occupies 592 μm2, operates in a frequency range from 43 to 53 Hz and consumes a maximum average power of 210 pW at a supply voltage of 1 V and 4 pW at 0.3 V. In addition, the proposed VCO exhibits a quasi-linear response of frequency vs. supply voltage and temperature, allowing easy temperature compensation with complementary to absolute temperature (CTAT) voltage.

Compact Electron Paramagnetic Resonance on a Chip Spectrometer Using a Single Sided Permanent Magnet.

Electron paramagnetic resonance (EPR) spectroscopy provides information about the physical and chemical properties of materials by detecting paramagnetic states. Conventional EPR measurements are performed in high Q resonator using large electromagnets which limits the available space for operando experiments. Here we present a solution toward a portable EPR sensor based on the combination of the EPR-on-a-Chip (EPRoC) and a single-sided permanent magnet. This device can be placed directly into the sample environment (i.e., catalytic reaction vessels, ultrahigh vacuum deposition chambers, aqueous environments, etc.) to conduct in situ and operando measurements. The EPRoC reported herein is comprised of an array of 14 voltage-controlled oscillator (VCO) coils oscillating at 7 GHz. By using a single grain of crystalline BDPA, EPR measurements at different positions of the magnet with respect to the VCO array were performed. It was possible to create a 2D spatial map of a 1.5 mm × 5 mm region of the magnetic field with 50 μm resolution. This allowed for the determination of the magnetic field intensity and homogeneity, which are found to be 254.69 mT and 700 ppm, respectively. The magnetic field was mapped also along the vertical direction using a thin film a-Si layer. The EPRoC and permanent magnet were combined to form a miniaturized EPR spectrometer to perform experiments on tempol (4-hydroxy-2,2,6,6-teramethylpiperidin-1-oxyl) dissolved in an 80% glycerol and 20% water solution. It was possible to determine the molecular tumbling correlation time and to establish a calibration procedure to quantify the number of spins within the sample.

A Reconfigurable, Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications.

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain-machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm2. Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW.

Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs.

Full-speed domain position sensorless control strategy for PMSM based on a novel phase-locked loop

This paper proposes a full-speed-domain position-sensor-less control strategy for precise control under forward and reverse rotation conditions to address the weak convex polarity of surface-mounted permanent magnet synchronous motor (SPMSM). The strategy comprises several key stages: pre-positioning of the rotor, constant current variable frequency (I/F) start-up, construct the Luenberger State Observer, and utilization of an improved phase-locked loop (PLL) for position estimation. In the pre-positioning stage, a constant amplitude current is applied to drag the rotor to a predetermined position. Subsequently, the I/F start-up stage accelerates the motor to a predetermined speed before transitioning to the Luenberger observer for closed-loop speed control, which is based on an extended back electromotive force (back-EMF) a two-phase rotating coordinate system. The improved PLL for position and speed estimation features three components: a phase discriminator (PD), a voltage-controlled oscillator (VCO), and loop filter (LF). Experimental results demonstrate the efficacy of the proposed strategy, showing quick start-up response, speed estimation error below 2 RPM, rotor position estimation error under 0.6 degrees post-loop closure, stable tracking during rapid speed changes, and consistent accuracy and stability even under reverse rotation conditions, thereby meeting the control strategy’s objectives.

A 60 GHz low phase noise VCO with second harmonic tail extraction in 40-nm CMOS

This work presents a 60 GHz continuously adjustable mm-wave cross-coupled voltage − controlled oscillator (VCO) utilizing an innovative frequency doubling technique in 40 nm CMOS technology. The extraction of the second harmonic is performed through a transformer from the tail of the 30 GHz fundamental VCO. The primary side of the transformer serves a dual purpose, functioning both as a filter for the second harmonic and as a balun simultaneously. The circuit incorporates a MOS varactor along with a four-bit binary weighed capacitor bank to achieve coarse and fine frequency tuning respectively. Post Layout simulation results indicate that the VCO spans a broad tuning range of 12.3 GHz, covering frequencies from 52.7 to 64.98 GHz. Phase noise (PN) remains below −96.3 dBc/Hz at a 1 MHz frequency offset within all bands Power consumption, including the output stage, is 21.8 mW from a 1.1-Volt supply. The VCO provides more than −13 dBm output power in all frequency bands and occupies a chip area of 0.53 mm2.

Microwave field mapping for EPR-on-a-chip experiments.

Electron paramagnetic resonance-on-a-chip (EPRoC) devices use small voltage-controlled oscillators (VCOs) for both the excitation and detection of the EPR signal, allowing access to unique sample environments by lifting the restrictions imposed by resonator-based EPR techniques. EPRoC devices have been successfully used at multiple frequencies (7 to 360 gigahertz) and have demonstrated their utility in producing high-resolution spectra in a variety of spin centers. To enable quantitative measurements using EPRoC devices, the spatial distribution of the B1 field produced by the VCOs must be known. As an example, the field distribution of a 12-coil VCO array EPRoC operating at 14 gigahertz is described in this study. The frequency modulation-recorded EPR spectra of a "point"-like and a thin-film sample were investigated while varying the position of both samples in three directions. The results were compared to COMSOL simulations of the B1-field intensity. The EPRoC array sensitive volume was determined to be ~19 nanoliters. Implications for possible EPR applications are discussed.

Implementation of a fully integrated memristive Chua’s chaotic circuit with a voltage-controlled oscillator

In this paper, a fully integrated memristive Chua’s chaotic circuit based on the voltage-controlled oscillator is proposed. The memristor replaces the nonlinear diode, and the VCO (voltage-controlled oscillator) replaces the LC oscillator, eliminating the need for diodes, resistors, capacitors, and other complex circuit structures. The proposed chaotic circuit occupies a small chip area, only 0.0045 mm2, and achieves low power consumption of 2.8267 mW. The chaotic circuit is fabricated using the SMIC 180 nm CMOS process. The simulation results demonstrate that the VCO circuit can generate a frequency output ranging from 358 MHz to 1.1 GHz by varying Vc from 0 V to 2.8 V, with a power supply of 3.3 V. The value range of the Lyapunov index is 1.015 ∼1.03. The circuit offers advantages such as a stable power supply, low power consumption, and a small chip area.

Comprehensive review and study for the CMOS transformer tank voltage‐controlled oscillator

AbstractThis article comprehensively reviews and studies CMOS transformer tank voltage‐controlled oscillators (VCOs) designed to improve the frequency tuning range (FTR) and minimize phase noise (PN) across a broad frequency range, particularly for mm‐wave and fifth‐generation applications. The study focuses on enhancing the performance of the oscillators to meet the demanding requirements of these advanced applications. This study thoroughly investigates and compares various strategies to increase the FTR, minimize PN, and reduce power dissipation in transformer tank VCOs. The aim is to establish fundamental guidelines for implementing transformer‐based tank VCOs. The study comprehensively reviews and analyzes the overall architecture of transformer‐based tank VCOs, presenting a detailed examination of the methods employed to enhance VCO performance. Additionally, the study illustrates the impact of the coupling factor on the VCO's performance parameters, detailing and demonstrating the overall tank circuit quality factor (Q) and resonator coupling factor (κ). A thorough understanding of PN methodology and the limitations of FTR has led to the development of innovative architectures. These include transformer‐based capacitive feedback (FB) oscillators with resistively adjusted variable inductors, as well as class‐F and inverse class‐F VCOs. These novel architectures contribute significantly to the improvement of oscillator performance.

A Low-Power Impedance-to-Frequency Converter for Frequency-Multiplexed Wearable Sensors.

We propose a low-power impedance-to-frequency (I-to-F) converter for wearable transducers that change both its resistance and capacitance in response to mechanical deformation or changes in ambient pressure. At the core of the proposed I-to-F converter is a fixed-point circuit comprising of a voltage-controlled relaxation oscillator and a proportional-to-temperature (PTAT) current reference that locks the oscillation frequency according to the impedance of the transducer. Using both analytical and measurement results we show that the operation of the proposed I-to-F converter is well matched to a specific class of sponge mechanical transducer where the system can achieve higher sensitivity when compared to a simple resistance measurement techniques. Furthermore, the oscillation frequency of the converter can be programmed to ensure that multiple transducer and I-to-F converters can communicate simultaneously over a shared channel (physical wire or virtual wireless channel) using frequency-division multiplexing. Measured results from proof-of-concept prototypes show an impedance sensitivity of 19.66 Hz/ Ω at 1.1 kΩ load impedance magnitude and a current consumption of [Formula: see text]. As a demonstration we show the application of the I-to-F converter for human gesture recognition and for radial pulse sensing.

Development of a compact control circuit for voltage-controlled oscillator with applications in laser stabilization

Development of a compact control circuit for voltage-controlled oscillator with applications in laser stabilization

A Class-C Eight-Phase Voltage-Controlled Oscillator With 184.2 dBc/Hz FoM and Loop-Based Superharmonic Coupling in 65-nm CMOS

A Class-C Eight-Phase Voltage-Controlled Oscillator With 184.2 dBc/Hz FoM and Loop-Based Superharmonic Coupling in 65-nm CMOS

Edge scanning reflectometry for density profile measurement on the SPARC tokamak.

Edge scanning reflectometry (ESRL) on the SPARC tokamak aims to measure the electron density profile from the far scrape-off layer to the top of the typical H-mode pedestal and provide real-time data for plasma control. ESRL uses a standard frequency-modulated continuous wave technique from 18 to 90GHz. By implementing both the O-mode and left-hand-cutoff X-mode, it covers densities from ∼4 × 1018 to ∼4 × 1020m-3 at B0 ∼12T. A voltage-controlled oscillator acts as the frequency sweep source. Phase-locked dielectric resonator oscillators and bandpass filters generate base signals ∼9-15GHz. The signals are then frequency multiplied and amplified to reach the K (18-26GHz), Ka (26-40GHz), U (40-60GHz), and E (60-90GHz) bands. Multi-band signals are combined via the quasi-optical technique. ESRL plans to use oversized waveguides (∼20m one-way) and a bi-static arrangement to minimize signal losses and distortions while allowing system flexibility. A COMSOL Multiphysics RF model in 2D has been set up to simulate the reflectometry process and help decide the layout of the horn antennas. Engineering analyses of the key parts of the system have been carried out in support of its preliminary design.

An octave tuning range quad-core VCO using a multi-mode resonator

This paper presents a novel multi-core multi-mode electric-magnetic (E-M) mixed-coupling voltage-controlled oscillator (VCO), achieving wide tuning range and phase noise optimization simultaneously through a multi-core structure. A symmetric multi-mode resonator is proposed to address the issue of differential signal mismatch caused by transformer asymmetry. An inductor ring is used to balance the inductance of each mode and its effect in each mode is analyzed in detail. A symmetrical switch network is employed for mode switching, offering advantages such as reduced parasitics and mismatch. The utilization of a varactor combined with a fixed capacitor enables electrical coupling, ensuring overlapping frequency bands even with variations in process, voltage, and temperature (PVT), and extending the tuning range. Furthermore, a switched resistor array is employed to bias the negative resistance pair and minimize the contribution of 1/f noise upconversion to the phase noise. Designed in a 40-nm complementary metal–oxide–semiconductor (CMOS) technology with a core area of 0.16 mm2, the VCO achieves a simulated continuous tuning range of 81.5%, spanning from 11.1 to 26.4 GHz. Operating at a 1.1 V supply with a power consumption of 16 mW, the phase noise at 12.15 GHz is −118.6 dBc/Hz at a 1 MHz offset, corresponding to a figure-of-merit (FoM) of 188.3 dBc/Hz and a FoMT of −206.3 dBc/Hz.

Application and Research of Voltage-Controlled Oscillator in Phase-Locked Loop

Application and Research of Voltage-Controlled Oscillator in Phase-Locked Loop