Voltage-controlled Oscillator Research Articles

A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

A Closed-Loop VCO-based 1-1 SMASH CT ΔΣ ADC Architecture

A novel closed-loop voltage-controlled oscillator (VCO)-based 1-1 sturdy multistage noise-shaping (SMASH) continuous-time ΔΣ ADC is presented in this paper. The proposed architecture uses VCOs as integrators and puts them in a closed loop to suppress the VCO nonlinearity. The multi-bit quantization is employed in the proposed architecture so that the requirement of a high over-sampling ratio (OSR) is relaxed while maintaining a high resolution. The architecture has been verified in MATLAB Simulink.

A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique

This article introduces a compact and low phase noise (PN) 19-GHz quad-core class-F voltage-controlled oscillator (VCO) based on a square-geometry transformer tank using the inductor-sharing technique. The proposed square-geometry transformer tank is inherently more compact than the prevalent topologies such as star geometry, dual-row geometry, and circular geometry. The inductor-sharing technique is introduced to merge neighboring inductors into smaller ones, which further reduces the chip area. Moreover, the proposed quad-core topology supports impedance boosting at harmonic frequencies without extra chip area consumption and class-F operation is adopted to achieve better PN performance. The quad-core VCO prototype is designed and fabricated in a 65-nm CMOS process. Measured performances are 17.6 to 19.4 GHz frequency range with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 137.2 dBc/Hz minimum PN at 10 MHz offset from 19 GHz carrier with 46 mW power consumption and 0.9-V supply, resulting a figure of merit (FoM) of 186.1 dBc/Hz. Thanks to the proposed square-geometry and inductor sharing technique, the proposed VCO is the smallest in quad-core VCOs with a similar operating frequency with a core chip area of 0.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.3 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and the corresponding FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{A}}$</tex-math> </inline-formula> is 196.5 dBc/Hz.

A 28-GHz Low Phase Noise Class-C Transformer VCO With 187-dBc/Hz FoM in 90-nm SiGe BiCMOS

This article presents a 27.9–28.8-GHz voltage-controlled oscillator (VCO) in a 90-nm SiGe BiCMOS process. The VCO consists of class-C active devices and a transformer tank. A transformer tank model which captures all parasitic capacitance is formulated. Several transformer design examples are studied and compared with an LC tank in terms of quality factor and tuning range. The VCO achieves a state-of-the-art phase noise of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 111.5 dBc/Hz at 1-MHz offset. The figure-of-merit (FoM) is 187 dBc/Hz, and the flicker corner is 82 kHz with a power consumption of 24.7 mW. Potential applications include phase-locked loops (PLLs) for wireless systems at 28, 60, and 90 GHz.

A W-Band Transmitter for Automotive Radar Sensors in 28-nm FD-SOI CMOS

This article presents a 77-GHz transmitter (TX) in a 28-nm fully depleted silicon-on-insulator CMOS technology for automotive radar applications. The circuit has been designed to simultaneously fulfill both short-/medium-range (S/MR) and long-range (LR) operations. It exploits an LO frequency doubling architecture, which allows preventing voltage-controlled oscillator (VCO) pulling effects for improved phase noise (PN) performance. The proposed TX comprises a 38-GHz VCO driving a frequency doubler and then a current-combining two-path power amplifier. The VCO takes advantage of a novel tank architecture to cope S/MR and LR requirements with an effective and silicon area-saving solution. The proposed TX also features a feedback loop that allows properly setting the power delivered to the output load. It exhibits a 5-GHz bandwidth, ranging from 76 to 81 GHz, with a PN performance as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 93 dBc/Hz at a 1-MHz offset frequency from a 77-GHz carrier. It is also able to deliver a maximum output power as high as 17.5 dBm with a dynamic control range of around 13 dB. The overall power consumption is 351 mW.

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider

Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

SkinAid: A Wirelessly Powered Smart Dressing Solution for Continuous Wound-Tracking Using Textile-Based Frequency Modulation.

In this article, SkinAid, a battery-free, low-cost, robust, and user-friendly smart bandage for electrochemical monitoring and sensing of chronic wounds is proposed. The working principle of the bandage is based on direct frequency modulation of a tri-electrode electrochemical sensing of wound data. The electronics and biotelemetry links were realized using low-cost manufacturing process of textile embroidery onto fabric substrate. The transmitter was represented by a bedsheet with novel corrugated crossed-dipole made of Elektrisola-7 embroidered onto gauze fabric. An input RF signal of 1 W was transmitted at 462 MHz from the bedsheet to the all-textile bandage featuring a rectifying circuit, a voltage-controlled oscillator (VCO), an electrochemical sensor, and a 915-MHz dipole for re-transmission of the modulated wound data. We demonstrate that for wound fluid emulated by various uric acid concentrations from 0.2 mM to 1.2 mM, corresponding modulated frequency varies from 1090 MHz to 1145 MHz for signals captured at 25 cm away from the bandage. For pH modulation ranging from 2 to 10, the corresponding modulated frequency was between 800 MHz and 830 MHz for signals received at more than 6 feet away from the bandage. For quick and reliable assessment, two empirical models were developed for the direct frequency modulation as a function of uric acid and pH. To the best of our knowledge, this is the first time an all-textile (fabric-integrated), battery-free and wirelessly powered smart bandage have been proposed for wound monitoring. This result can be used as a first step in developing RFID-type, battery-free, and low-cost 5G/6G smart bandages using millimeterwave and terahertz frequencies where the bedsheet can be host to a MIMO-aided beamforming.

A 52.97–60.51-GHz Voltage-Controlled Oscillator With an 8-Shaped-Inductor-Based Triple-Coil Transformer

A 52.97–60.51-GHz Voltage-Controlled Oscillator With an 8-Shaped-Inductor-Based Triple-Coil Transformer

A 103 fJ/b/dB, 10–26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement

A 10–26 Gb/s energy-efficient receiver incorporating a dual-feedback nested loop clock and data recovery circuit (DF-CDR) is proposed. Combining a direct modulation path on voltage-controlled oscillator (VCO) and phase interpolator (PI)-based phase rotator inside a phase locked loop (PLL), it improves high-frequency jitter tolerance by 0.15 UI. An edge-first equalization scheme is proposed to reduce power and hardware overhead of decision feedback equalizers. Meanwhile, it facilitates adaptive equalization of continuous time linear equalizer, and background offset calibration of the receiver frontend. A three-stage latch comparator is adopted to enable high-speed direct feedback equalizer. By applying PRBS-31 test pattern through a 32 dB loss channel, the receiver is error-free and features the best energy efficiency of 103 fJ/b/dB at 26 Gb/s.

A 42 GHz low phase noise Colpitts VCO in 180-nm SiGe BiCMOS

This paper describes a 39.1 to 42.5 GHz low phase noise Colpitts voltage-controlled oscillator (VCO) using 180-nm SiGe BiCMOS technology. In order to achieve better phase noise, an optimization method related to capacitance ratio is analyzed. Meanwhile, the linearization method is used to achieve a linearized KVCO which is robust to varactor bias variations. The simulated VCO features a tuning range of 8%, low phase noise of –95.3 dBc/Hz at 1 MHz offset, voltage supply of 3.3 V and power consumption of 40 mW, which results in a FOM T of –170 dBc/Hz.

A Single-Chip Single-Antenna Radar for Remote Vital Sign Monitoring

This article proposes an effective way to use self-injection locking (SIL) in a radar system to detect human chest cavity movement for vital signs monitoring with minimal hardware. The proposed approach expands the idea of using a phase-locked loop (PLL) system as a demodulator and a single antenna, making the system more compact. The system includes on-chip dc offset cancellation for system initialization. This work investigates and compares an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$</tex-math> </inline-formula> -based voltage-controlled oscillator (LCVCO) and a ring voltage-controlled oscillator (RVCO) in terms of primary sensitivity for motion detection and phase noise. A study of injection-locking of both the LCVCO and RVCO is also established. The study shows that the RVCO is superior to the LCVCO in terms of sensitivity while the phase noise does not differ significantly as the frequencies of interest are very small, i.e., heart rate and respiration are bandwidth-limited to a few hertz. To verify the proposed idea, a design of both systems, an LCVCO-based PLL and an RVCO-based PLL, was implemented in 65 nm CMOS technology at 1.5 GHz. The simulation and measurement results confirm the idea proposed: the RVCO shows better performance across all metrics, e.g., higher sensitivity by 4 dB, lower power consumption by 30%, and reduced area (almost half) compared to the LCVCO.

A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm2 in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

An integrated spiral DGS and an open stub meander-line resonator in the 0.13-µm BiCMOS technology for a 18-GHz band oscillator

In this paper, an 18 GHz voltage-controlled oscillator (VCO) with improved phase noise (PN) and smaller size is proposed. The filter consists of an open stub resonator and an integrated spiral Defective Ground Structure (DGS) resonator. The proposed oscillator is designed in the 0.13-µm SiGe BiCMOS technology. The differential cross-coupled VCO uses a bandpass filter. In this work, the conventional large-size coil is replaced by a resonator based on our proposed open stub resonator and defected ground structure (DGS) where the filter is equivalent to the large coil and the associated capacitors. The use of the filter results in a great reduction of VCO size, low losses, and low power consumption, hence an enhancement in the quality factor. The integrated spiral DGS is etched on the third metal layer (M3) below an open stub meander line onthe top metal layer (TM2) of the 0.13-µm top metal two (TM2) BiCMOS technology. The proposed VCO has a small die area of 0.089 mm2 and has FoMA of 188.8 dB and a power consumption is 13.38 mw. The simulated carrier frequency and phase noise are 18-GHz and −123.59 dBc/Hz (−103.7 dBc/Hz) at 10-MHz (1 MHz) offset frequency, respectively, which results in a figure of merit of 177.37 dB.

Working principle and application analysis of phase-locked loop

This article analyzes the current research status of phase-locked loops (PLLs) from multiple aspects. The working principle and components of PLL are discussed in detail, including the feedback controlling mechanism, clock skew generation and elimination, and frequency multiplication. The main components of PLL, including phase detector, low-pass filter, and voltage-controlled oscillator, are also explained in the following parts. The article further explores the applications of PLL, such as frequency synthesizers and clock and data recovery, and the challenges faced in designing PLLs. These challenges include the need for new architectures and advanced loop filters and improved phase detectors. Finally, the prospects and potential developments in PLL technology will be given. The paper will first present a comprehensive review of recent advances in PLL research, focusing on both the theoretical and practical aspects of PLL design and application. Then highlight the innovative approaches proposed by researchers to address the challenges associated with PLLs, including new architectures, advanced loop filters, and improved phase detectors.

An analytical method for phase noise evaluation in a microwave VCO stabilized by an interferometry structure

This study proposes a set of mathematical formulations to model a microwave interferometric structure to stabilize a free-running oscillator. The microwave interferometric structure employed a carrier suppression system to lock the voltage-controlled oscillator (VCO) frequency to a high-Q resonator and clean up the phase noise spectrum. Analytical relations were derived by modeling the system's stabilization loop components with an equivalent system transfer function. This model optimized the feedback loop circuits for a reliable frequency-locked structure with suitable spectral purity using well-known linear system methods. Thus, the phase noise of an oscillator's output signal locked to a high-Q cavity resonant frequency could be predicted and optimized. Furthermore, a prototype cavity-stabilized oscillator (CSO) system with commercial components wasimplemented to validate the proposed model. The results demonstrated that approximately 40 dB phase noise reduction at 10 kHz offset frequency was obtained at X-band, exhibiting good agreement with the proposed mathematical model. Moreover, the prototype structure's feedback circuits were designed, and their performance was validated using simulation and measurement data.

Ferromagnetic resonators synthesized by metal-organic decomposition epitaxy

Metal-organic decomposition epitaxy is an economical wet-chemical approach suitable to synthesize high-quality low-spin-damping films for resonator and oscillator applications. This work reports the temperature dependence of ferromagnetic resonances and associated structural and magnetic quantities of yttrium iron garnet nanofilms that coincide with single-crystal values. Despite imperfections originating from wet-chemical deposition and spin coating, the quality factor for out-of-plane and in-plane resonances approaches 600 and 1000, respectively, at room temperature and 40 GHz. These values increase with temperature and are 100 times larger than those offered by commercial devices based on complementary metal-oxide semiconductor voltage-controlled oscillators at comparable production costs.

Dead Time-Free Detection of NMR Signals Using Voltage-Controlled Oscillators

In this paper, we introduce voltage-controlled oscillators (VCOs) as a new type of nuclear magnetic resonance (NMR) detector, enabling dead time-free detection of NMR signals after an excitation pulse as well as the real-time inductive detection of Rabi oscillations during the pulse. Together with the theory of operation, we present the details of a custom-designed prototype implementation of a VCO-based NMR detector with an operating frequency around 62 MHz. The proof-of-concept measurements obtained with this prototype clearly demonstrate the possibility of performing dead time-free NMR experiments with coherent spin manipulation. Moreover, we also experimentally verified the capability of VCO-based detectors for performing real-time inductive detection of Rabi oscillations during the excitation pulse.

Voltage-controlled oscillators using CFOAs with correction terminal Z

ABSTRACT In this work, a realization of a voltage-controlled LC oscillator (VCO), using monolithic current-feedback operational amplifiers (CFOAs) with accessible correction terminal Z, is proposed. The frequency variation for the developed oscillator is obtained by replacing the capacitor in the resonant LC circuit with pairs of varactor diodes that use a common cathode. The barrier capacitance of the varactor diodes is controlled by a DC voltage obtained from an external voltage source. The proposed circuit configurations include single active element, a small number of discrete components, an operating frequency range of up to about 10 MHz and a relatively high value of the equivalent quality factor. To verify the effectiveness of the realised oscillators, results of computer simulations and experimental studies of sample electronic circuits using commercially available monolithic CFOAs with correction terminal Z are presented. Moreover, the obtained experimental results confirm the theoretical analyses of the circuits and the obtained mathematical expressions for the basic parameters, and the differences between them are within 10% and are mainly due to tolerances in the technological parameters of the used electronic components.

Voltage-controlled oscillator based analog-to-digital converter in 130-nm CMOS for biomedical applications

Medical implants and portable wireless sensors are the most serious of biomedical applications due to the dependence on limited battery lifetime. Consequently, energy efficiency integrated circuits designs must be put to higher attention. A particular distinguishing contribution of this paper is its focus on the power consumption that affects battery life and the heat dissipated for biomedical applications. This paper demonstrates a power-efficient implementation of analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO) to convert the collected analog vital signs into digital data for digital signal processing. The current-starved scheme is employed to implement the VCO efficiently with five-stage which leads to high savings in power and area. D-flip flop (D-FF) scheme is proposed to simplify the hardware architecture of the proposed reset counter. The proposed architecture is implemented with 130 nm CMOS technology and it can perform conversion of analog input signal to digital output using a straightforward hardware structure. The proposed VCO-based ADC achieves improvement in energy saving. Simulation results confirm that this work attains a power dissipation of 0.257 mW and active area of 0.007 mm2, and a very good Walden FOMW of 125 dB. The proposed methodology can implement any number of bits of the ADC by using the appropriate voltage-controlled oscillator with the convenient reset counter.

Compact and low phase noise LC‐VCO design using novel V‐shaped inductor in 0.18‐μm CMOS technology for Ku‐band applications

SummaryAn innovative, high‐quality factor, and small‐area V‐shaped inductor is presented in this article to improve the performance of voltage‐controlled oscillators (VCOs). The differential inductance of the suggested V‐shaped inductor in the resonator and the buffer is 280 pH and 630 pH, respectively. The inductor area is compacted by 42% and 76% compared to the conventional inductor with the same inductance value. Using 0.18‐ CMOS technology, the proposed V‐shaped inductor is employed to design a compact VCO operating at Ku‐band. The proposed VCO has a simulated phase noise range of −114 to −114.6 dBc/Hz, which is relatively constant. Also, its simulated frequency tuning range (FTR) is 5.6 % from 14.03 to 14.74 GHz. The power consumption is 2.2 mW. The simulated figure of merit (FoM) ranges from −193.5 to −194.2 dBc/Hz, which is enhanced by 6%. The designed VCO core area is 0.034 mm2, which is compacted by 35% compared to using a conventional spiral inductor. The achieved area‐included figure of merit ( ) is −208.7 dBc/Hz. The VCO has an output power of −6.8 dBm and a good harmonic suppression of 29.4 dB between the fundamental and the second harmonic.