Voltage Controlled Oscillator Gain Research Articles

A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance.

A Differential Ring Oscillator With Tail Current Source Control Scheme Using N-Type Oxide TFTs

In this article, a voltage-controlled oscillator (VCO) design using n-type metal oxide thin-film transistor (TFT) technology is proposed. The VCO has a differential structure delay cell based on a tail current source control scheme. The circuits were fabricated on a glass substrate using our ITO-stabilized ZnO TFT technology. According to tape-out test results, under a 15-V power supply voltage, the presented VCO can reach a 111.23–171-kHz tuning range, a 4.28-kHz/V tuning sensitivity, and 4% linearity error. When the control voltage changes from 2 to 15 V, the VCO gain range is 177.5–181.9 kHz/V. The phase noise performance was also analyzed. At 150 kHz, the phase noise of the VCO is −74.5 dBc/Hz at a frequency offset of 340 kHz. In addition, the circuit power consumption at the maximum oscillation frequency is 1.5 mW. These results indicate that the VCO can be applied to transparent and flexible sensors and digital signal processor (DSP) electronics with moderate speed requirements.

A 178.9-dB FoM 128-dB SFDR VCO-Based AFE for ExG Readouts With a Calibration-Free Differential Pulse Code Modulation Technique

This article presents a voltage-controlled oscillator (VCO)-based analog front end (AFE) for ExG readout applications with both a wide dynamic range (DR) and high linearity. By using a differential pulse code modulation (DPCM) technique, VCO non-linearity is mitigated by operating the VCO in the small-signal linear regime. To minimize power consumption from the power-hungry gain error calibration, the effect of VCO gain variation within the DPCM loop is investigated, leading to a calibration-free DPCM via a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> truncator. At the circuit level, a coarse–fine phase decoding scheme is proposed to increase signal-to-quantization-noise ratio (SQNR) while avoiding metastability issues. Fabricated in 65 nm, the AFE occupies an area of 0.056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves 94.2-dB SNDR and 95.1-dB DR in 500 Hz of bandwidth while dissipating 1.68- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power from a single 0.8-V supply, yielding a Schreier FoM of 178.9 dB. Importantly, the techniques enable a virtually distortion-less spectrum with a noise-floor limited spurious-free dynamic range (SFDR) of 128 dB. In addition, the AFE is validated with ECG and EOG recording, demonstrating complete signal capturing in the presence of motion/stimulation artifacts.

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

A 94.2-dB SNDR 142.6-μW VCO-Based Audio ADC With a Split-ADC Differential Pulse Code Modulation Architecture

This letter presents a voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) for audio applications using differential pulse code modulation (DPCM) to mitigate VCO voltage-to-frequency nonlinearity. To overcome VCO gain variation, a split-ADC architecture is employed where two sub-ADCs share one calibration unit, thereby enabling a quasideterministic background gain calibration with small delay and fast convergence speed. In addition, a hybrid dynamic element matching (DEM) is employed, which offers a lower delay and a smaller in-band mismatch noise compared to the segmented-tree DEM. Fabricated in 65 nm, the ADC achieves 94.2-dB SNDR, 97.3-dB SNR, and 100.3-dB DR in 20-kHz bandwidth while dissipating 142.6-μW power, yielding a DR-based FoM of 181.8 dB.

4.02-5.48 GHz wideband VCO with coupling reduction and small Kvco variation

ABSTRACT A wideband voltage-controlled oscillator (VCO) with coupling reduction and small VCO gain () variation has been fabricated for multi-standard RF transceivers. A high-quality factor 8-shaped inductor is adopted to reduce the magnetic coupling between inductors and optimise the phase noise of the VCO. Electromagnetic simulations of magnetic coupling are carried out between an octagonal inductor and an 8-shaped inductor, and as high as 36 dB reduction in magnetic coupling is achieved by using 8-shaped inductors. A novel varactor group is proposed to realise a constant in the fine-tuning process, in which the scheme adopts an inversion-mode MOS varactor to revise the capacitance variation of an accumulation-mode MOS varactor. Meanwhile, an extra 3-bit varactor array is employed to reduce variation in the coarse tuning process. Based on a conventional TSMC 0.18-μm CMOS process, a nearly constant of 58 MHz/V is obtained for a wide frequency range of 4.02 to 5.48 GHz. The proposed VCO achieves a phase noise of less than −119.8 dBc/Hz at 1 MHz offset. The current consumption is 4.3–8.8 mA under a source voltage of 1.8 V.

A Voltage-Controlled Ring Oscillator With VCO-Gain Variation Compensation

A voltage-controlled oscillator (VCO) with VCO-gain ( $K_{\mathrm {VCO}}$ ) variation compensation is proposed to reduce $K_{\mathrm {VCO}}$ variation in a current-mode logic (CML) ring oscillator by introducing a cross-coupled pair with capacitive degeneration that mitigates the nonlinearity of $K_{\mathrm {VCO}}$ . Designed and fabricated in a standard 0.18- $\mu \text{m}$ CMOS process, the proposed VCO can be tuned from 1.78 to 2.53 GHz, with the VCO gain variation less than 14.01%, while occupying a core area of $0.185\times0.081$ mm2 and consuming 20 mA including the bias circuitry, from a 1.8-V supply voltage. The phase noise is measured to be −92.68 dBc/Hz at 1 MHz offset and −114.97 dBc/Hz at 10 MHz offset from the high-band carrier frequency, respectively.

A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

A compact 0.045–2.3 GHz frequency synthesizer with a wide tuning range low phase noise VCO for software defined radios

A compact 0.045–2.3 GHz wideband fractional-N frequency synthesizer (FS) for software defined radios (SDR) applications is presented in this paper. Based on a single phase locked loop (PLL) that employs one integrated inductor-capacitor voltage controlled oscillator (VCO), the proposed FS can provide a wide operating frequency range. The VCO adopts an optimized circular inductor to mitigate the phase noise degradation caused by the high VCO gain. The in-band phase noise is optimized by employing current mode logic dividers and true single phase clock dividers. The PLL provides the differential outputs ranging from 2.3 to 4.6 GHz and the 0.045–2.3 GHz quadrature local oscillator signals are generated by the following divider chain. The proposed FS is implemented in TSMC 180 nm RFCMOS process and provides a phase noise performance less than − 116 dBc/Hz at 1 MHz offset. The maximum power consumption is 54 mW. The die size including pads and I/O is 1.92 mm2 with an active core area of 1.13 mm2. This proposed circuit has the great potential for SDR applications.

A wide-range 22-GHz LC-based CMOS voltage-controlled oscillator

ABSTRACTThis work presents a novel voltage-controlled oscillator (VCO) design and simulations that combine a varactor bank with a transformer in the LC tank to achieve a high-frequency range. While the varactor bank is responsible for changing the capacitance in the LC tank, the transformer acts as a means to change the value of the inductance, hence allowing tune-ability in the two main components of the VCO. A control mechanism utilises a mixed-mode circuit consisting of comparators and a state machine. It allows efficient tuning of the VCO by controlling the capacitance and transformer in the LC tank. The VCO has a 10.75–22.43 GHz frequency range and the VCO gain, KVCO, is kept at a low value ranging from 98.6 to 175.7 MHz/V. The simulated phase noise is −111 dBc/Hz at 1 MHz offset from the 10.75 GHz oscillation frequency. The circuit is designed and simulated in 28 nm CMOS technology and uses a 1 V supply drawing a typical power of 14.74 mW.

A fast-settling charge-pump PLL with constant loop bandwidth

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the $$\Delta \varSigma$$ modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump $$Icp$$ is programmed not only to compensate the variation of voltage-controlled oscillator gain $$Kvco$$ , but also for adapting to the change of divider ratio $$N_{m}$$ . This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 µm CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is − 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized $$\left( {Icp*Kvco} \right)/N_{m}$$ which is equivalent to the variation of PLL loop bandwidth ranges from − 6 to 6%.

Linear CMOS $LC$ -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop

A linear CMOS $LC$ voltage-controlled oscillator (VCO) utilizing triple-coupled inductors and a 40-GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process. The VCO utilizes triple-coupled inductors to couple varactor pairs, which compensate each other to linearize the VCO gain. The triple-coupled $LC$ tank is theoretically analyzed using equivalent circuit models. With the triple-coupled inductors, there is no need for tuning-voltage shifting circuits or dc-block capacitors, suitable for high-performance millimeter-wave (mm-wave) VCO design. A 40-GHz PLL has also been design and built around this linear $LC$ -VCO to demonstrate a stable PLL with small loop bandwidth variations. The measured tuning bandwidth, phase noise, and figure of merit (FOM $_{T}$ ) of the linear VCO is 15.8%, −100.7 dBc/Hz at 1-MHz offset, and −181.8 dBc/Hz, respectively. Utilizing the linear VCO, the experimental PLL is stably locked from 38.61 to 44.55 GHz. The PLL without output buffer consumes 76 mW from 1.5/1.0 V supplies. The measured in-band and out-band phase noise of the 40-GHz PLL are −81 dBc/Hz at 100-kHz offset, and −114.5 dBc/Hz at 10-MHz offset, respectively. Thanks to the proposed linearization method, the VCO gain shows very small variations, compared with reported works. The implemented PLL demonstrates good stabilities with small loop bandwidth variations across the operation frequency range.

Demonstration of a Highly Tunable Hybrid nMOS-Magnetic-Tunnel-Junction Ring Oscillator

A highly tunable oscillator using magnetic tunnel junctions (MTJs) has been developed through integration with CMOS ring oscillators. MTJs are used to replace the pMOS transistors in a typical CMOS inverter fabricated in 40-nm CMOS. The hybrid MTJ-CMOS devices exhibit a voltage-controlled oscillator gain of 300–500 MHz/V and are tunable with respect to both voltage and magnetic field.

A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs

This paper presents a complete methodology to model, design, and implement wide tuning-range phase-locked loops (PLLs) using a top–down approach. Mathematical equations that illustrate the contribution of the different sources of noise in the PLL are presented. Behavioral models that encompass the nonidealities of the PLL components are described using Verilog-A language. The PLL components are designed, and the noise performance of each component is evaluated using transistor-level simulations. The extracted jitter from the individual blocks is used to find the overall system noise. The proposed methodology considers the variations in the loop dynamics due to changes in the voltage-controlled oscillator gain and noise, frequency divider ratio, and charge pump current. While optimizing the PLL for maximum tuning range, the methodology also considers the tradeoff between the noise, speed, and reference spurs attenuation. The design and implementation of an integer- $N$ frequency synthesizer PLL that covers a continuous frequency range from 156.25 MHz to 10 GHz using a 65-nm CMOS technology is demonstrated in this paper. Measurement results to verify the accuracy of the models and to validate the predictions made by the simulations are provided.

A dual-band CMOS LC-VCO with highly linear frequency tuning characteristics

A dual-band wide range LC voltage controlled oscillator (VCO) with highly linear frequency tuning characteristics for GNSS application is presented. The linearity of VCO includes the coarse and fine tuning sensitivity variations, which are defined as the frequency step per-code (fstep) variation and the VCO gain (KVCO) variation, respectively. Compared to the conventional circuit topology, the proposed VCO utilizes the 4-bit (Bit<3:0>) digital signal to control a varactors array instead of the switched capacitors bank to realize the linear coarse tuning. And the 4-bit digital signal also controls the other varactors array to reduce the variation of the VCO gain. Measurement results illustrate that the output frequency range covers the whole GNSS bands with fstep and KVCO almost keeping constant. Thanks to the good linearity, the designed VCO obtains a low phase noise of −124dBc/Hz at 1MHz offset from 3.018GHz output frequency while consuming only 5mA from 1.8V supply. The proposed circuit is fabricated in 0.18μm CMOS process and the die area is 0.7mm×0.7mm.

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

In this paper, we present a voltage-controlled oscillator (VCO), which achieves highly linear frequency tuning under a low supply voltage of 0.5 V. To obtain the linear frequency tuning of a VCO, the high linearity of the threshold voltage of a varactor versus its back-gate voltage is utilized. This enables the linear capacitance tuning of the varactor; thus, a highly linear VCO can be achieved. In addition, to decrease the power consumption of the VCO, a current-reuse structure is employed as a cross-coupled pair. The proposed VCO was fabricated using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. It shows the ratio of the maximum VCO gain (KVCO) to the minimum one to be 1.28. The dc power consumption is 0.33 mW at a supply voltage of 0.5 V. The measured phase noise at 10 MHz offset is −123 dBc/Hz at an output frequency of 5.8 GHz.

A 5GHzVCO with Series VaractorBank to Compensate Large Kvco

This paper presents the design of a voltage controlled oscillator (VCO) with small VCO gain (Kvco) variation. To compensate large Kvco variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. Implemented in a 0.13m CMOS RF technology, the proposed VCO can be tuned from 4.6GH to 5.5GHz with the Kvco variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier.

A fractional-N frequency synthesizer for wireless sensor network nodes

This paper presents a fractional-N frequency synthesizer for wireless sensor network (WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop (PLL) based structure, which employs an LC voltage-controlled oscillator (VCO) with small VCO gain (KVCO) and frequency step (fstep) variations, a charge pump (CP) with current changing in proportion with the division ratio and a 20-bit ΔΣ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups' sizes are arranged according to the maximal allowed KVCO variation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13 μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is −86.34 dBc/Hz at 100 kHz offset and −114.17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 kHz, which meet the WSN nodes' requirements.

A finite state machine read-out chip for integrated surface acoustic wave sensors

A finite state machine based integrated sensor circuit suitable for the read-out module of a monolithically integrated SAW sensor on Si is reported. The primary sensor closed loop consists of a voltage controlled oscillator (VCO), a peak detecting comparator, a finite state machine (FSM), and a monolithically integrated SAW sensor device. The output of the system oscillates within a narrow voltage range that correlates with the SAW pass-band response. The period of oscillation is of the order of the SAW phase delay. We use timing information from the FSM to convert SAW phase delay to an on-chip 10bit digital output operating on the principle of time to digital conversion (TDC). The control inputs of this digital conversion block are generated by a second finite state machine operating under a divided system clock. The average output varies with changes in SAW center frequency, thus tracking mass sensing events in real time. Based on measured VCO gain of 16MHz/V our system will convert a 10kHz SAW frequency shift to a corresponding mean voltage shift of 0.7mV. A corresponding shift in phase delay is converted to a one or two bit shift in the TDC output code. The system can handle alternate SAW center frequencies and group delays simply by adjusting the VCO control and TDC delay control inputs. Because of frequency to voltage and phase to digital conversion, this topology does not require external frequency counter setups and is uniquely suitable for full monolithic integration of autonomous sensor systems and tags.