Voltage Complementary Metal Oxide Semiconductor Research Articles

A 62 ppm MDR Deviation and Sub-250 ns MTIE Railway Balise

A balise is a specialized device utilized for train communication and control. However, existing balises are composed of separate components, resulting in high production costs, low integration, and significant room for improvement in stability. We propose an integrated solution, to enhance the integration of balises, reducing the number of discrete components. Additionally, we propose a feedback-enabled energy extraction circuit with a limiter-based startup circuit, to enhance the stability of the balise system. The prototype was fabricated using 180 nm high voltage(HV) complementary metal oxide semiconductor(CMOS) technology. Once implemented in the balise, the number of discrete components in the system is reduced by 25%, and the system can start up within 20 ms and operate stably. The mean data rate (MDR) deviation of the balise is only 62 ppm, which is 69% lower than that specified in the test specification for the Eurobalise form–fit–function interface specification (FFFIS), and the maximum time interval error (MTIE) is less than 250 ns.

Design and Performance Analysis of Improved FIR Filter using Ultra-Scale FPGA

It is discussed in many studies and demonstrated in many pieces of research that based on certain applications, analog design of filter has several issues including complex design, re-use limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design, the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital Finite Impulse Response (FIR) filter designed is demonstrated using Ultra-Scale Field Programming Gate Array (FPGA) having chip XCKU3P. The filter is designed using a coefficient multiplier via Canonic Signed Digit (CSD) Technique. The optimized design of the digital filter is conducted via real-time implementation is performed using Ultra-Scale FPGA. The filter is designed and evaluated with an ordinary filter at 10 MHz and 10 GHz frequencies. The performance analysis of the system is illustrated using the response rate at the bitstream of 16-bit. In the results, it is demonstrated that for 10 MHz frequency design FIR filter in FPGA the 30% faster response filter is achieved at for 10 GHz, the 15% faster response is achieved at the I/O standard of Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS). The optimization of 30% in terms of the response time of the filter is attained using the proposed work. The proposed improved FIR filter design using Ultra-Scale FPGA helps in increasing design performance to increase the speed of overall response of FIR filter that is lacking in ordinary Filters.

Comparative performance analysis of AES encryption algorithm for various LVCMOS on different FPGAs

PurposePrivacy and security of personal data is the prime concern in any communication. Security algorithms play a crucial role in privacy preserving and are used extensively. Therefore, these algorithms need to be effective as well as energy-efficient. Advanced Encryption Standards (AES) is one of the efficient security algorithms. The principal purpose of this research is to design Energy efficient implementation of AES, as it is one of the important aspects for a step toward green computing.Design/methodology/approachThis paper presents a low voltage complementary metal oxide semiconductor (LVCMOS) based energy efficient architecture for AES encryption algorithm on Field Programmable Gate Array (FPGA) platform. The experiments are performed for five different FPGAs at different input/output standards of LVCMOS. Experiments are performed separately at two frequencies (default and 1.6 GHz).FindingsThe comparative study of total on-chip power consumption for different frequency suggested that LVCMOS12 performed best for all the FPGAs. Also, Kintex-7 Low Voltage was found to be the best performing FPGA. At 1.6 GHz frequency, the authors observed 55% less on-chip power consumption when switched from Artix-7 with LVCMOS33 (maximum power consuming combination) to Kintex-7 Low Voltage with LVCMOS12. Mathematical models are developed for the proposed design.Originality/valueThe green implementation of AES algorithm based on LVCMOS standards has not been explored yet by researchers. The energy efficient implementation of AES will certainly be beneficial for society as it will consume less power and dissipate lesser heat to environment.

Optimum sizing of the sleep transistor in MTCMOS technology

Multi-threshold voltage complementary metal-oxide semiconductor (MTCMOS) technology finds a wide variety of applications in reducing the subthreshold-leakage current in both combinational and sequential circuits. This is due to the fact that slightly increasing the threshold voltage causes a dramatic decrease in the subthreshold-leakage current. One of the most important applications of the MTCMOS technology is the use of a sleep transistor with high threshold voltage. However, the decision on the sizing of the sleep transistor is a critical issue because there are various trade-offs that the designer must face with this respect. In this paper, the area, the static and dynamic-power consumption, and the time delay are investigated with respect to the aspect ratio of the sleep transistor with compact-form expressions derived for them. Accordingly, the optimal size of the sleep transistor is determined quantitatively. In addition, a realistic figure of merit (FOM) that takes into account the contradicting parameters when sizing the sleep transistor is introduced and verified by simulations. The results are discussed for various cases of the logic circuit at hand. The results obtained are also verified by simulation adopting the Berkeley predictive technology model (BPTM) of the 45 nm, 32 nm, and 22 nm CMOS technologies with power-supply voltages, VDD, equal to 1 V, 0.9 V, and 0.8 V, respectively.

Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

FPGA based Green Digital Clock Design for Network Synchronization using LVCMOS I/O Standard

The idea is to develop a green digital clock design that consumes least amount of power for its network specific operation. Low Voltage complementary metal oxide semiconductor i.e. LVCMOS IO standard is used at fixed temperature and changing output load at various frequencies. FPGA family used is Virtex-6 and software used of simulation of proposed algorithm for digital clock is Xilinx. Coding is done using Verilog. The results are taken for LVCMOS at frequency of 0.1GHz, 1GHz, 10GHz and 100 GHz and data is collected to prove it green digital clock. For making any device green means the amount of power consumed by it should be small with desirable output. There is 89.60%, 98.56%, 99.46% and 99.56% saving in IOs power when we reduce output load from 5000pF to 500pF, 50pF, 5pF and 0.5pF respectively.

Energy Efficient CRC Design for Processor of Workstation, and Server using LVCMOS

In our work we have designed CRC using the LVCMOS IO standards which are stands for Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with four kinds of LVCMOS (LVCMOS 12, LVCMOS 15, LVCMOS 18, LVCMOS 25). For LVCMOS 12 when we scaled down the frequency form 50GHz to 10 GHz we found 64.41% reduction in total power. For LVCMOS 15 when we change down the frequency form 50GHz to 10GHz we found 67.58% reduction in total power. For LVCMOS 18 when we scaled down the frequency form 50GHz to 10 GHz we found 69.54% reduction in total power. In last when we reduced the frequency form 50GHz to 10GHz in LVCMOS 25 we found 64.41% reduction in total power. Our CRC design is implemented on Virtex-6 FPGA family.

Comparison of Low Power CMOS Voltage Reference Circuit Using Different Types of Charge Pumps

Background: The voltage reference circuits are mainly used in the portable devices like mobiles, laptops for the long battery runtime. Due to this voltage reference circuits the circuit can be operated in the very low supply voltage because of this the power consumption of the circuit can be reduced. Method Adopted: In this paper the low power Complementary Metal-Oxide-Semiconductor (CMOS) voltage has been designed by using the conventional charge pump and to achieve the better low power consumption voltage reference circuits and high constant voltage reference different types of charge pumps like Dickson charge pump and the Static Charge Transfer Switch (CTS) charge pump has been replaced in the place of the conventional charge pump. The conventional CMOS volatge reference circuit has the power consumption of 1.007μW and the constant voltage reference of 210mV. Findings: By using the Dickson charge pump the power consumption has been reduced to 1.389μW and the constant voltage reference has been icreased to 231mV. Similarly by using by using the Static (CTS) charge pump the power consumption has been reduced to 0.803μW and the constant voltage reference has been icreased to 229.03mV compared to the reference voltage circuit using the conventional charge pump. Improvements: The CMOS voltage reference circuit has been designed by using the two types of the charge pump Dickson charge pump and the Static CTS charge pump and all the power consumption and the constant voltage reference circuits has been compared.

Input/output Buffer based Vedic Multiplier Design for Thermal Aware Energy Efficient Digital Signal Processing on 28nm FPGA

Multiplier is used for multiplication of a signal and a constant in Digital Signal Processing (DSP). 28nm tech-nology based Vedic multiplier is implemented with use of VHDL HDL, Xilinx ISE, Kintex-7 FPGA and Xpower Analyser. Vedic multiplier gains speed improvements by parallelizing the generation of partial prod-ucts with their concurrent summations. In this work, we are exploring the feasibility of Vedic multiplier in Data Encryption Algorithm, DSP, reliable system, multimedia and fault tolerant systems. In our work, we are using 11 different IO standards from HSTL (High Speed Transistor Logic) and LVCMOS (Low Voltage Comple-mentary Metal Oxide Semiconductor) family. IO standards are used to match the impedance of transmission line, input/output port and device. The energy-efficient multipliers play a significant role in portable computing and communication systems also. Here we are using Field Programmable Gate Array (FPGA) in order to re-duce the development cost. The development cost for Application Specific Integrated Circuits (ASICs) are high in compare to FPGA. Selection of the most energy efficient IO standards in place of signal gating is the main design methodology for design of energy efficient Vedic multiplier. There is 68.51%, 69.86%, 74.65%, and 78.39% contraction in total power of Vedic multiplier on 28nm Kintex-7 FPGA, when we use HSTL_II in place of HSTL_II_DCI_18 at 56.7oC, 53.5oC, 40oC and 21oC respectively.

Efficient self‐powered convertor with digitally controlled oscillator‐based adaptive maximum power point tracking and RF kick‐start for ultralow‐voltage thermoelectric energy harvesting

A self-powered convertor for thermoelectric energy harvesting in body sensor nodes (BSNs) is designed to boost extremely low voltage to the typical supply voltage of BSNs. An adaptive maximum power point tracking (MPPT) based on digitally controlled oscillator (DCO) is achieved by adjusting the switching frequency according to the relation between the half open-circuit voltage of thermoelectric generator and the equivalent voltage. DCO exhibits small line sensitivity and temperature coefficient (TC). Radio frequency (RF) kick-start based on a self-synchronous rectifier is introduced to achieve the no-battery effect. A modified zero current switching based on the common-gate comparator is utilised to decrease the power dissipation of power metal–oxide–semiconductor field-effect transistors. In addition, the power dissipation of the main blocks is reduced by discontinuing the clocked and common-gate comparators after comparison in each cycle, and by making most transistors of DCO and the complementary metal-oxide-semiconductor (CMOS) voltage reference work in the weak inversion or linear region. The zero TC principle of the CMOS voltage reference is extended to all process. The novel convertor is designed and verified in Central Semiconductor Manufacturing Corporation CMOS 0.18 µm process. The results reveal that it achieves adaptive MPPT without battery and exhibits a peak end-to-end efficiency of about 63%.

Flexible Complementary Oxide–Semiconductor-Based Circuits Employing n-Channel ZnO and p-Channel SnO Thin-Film Transistors

In this letter, we report flexible fully oxide-based complementary metal–oxide–semiconductor (CMOS) inverters and ring oscillators by the monolithic integration of flexible n-channel zinc oxide (ZnO) and p-channel tin monoxide (SnO) thin-film transistors (TFTs). Inverted-staggered bottom-gated TFTs were fabricated by a low-temperature RF-sputtering technique. The static voltage gain of a flexible oxide-TFT-based CMOS inverter with a geometric aspect ratio of 5 is $\sim 12$ at a supplied voltage ( $\text{V}_{\mathrm {DD}}$ ) of 12 V. An oscillation frequency of $\sim 18.4$ kHz is obtained from a five-stage flexible oxide-TFT-based CMOS voltage control ring oscillator at $\text{V}_{\mathrm {DD}}$ of 12 V. Degradations of TFTs, inverters, and ring oscillators have been observed when a mechanical tensile strain is applied, whereas the influence of compressive strain is negligible.

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Optimal transistor sizing for maximum yield in variation‐aware standard cell design

SummaryProcess variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst‐case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low‐power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [−40 °C, 125 °C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)‐level Monte Carlo analysis confirmed the estimated yield of the obtained circuits. Copyright © 2015 John Wiley & Sons, Ltd.

Low Voltage Complementary Metal Oxide Semiconductor Based Internet of Things Enable Energy Efficient RAM Design on 40nm and 65nm FPGA

Low Voltage Complementary Metal Oxide Semiconductor Based Internet of Things Enable Energy Efficient RAM Design on 40nm and 65nm FPGA

Temperature Sensing Based Energy Efficient Vedic Multiplier Design Using Either Proportionality or Similarity

In this project, an innovative design of energy efficient Vedic Multiplier using a prehistoric Vedic mathematics method known as have been implemented on FPGA. Anurupyena Shunyamanyat is a Sanskrit name which in simple words means ' proportionality 'or ' similarly '. This Sutra is highly useful to find products of two numbers when both of them are near the frequent bases like 10, 50, 500 etc (multiples of powers of 10). Lesser time and energy efficient is today's world demand. Choice of IO Standard plays a very important role in power indulgence design. So, we have selected most energy efficient IO standard Low Voltage Complementary Metal Oxide Semiconductor also called LVCMOS. Then, we try to achieve more energy efficiency with different technology (40nm and 28nm) based FPGA. Virtex-6 and Kintex-7 are the platforms which have been used in this project. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 were tested on 28nm and 40nm FPGA. In this project we have observed approx 87-88% decrease in leakage power dissipation when we shift from 40nm to 28nm technology based FPGA.

Blue enhanced vertically stacked quad junction photodetector with opto window

A vertically stacked quad junction photodetector (PD) with an enhanced spectral responsivity for blue light is presented. This PD is implemented in a 0.35 µm high voltage complementary metal-oxide semiconductor (CMOS) technology. In addition, an optical window, an antireflection coating and a modified p + doping are used to attain the enhancement for blue light. The proposed PD is compared against other state of the art implementations and characterised for its spectral response.

A Highly Miniaturized Low-Power CMOS-Based pH Monitoring Platform

This paper presents the design and fabrication of a wireless, highly miniaturized, low-power electrochemical pH sensing system employing complementary metal-oxide- semiconductor (CMOS) electronics. Since plasma pH readings directly correlate to carbon dioxide levels present in the human body, this paper holds great promise for continuous monitoring of carbon dioxide in totally implantable device applications. In this paper, we have integrated a CMOS voltage controlled oscillator, which consumes only 120 μW of power and occupies an area of 0.045 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , together with a miniature electrochemical pH sensor which detects real-time changes in pH levels. The fabricated sensor employs an electropolymerized poly(o-phenylenediamine) layer atop a platinum working electrode which yields linear operation well above and below the physiological pH range of 7.38-7.42, with sensitivities as high as 56 mV/pH. In turn, the fabricated CMOS electronics convert the voltage generated by the sensor to output frequency pulses in a linear fashion. Furthermore, a wireless transmission link was designed which broadcasts the resulting sensor data to a computer which displays real-time continuous pH readings. The miniature footprint of both the sensor and electronics, together with its low power consumption, renders this a versatile platform for facile carbon dioxide monitoring and other metabolic sensing systems.

Complementary Oxide–Semiconductor-Based Circuits With n-Channel ZnO and p-Channel SnO Thin-Film Transistors

Fully oxide thin-film transistor (TFT)-based complementary metal-oxide-semiconductor (CMOS) ring oscillators are reported, for the first time, using large-area-compatible sputtering processes. The p-channel tin monoxide (SnO) and n-channel zinc oxide (ZnO) TFTs used in the CMOS inverter have inverted-staggered bottom-gate structures. The SnO TFT exhibits a threshold voltage (Vth) of 3.5 V, field-effect mobility of 0.33 cm 2 /V-s, subthreshold swing of 2.5 V/decade, and ON/OFF current ratio of ~10 3 . The corresponding values for the ZnO TFT are 6.22 V, 3.5 cm 2 /V-s, 350 mV/decade, and >10 6 . The achieved voltage gain of the CMOS inverters is ~17 at a supplied voltage (VDD) of 10 V when the geometric aspect ratio is 5. An oscillation frequency of 2 kHz is obtained from a five-stage oxide-based CMOS voltage control oscillator at (VDD) of 14 V.

A New Low-voltage Tunable CMOS VDTA-based 10MHz LP/BP Filter

In this paper, a new low-voltage complementary metal oxide semiconductor voltage differencing transconductance amplifier is proposed, and its performance is demonstrated by comparing its theory and simulated results with conventional versions. The main advantage of the proposed voltage differencing transconductance amplifier is that there are only two transistors composing a path from Vdd to Vss. A secondary advantage is that it can operate at very low voltages of less than ± 0.6V, which is superior to that of conventional models that require ± 0.9V and ± 2V. Additionally, a 10MHz multifunction filter is designed with the proposed complementary metal oxide semiconductor voltage differencing transconductance amplifier, which works both as a lowpass filter and a bandpass filter. The performance of the proposed voltage differencing transconductance amplifier and filter is verified using an HSPICE simulation with complementary metal oxide semiconductor 0.18㎛ process parameters.

Design and analysis of a single-stage source coupled complementary metal oxide semiconductor voltage control oscillator using 45 nm technology

This paper deals with the design and performance analysis of a single-stage source coupled complementary metal oxide semiconductor voltage controlled oscillator (VCO). VCO is a crucial component in many wireless communication and signal processing systems. Single-stage VCO provides effective power reduction in comparison to the traditional LC tank (LC circuit known as resonant circuit, or tank circuit, which consists of an inductor [L] and a capacitor [C]) and ring VCO. By reducing the noise source, we have provided the single-stage VCO circuit with a low phase noise performance. The VCO is intended to control as a frequency synthesiser in a phase locked loop (PLL) to generate local oscillation frequency. The proposed single-stage VCO is implemented in 180 nm and 45 nm cadence virtuoso environment. VCO provides high oscillation frequency (THz), less power dissipation (1.708 × 10‒21 W) and lower delay (50.4 fsec) in 45 nm technology with (V dd = 0.7 V). Simulation result shows an effective performance improvement in 45 nm technology in comparison to 180 nm technology.