Voltage Calibration Research Articles

47‐1: Invited Paper: A 6Gbps Intra‐Panel Interface with Video Image Compression for Next Generation Displays

This paper proposes a 6Gbps receiver for 8K 240Hz OLED display. In the proposed receiver, video image compression is presented to double the effective data bandwidth. In addition, it proposes dual path CTLE offset voltage calibration and CTLE adaptation with eye margin tester to implement 6Gbps receiver. The prototype IC is implemented in a 0.18μm HVCMOS process and is evaluated as an 8K 65‐inch panel.

Calibration and Validation of INA219 as Sensor Power Monitoring System using Linear Regression

Electricity demand which increases up to 2.7%, needs to be evaluated to prevent power wastage. This paper proposes an INA219 sensor and a power monitoring solution based on the ESP8266. Power Monitoring stores and displays real-time data in Google Sheets via Blynk version 1.0.1. The system has been calibrated with a fixed LED and resistor as a voltage calibration load. Meanwhile, the lamp and shunt resistors calibrate the shunt voltage. The measuring tools for comparison in calibration are digital multimeters, oscilloscopes, and power data loggers. Calibration using the linear regression technique with accuracy, precision, and uncertainty analysis are determined by Mean Absolute Percent Error (MAPE), Relative Standard Deviation (RSD), and Gaussian distribution. Successively, the sensor coefficient of determination (R2), accuracy, precision, and uncertainty of the load voltage and shunt voltage are 0.999 and 0.997, 99.27% ​​and 93.71%, 99.82% and 99.55%, 0.37 V and 0.89 mV.

Digital Calibration of Input Offset Voltage and Its Implementation in FDDA Circuits

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage VIN_OFF of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the VIN_OFF of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage VDD = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations.

CALIBRATION OF 122 SENSL MICROFJ-60035 SIPMS AND THE REDUCTION OF OPTICAL CROSS-TALK DUE TO COUPLED LIGHT GUIDES

Recent silicon photomultipliers (SiPMs) boast excellent production quality, eliminating the need for individual breakdown voltage calibration. We present measurements of cross-talk probability and relative gain for 122 SensL MicroFJ-60035-TSV SiPMs. These semiconductor photosensors have replaced photomultiplier tubes in many applications due to their single-photon resolution, insensitivity to magnetic fields, robustness, and cost-effective photon detection at lower voltages. Light guides expand SiPMs' small photosensitive area, and optical coupling reduces cross-talk probability compared to bare sensors at nominal bias voltage, as demonstrated in this study.

Lightweight Read Reference Voltage Calibration Strategy for Improving 3-D TLC NAND Flash Memory Reliability

Flash memory has gradually become the dominant storage device in the consumer market and data centers since the storage capacity increases and production costs decline. Unfortunately, as the bit density of flash memory increased, the severity of reliability issues has escalated. Read retry is necessary to recover high bit-error-rate flash data; however, read retry requires the flash to perform sequential read operations, which significantly increases read latency. To improve the flash memory read performance, a reliable adaptive optimization strategy for flash memory read reference voltage (RRV) is urgently needed. In this paper, we performed a full range of error characterization tests on three-dimensional (3-D) triple-level cell (TLC) flash memory, focusing on the effects of retention leakage, P/E wear, and interlayer variation on the threshold voltage. Finally, a lightweight flash memory RRV calibration strategy was constructed. The experiment results show that the predicted RRV using the proposed strategy is very close to the actual optimal RRV, reducing the raw bit error rate (RBER) of the same model of flash memory by up to 93.2%.

Main results of supplementary comparisons of high voltage and current measuring systems

High voltages of alternative current (AC) are important because they are needed for numerous applications in physics and engineering. High AC voltages are also used to test insulating materials for their dielectric properties. Calibrations of instruments for high-voltage measurements should provide metrological traceability to national standards. This applies to the requirements for both voltage measuring instruments and current measuring instruments. The transformer for high-voltage measurements is used to reduce the values of currents and voltages during measurements in high-voltage electrical networks.
 Voltage transformers (VTs) are used to accurately measure high AC voltages. Current transformers (CTs) are used to convert line currents in power systems to levels that are acceptable for other measuring instruments, which are necessary to trip protective devices. There are measuring installations that are well known for accurate measurements of the CT coefficient for large primary currents, and systems for determining the behaviour of the industrial current and VT under distorted waveforms, etc. The calibration of a high voltage measuring system must be traceable to national or international measurement standards. Mutual comparisons of calibration results of CT and VT standards are carried out with the participation of several national laboratories.
 The results of high voltage transformer measuring systems (GULFMET.EM-S6) and high current transformer measuring systems (GULFMET.EM-S7) supplementary comparisons are described. The comparisons were carried out between national laboratories from three Regional Metrology Organizations. In general, the participants of both comparisons have demonstrated a good agreement of the results in the ratio error and phase displacement for high voltage and current. The comparison results may be used to improve the participants’ existing calibration and measurement capabilities entries in the Key Comparison Database (KCDB) of the International Bureau of Weights and Measures (BIPM).

Characterization of developed low thermal scanner for DC voltage measurement

A low thermal scanner has been completely developed for improving DC voltage calibration from semi-automatic to fully automatic measurement system. The application of the switching system inside the built-up scanner introduced offset voltage to the measurement due to thermal electromotive force (EMF). A differential measurement method was proposed to characterize the thermal EMF of the scanner, and this method has been compared to previous characterization using the direct measurement method. The results show that the differential measurement method could minimize the thermal EMF effect, and the thermal EMF had a negligible contribution to the measurement for uncertainty levels around 10 to 11 ppm. Therefore, the differential measurement method is recommended for DC voltage calibration with uncertainty levels below 10 ppm since the thermal EMF can significantly affect the measurement. Furthermore, the direct measurement method is suggested for DC voltage calibration with uncertainty levels above 11 ppm since it can speed up the measurement process.

Determination of the junction intrinsic recombination velocity of minority carriers in the base of parallel vertical multi junctions’ silicon solar cell using the open-circuit voltage calibration curve technique

Determination of the junction intrinsic recombination velocity of minority carriers in the base of parallel vertical multi junctions’ silicon solar cell using the open-circuit voltage calibration curve technique

Comparison of a Modern Digital Mechanomyograph to a Mechanomyograph Utilizing an Archival Grass Force Transducer.

Mechanomyography is the traditional gold standard research technique for quantitative assessment of neuromuscular blockade. Mechanomyography directly measures the isometric force generated by the thumb in response to ulnar nerve stimulation. Researchers must construct their own mechanomyographs since commercial instruments are no longer available. A mechanomyograph was constructed, and its performance was compared against an archival mechanomyography system from the 1970s that utilized an FT-10 Grass force transducer, hypothesizing that train-of-four ratios recorded on each device would be equivalent. A mechanomyograph was constructed using 3D-printed components and modern electronics. An archival mechanomyography system was assembled from original components, including an FT-10 Grass force transducer. Signal digitization for computerized data collection was utilized instead of the original paper strip chart recorder. Both devices were calibrated with standard weights to demonstrate linear voltage response curves. The mechanomyographs were affixed to opposite arms of patients undergoing surgery, and the train-of-four ratio was measured during the onset and recovery from rocuronium neuromuscular blockade. Calibration measurements exhibited a positive linear association between voltage output and calibration weights with a linear correlation coefficient of 1.00 for both mechanomyography devices. The new mechanomyograph had better precision and measurement sensitivity than the archival system: 5.3 mV versus 15.5 mV and 1.6 mV versus 5.7 mV, respectively (P < 0.001 for both). A total of 767 pairs of train-of-four ratio measurements obtained from eight patients had positive linear association (R 2 = 0.94; P < 0.001). Bland-Altman analysis resulted in bias of 3.8% and limits of agreement of -13% and 21%. The new mechanomyograph resulted in similar train-of-four ratio measurements compared to an archival mechanomyography system utilizing an FT-10 Grass force transducer. These results demonstrated continuity of gold standard measurement of neuromuscular blockade spanning nearly 50 yr, despite significant changes in the instrumentation technology.

Research on Non-Invasive Floating Ground Voltage Measurement and Calibration Method

Voltage measurement is an important part of power system operation, and non-intrusive voltage sensors have the advantages of low insulation difficulty, simple structure, easy loading and unloading, and high construction safety, which have become a new direction for voltage measurement. Based on the principle of electric field coupling, this paper constructs a non-intrusive floating ground three-capacitance voltage measurement model, which can complete the accurate measurement of voltage without connecting with the line to be measured and the earth in the measurement process. In non-intrusive voltage measurement, the change of the object to be measured or the measurement environment will cause the change of the coupling capacitance, which leads to the uncertainty of the transmission relationship of the sensor and the large error of measurement results. In order to solve this problem, a new method of sensor calibration is proposed in this paper. By sampling capacitance in parallel between two electrodes of the sensor, changing the capacitance value, and establishing an input output equation, the coupling capacitance value and the voltage value to be measured under different operating conditions are solved. In addition, the sampling capacitance is often several orders of magnitude larger than the sensor’s own capacitance, making the sensor’s voltage division ratio significantly higher and more conducive to the measurement of high voltages. The experimental results show that the measurement error is less than 2%, which verifies the feasibility of the method and the accuracy of the voltage measurement.

Voltage–current locus‐based stator winding inter‐turn fault detection in induction motors

SummaryMonitoring the condition of induction motors requires continuous inspection of all motor components. The three‐phase stator windings forming the critical components of the motors and handling heavy currents as high as twice the blocked rotor current under inter‐turn short circuits necessitate a fault detection system that is efficient, appropriate, and worthwhile. The proposed algorithm takes measurements of the three‐phase supply voltages and phase currents and plots their loci for each cycle under various fault levels. The proposed simple, nonintrusive, less expensive, and fault‐sensitive voltage–current loci (£(v–i))‐based technique accurately identifies the faulty phase and detects stator inter‐turn faults (SITFs). In addition, the algorithm corrects supply voltage imbalances, winding asymmetries, and calibration errors of sensing elements. It contributes to examining the insulation condition of the stator windings at the onset and identifying the faulty phase of a motor. The experimental results for a 1 hp, 415 V squirrel‐cage induction motor (SCIM) in a laboratory investigation validate the competence of the proposed technique under various fault levels and load conditions.

Low-power high-dynamic-range analog front-end for picosecond waveform sampling ASICs

This short communication presents an analog front-end (AFE) circuit used in the switched-capacitor array (SCA) for the waveform sampling ASIC. The idea to use in SCA-AFE native transistors which are common in today’s CMOS technologies offers a feasible solution to the issue of achieving picosecond time resolution with a low supply voltage. The circuit features a MOS capacitor and a source follower both of which are implemented with the native transistors, and a simple rail-to-rail comparator. A prototype PISTWAVE1 ASIC is designed in a 55 nm CMOS with a single 1.2 V supply voltage, the experimental results show the ASIC achieves a dynamic range of 0.1∼1.1 V, a 65.3 dB signal-to-noise ratio (SNR) with voltage calibration and a less than 10 ps time resolution. The overall power consumption is less than 10 mW/channel at a sampling rate of nearly 6 GS/s.

Research and application of high voltage measurement technology in DC UHV preventive test

With the state’s high attention to clean energy and the requirement to reduce the loss of power grid transmission lines, DC UHV has developed rapidly in recent years. It refers to DC transmission and related technologies with voltage levels of ±800 kV (±750 kV) and above. In the power system, DC high-voltage transmission is inseparable from power equipment, but the higher the transmission voltage level, the higher the voltage of DC withstand voltage preventive test. Before the transmission of UHV DC transmission lines, if the DC voltage withstand device is 800 kV or above, the voltage withstand test shall not be carried out for the high-voltage line. The traditional direct comparison method using voltage divider cannot be used to measure the DC output voltage of DC UHV withstand voltage device on site. This paper analyzes the method of full coverage of DC UHV system in limited voltage range and the method of out of range calibration using scale factor. In order to solve the problem of voltage traceability in the DC high voltage generator, especially the voltage traceability of the field DC UHV device, when the voltage output range of the calibrated DC high voltage generator exceeds the measurement range of the standard, the standard value of the voltage calibration point beyond the range can be determined by comparison and obtained through the linearity test. The comparison with the standard shall be conducted at a voltage not lower than 20% of the rated voltage of the calibrated DC high voltage generator, and compared to the maximum voltage of the standard voltage divider. The comparison is carried out at a (a ≥ 2) voltage point. When comparing at a point, the highest voltage level is equal to the upper limit of the standard. Under a voltage point, according to the mathematical relationship between the voltage standard value of the tested device and the current flowing through the linear load resistance, the fitting function can be obtained through the linear regression method. For b (b ≥ 4) calibration points beyond the measurement range of DC standard voltage divider, the standard value can be “extrapolated” from the linear load resistance current and the fitting function Yang (2002). Through comparison and verification, the method is feasible, which is of great significance to promote the compilation of calibration specification for DC high voltage generator.

Concentration measurement of coloured solution using optofluidic approach

In analytical process, measurement of concentration of solution based on colorimetric sensing is normally performed using commercial devices such as colorimeter and spectrophotometer. This approach has several disadvantages such as involving a large volume of reagent and analyte during testing and measurement, unextendible and expensive. Such problem can be solved by replicating its function using a simple optofluidic device with capability of carrying out colorimetric testing with low volume of analyte and reagent. Other benefits of optofluidic devices platforms includes ability to be expanded for automated sensing and mixing for various analytical based reaction. The measurement device works based on the absorbance of absorbance of light, which is related to Beer-Lambert law principles with LED and photodiode as its main optical components. The samples were prepared for concentration ranges between 0.2 to 2.0 M for testing. As a result, it is observed that these concentrations produce a linear voltage calibration curve with correlation coefficient, R2 equal to 0.9944. By using the obtained calibration curve, the final absorbance calculation gives an acceptable linear absorbance concentration with R2 equal to 0.9751 for the tested samples. As a conclusion, these microfluidic platforms not only have a good measurement performance, but also have advantages in terms of its portability and have potential to be implemented for real time application.

A low power offset voltage calibration method for flash ADCs

In this manuscript, a lookup table (LUT) based offset voltage cancellation algorithm has been presented. The proposed algorithm helps to mitigate the ADC output non-linearity due to the effect of non-zero comparator random offset voltages. The technique has been simulated at behavioural level using MATLAB. In addition to that, circuit level verification has been done using cadence virtuoso tool and synopsis design compiler tool. A 6 bit flash ADC has been simulated using 180nm CMOS process with comparator offset voltage standard deviation of ±2LSB. Post calibration, the ADC output signal-to-noise-and-distortion ratio (SNDR) gets improved from 23.99 dB to 35.61 dB and the ADC INL gets reduced to −0.5LSB≤INL≤+1LSB from −0.51LSB≤INL≤+5.85LSB. From the synopsis design compiler tool, the power consumption of the calibration block is determined as 7.8 mW.

Design and Verification of a Calculable Composite Voltage Calibrator

Components used in the power grid need to be tested to verify they can withstand specified voltage stresses. Composite voltage test according to IEC 60060-1:2010 is a test method where impulse voltage is applied simultaneously with AC or DC voltage to the same terminal of the test object. To provide traceability to instruments used for composite voltage measurements, low-voltage calibrator based on combining existing calibrators was developed. The developed composite voltage calibrator can generate lightning and switching impulses together with DC and AC. The calibrator design is based on a series connection of a DC/AC calibrator and a calculable impulse voltage calibrator. Maximum impulse voltage peak is 330 V whereas the DC/AC voltage can be within 1000 V. Reference parameters for composite waveshape are calculated based on the applied voltage, charging voltage of the impulse calibrator, internal impedance of the impulse calibrator, and the input impedance of the device under calibration. The main uncertainty components of this composite voltage calibrator are the uncertainties related to the separate calibrators and the uncertainty of the load impedance needed for the parameter calculation.

A high voltage capacitance measurement method based on alternating coupled signal injection.

As high voltage pulse power capacitors, ceramic capacitors are widely used in high voltage pulse generators, trigger circuits, laser generators, and other fields. The capacitance of ceramic capacitors is closely related to the direct current (DC) bias voltage. However, the current capacitance measurement methods can only achieve a DC bias of 1 kV, which cannot meet the measurement requirements in high voltage environments. This paper proposes a capacitance measurement method that can accurately measure the capacitance under a DC bias of 3 kV. This method decouples the high DC bias voltage and high frequency alternating small signals and realizes low voltage calibration and high voltage isolation. The experimental results show that the proposed method measures the capacitance under a DC bias of 3 kV with a relative error within ±1%, which makes it possible to accurately quantify the capacitance hysteresis deviation in the process of increasing and decreasing back the voltage.

A Hybrid Bipolar Active Charge Balancing Technique with Adaptive Electrode Tissue Interface (ETI) Impedance Variations for Facial Paralysis Patients.

Functional electrical stimulation (FES) is a safe, effective, and general approach for treating various neurological disorders. However, in the case of FES usage for implantable applications, charge balancing is a significant challenge due to variations in the fabrication process and electrode tissue interface (ETI) impedance. In general, an active charge balancing approach is being used for this purpose, which has limitations of additional power consumption for residual voltage calibration and undesired neurological responses. To overcome these limitations, this paper presents a reconfigurable calibration circuit to address both ETI variations and charge balancing issues. This reconfigurable calibration circuit works in two modes: An impedance measurement mode (IMM) for treating ETI variations and a hybrid charge balancing mode (HCBM) for handling charge balance issues. The IMM predicts the desired stimulation currents by measuring the ETI. The HCBM is a hybrid combination of electrode shorting, offset regulation, and pulse modulation that takes the best features of each of these techniques and applies them in appropriate situations. From the results, it is proved that the proposed IMM configuration and HCBM configuration have an optimal power consumption of less than 44 W with a power ratio ranging from 1.74 to 5.5 percent when compared to conventional approaches.

A PVT-Insensitive Optimal Phase Noise Point Tracking Bias Calibration in Class-C VCO

This paper presents a Class-C voltage-controlled oscillator (VCO) with bias voltage calibration that automatically finds the low-phase noise point and achieves robust start-up regardless of PVT variation. This VCO structure also has the bias circuit that compensates for temperature changes even when calibration is not applied. Through these techniques, the problems of robust start-up and vulnerability to PVT variation, which are chronic problems of Class-C VCO, are overcome. The proposed VCO was designed in a 28 nm CMOS process. Simulation results show that this VCO has an operating range from 3.717 to 4.675 GHz, resulting in a frequency tuning range (FTR) of 22.8%. In addition, power consumption was 2.135 mW, phase noise at 1 MHz was −124.1 dBc/Hz, and the figure of merit (FoM) was −192.2 dBc/Hz. The chip area was very small at 0.196 mm2.

A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations

This article presents a 0.975-pJ/bit 56-Gb/s pulse amplitude modulation-4 (PAM-4) receiver using a time-based least significant bit (LSB) decoder in 28-nm CMOS technology. The proposed time-domain decision technique improves the robustness of comparator voltage variations by separating the data and reference paths. If the reference voltage difference is constant regardless of the common-mode voltage shift, the time-domain decoder achieves a low bit error rate (BER). To improve the timing margin of the LSB decoder from the data-dependent jitter, a sample-and-hold (S/H) structure is adopted in both the data and reference paths. The S/H circuits extend the timing margin by converting the input of the comparators to a constant voltage. The number of comparators for data decoding is reduced to two-thirds, and only eight comparators are required for a quarter-rate structure. The number of comparators in the data path, excluding the reference path, is 4, which reduces the loading capacitance. An adaptive threshold voltage calibration was implemented to generate the timing reference pulse. In addition to bathtub graphs, the BER, according to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\text {CM}}$ </tex-math></inline-formula> change of the reference voltages, is plotted to show the sensitivity to the voltage variation.