Abstract
In this manuscript, a lookup table (LUT) based offset voltage cancellation algorithm has been presented. The proposed algorithm helps to mitigate the ADC output non-linearity due to the effect of non-zero comparator random offset voltages. The technique has been simulated at behavioural level using MATLAB. In addition to that, circuit level verification has been done using cadence virtuoso tool and synopsis design compiler tool. A 6 bit flash ADC has been simulated using 180nm CMOS process with comparator offset voltage standard deviation of ±2LSB. Post calibration, the ADC output signal-to-noise-and-distortion ratio (SNDR) gets improved from 23.99 dB to 35.61 dB and the ADC INL gets reduced to −0.5LSB≤INL≤+1LSB from −0.51LSB≤INL≤+5.85LSB. From the synopsis design compiler tool, the power consumption of the calibration block is determined as 7.8 mW.
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