Voltage Buffer Research Articles

Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

This paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an undesired lossy character of the impedance plot. The added feedback path in the structure serves for minimization of the serial parasitic resistance of the current input terminal as well as the output resistance of differential voltage buffer. The electronic driving of the current and voltage internal gains of the active elements allows the adjustment of the capacitance multiplication factor as well as readjustment of the overall capacitance structure between the lossy and lossless modes of operation. The adjustment of the multiplication factor intentionally targets low ranges of gains. Despite that the multiplication factor equals or is less than 1, the range of adjustability is very wide. Simple modifications of the proposed concept leading to the differential-mode operation and enhancement of the multiplication factor are shown and explored. They were experimentally tested in more than 2 decades, from 0.03 to 5.8 nF, and controlled by single DC voltage from 0.1 to 1.0 V. The outputs of experimental measurements meet with the PSpice simulations and confirm the design validity.

A Generic Test Board for the Electrical Characterization of ULP and ULV Fully-Differential Integrated Analog Circuits

The characterization of ultra-low power (ULP) fully-differential/balanced amplifiers and active filters is challenging due to the incompatibility with the classical single-ended (SE) and 50 Ω impedance equipment. Interface circuits between the device under test (DUT) and the equipment are needed to perform the signal conversion and to work as voltage buffers. In this work, we propose a generic test circuits to be used in the characterization of ULP and ultra-low voltage (ULV) analog circuits. The test board includes balun transformers to the signal conversion, a high input impedance and low capacitance output driver and voltage regulators to provide the target DUT supply voltage. The characterization of the proposed PCB demonstrates a bandwidth of 30 MHz, output driver input impedance of 5 MΩ with 2.5 pF capacitance and low input-referred noise. The proposed circuit was applied to the electrical characterization of two fully-differential ULV and ULP analog integrated circuits.

A New Rail-to-Rail Second Generation Voltage Conveyor

In this paper, a novel low voltage low power CMOS second generation voltage conveyor (VCII) with an improved voltage range at both the X and Z terminals is presented. The proposed VCII is formed by a current buffer based on a class AB regulated common-gate stage and a modified rail-to-rail voltage buffer. Spice simulation results using LFoundry 0.15 μm low-Vth CMOS technology with a ±0.9 V supply voltage are provided to demonstrate the validity of the designed circuit. Thanks to the class AB behavior, from a bias current of 10 µA, the proposed VCII is capable of driving 0.5 mA on the X terminal, with a total power consumption of 120 µW. The allowed voltage swing on the Z terminal is at least equal to ±0.83 V, while on the X terminals it is ±0.72 V. Both DC and AC voltage and current gains are provided, and time domain simulations, where the voltage conveyor is used as a transimpedance amplifier (TIA), are also presented. A final table that summarizes the main features of the circuit, comparing them with the literature, is also given.

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC

This paper presents a 12-b, 1-GS/s ADC array, realized by time-interleaving four 250-MS/s pipelined SAR ADCs, with integrated on-chip reference voltage buffers. A reference ADC-based calibration algorithm treats static nonlinearity, gain, and offset errors in the array. Timing-skew errors between the sub-ADCs are distinguished from those of the gain mismatches by the assistance of an analog high-pass filter (HPF) for input slope information and subsequently corrected by digitally controlled delay lines (DCDLs). Directly driven off the on-chip 50- $\Omega $ termination resistors without any dedicated input buffer, the 65-nm CMOS prototype ADC array also employs a frequency-hopped, randomly-sampling scheme for the ref. ADC, eliminating the spectral effect of its interference to the main array. The core ADC consumes 31.5 mW and occupies an area of 0.27 mm2, including nine on-chip reference voltage buffers, the ref. ADC, and the HPF path. The measured peak signal to noise and distortion ratio of the array is 65.3 dB, and the measured spurious-free dynamic range is >70 dB from dc to 500 MHz at 1 GS/s with calibration. The prototype ADC chip achieves an figure of merit of 20.9 and 59.7 fJ/step (the latter is limited by the jitter of an off-chip clock source) for a low-frequency input and a Nyquist input, respectively.

Z-Copy Current Differencing Buffered Amplifier based Schmitt trigger circuit without passive components

In this paper Z-Copy Current Differencing Buffered Amplifier (ZCCDBA) based new Schmitt trigger is introduced without passive components. This ZCCDBA is a newly introduced active element. It consists of three blocks, namely, Current Differencing Unit (CDU), Voltage Buffer and Third Generation Current Conveyor (CCIII+). The CCIII purpose is to copy the Z terminal voltage and current. The proposed Schmitt trigger consists of a single ZCCDBA block without passive components. This type of configuration helps and suits for IC implementation. The proposed circuit was simulated under ±0.8 V supply voltage with the bias currents such as IB1 = IB2 = 60 µA and IB3 = 10 µA using Cadence tool and with model parameters of gpdk 180 nm technology.

A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time

This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0-40°C. The TC increases to 4.3 ppm/°C over the range from -15 °C to 55 °C. The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is 69 μW with a 1-V supply, and the leakage power consumption is 110 nW, while power gated. The ROSC achieves a fast startup time of 8 μs by employing a voltage buffer to quickly stabilize the voltage reference.

Experimental Verification of Pseudo-Differential Electronically Controllable Multifunction Filter Using Modified Current Differencing/Summing Units

This paper presents the synthesis and analysis of reconfigurable frequency filter with differential input and differential output terminals and its experimental verification. The inner structure of the filter has single-ended form, i.e., filter behaves as the so-called pseudo-differential circuit. Filtering function can be electronically reconfigured between low-pass (LP) and band-pass (BP) responses. Active elements of the filter are differential voltage buffer (DVB) as an input stage and modified current differencing unit (MCDU) together with modified current summing unit (MCSU) as the inner and also output stage. Each of the important parameters of the filter (angular pole frequency, quality factor and pass-band gain) is electronically controllable by parameters of these active elements used. Some of the parameters of the filter are controlled by two independent parameters, i.e., are dual-controlled, which enables the extended electronic controllability. The proposed topology operates in the voltage mode and both input nodes have high input impedance. Expected behavior of the filter is analyzed and verified by PSpice simulations using CMOS models of above-mentioned active elements. Moreover, features of the filter in both configurations were successfully verified also by experimental measurements using behavioral models of active elements.

Electronically Adjustable Voltage-mode First-order Allpass Filter Using Single Commercially Available IC

In this design, the use of single commercially available integrated circuit (IC), LT1228 from Linear Technology Corporation, to implement the first order allpass filter is presented. The passband voltage gain of the presented first allpass filter (APF) is unit and constant throughout the operation frequency, while the phase response is electronically tuned by changing the external DC bias current. With this property, the proposed first order filter can be used as phase shifter with microcontroller controllability. Tuning phase property is not required any matching condition. The proposed phase shifter consists of one LT1228, one capacitor and two resistors which is attractive for off the shelf implementation. Moreover, the impedance at output voltage node is exhibit low which can connect to other circuit without the requirement of external voltage buffer. The expected performances of the proposed circuit are proved by Pspice simulation using macro model parameters. Also, the quadrature sinusoidal oscillator which is designed from the connecting of the proposed filter and integrator is chosen as application example.

Identification and characterization of infectious bursal disease virus subviral particles by capillary zone electrophoresis: potential application for vaccine production and quality control

The infectious bursal disease (IBD) causes immunosuppression in chicken of all ages and high mortality in young chicken, posing serious threat to poultry industry worldwide. One promising strategy for preventing this highly contagious disease is using recombinant subunit vaccine, employing VP2 subviral particles (SVP) as epitomic antigen. Analytical techniques of viral-like particles such as SDS-PAGE, western blot, or high-performance size-exclusion chromatography have been widely applied, but mostly unsatisfactory. In the present study, a simple, fast and cost-effective capillary zone electrophoresis (CZE) method with UV-detection was developed to analyze purified IBDV-SVP (expressed by Escherichia coli system) using commercial monoclonal antibody (mAb) against VP2. To find satisfying CZE conditions, injection mode, separation voltage, and separation buffer were explored. Through the modified CZE, mAb and SVP could be well separated and shown distinct peaks in the electropherogram. Furthermore, to determine the stoichiometry, the area of the mAb peak versus SVP/mAb binding ratio was plotted and indicated that 2 or 3 receptor molecules were bound per SVP. The purity and integrity of SVP and the interactions between SVP and mAb could be analyzed by the developed simple CZE-UV method in less than half hour. This CZE-UV method proved to be a valuable and useful tool in detection, characterization, and quantification of IBDV-SVP and the mAb, offering potential applications of in-process quality control of vaccine production, surveillance of serum antibody produced against IBDV infection, or vaccine immunization.

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

ABSTRACTThis paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm2, including the TI ADC core and memory.

Lossless grounded admittance simulator using OTRA

In this paper, a generalized admittance simulator is presented. The proposed circuit uses two operational transresistance amplifiers (OTRAs), one voltage buffer and three passive components. The proposed generalized admittance simulator can realize three simulators namely lossless grounded positive inductance simulator, frequency dependent negative resistance (FDNR) simulator and capacitance simulator/multiplier without any matching constraint. The non-ideality analysis of the circuit is also given. The workability of the proposed admittance simulator is shown through the implementation of second order band pass filter using inductance simulator, second order low pass filter using FDNR and variable capacitance low pass filter using capacitance multiplier. PSPICE simulation results are included to verify theory.

Characterization of high-precision resistive voltage divider and buffer amplifier for ac voltage metrology

A high-precision voltage buffer and a 10:1 resistive voltage divider have been constructed for use in ac voltage and electrical power metrology. Long-term stability of the buffer's dc response has been demonstrated by two dc sweeps performed 20 days apart, with best-fit linearized gain varying less than 1 μV/V. The absolute ac gain has been measured using a high-precision digital multimeter for 10 Hz and 1 kHz with results consistent with dc within 5 μV/V. This value agrees with the characterization of ac–dc difference using thermal converters from different producers with a variety of resistance for various voltages from 1 V to 5 V. The ac–dc difference was further characterized better than 40 μV/V for the same voltages up to 100 kHz and better than 100 μV/V for 3 V at 1 MHz. Absolute ac gain and ac–dc difference has also been measured for the voltage divider and buffer combination from 10 V to 50 V, with similar agreement up to 1 kHz. The ac–dc difference from 10 Hz to 100 kHz of this combination shows an agreement well within 30 μV/V in this entire voltage span with a total response not exceeding 125 μV/V. This make the voltage divider and buffer combination suitable for sampling electrical powers for a wide range of voltages.

ВИСОКОЛІНІЙНІ БУФЕРИЙ МАСШТАБАТОРИ НАПРУГИ НА БІПОЛЯРНИХ ТРАНЗИСТОРАХ ІЗ НИЗЬКИМ ВХІДНИМ СТРУМОМ

Buffer devices and voltage scalers are widely used in various analog-digital systems, when it is necessary to match the signal in the form of voltage from a low-power sensor to a load, it consumes significantly more power. In this case, the voltage buffer is characterized by a voltage transfer coefficient close to unity, and must also have a high input resistance and sufficient load capacity. The voltage scaler, in contrast to voltage buffers, must additionally provide the necessary gain transfer ratio, which can be substantially more than one. The circuit design features of three variants of the construction of voltage buffer cores and voltage scaling are considered. It is proved that it is advisable to reduce the input zero bias current by using amplifying n-p-n and p-n-p transistors, as well as Shiclay transistors in the input stages. The static and dynamic characteristics of the voltage buffers and the voltage scaler must meet the system requirements of the device. The static characteristics should be attributed primarily to the error of the transfer characteristics of the scale, zero offset and linearity. The dynamics of these devices is determined by the frequency response and transient response. Static and dynamic characteristics are analyzed by computer simulation where it is shown that the scale errors of the voltage buffers and the voltage scaler do not exceed 10 µV in the range of the corresponding signal ± 5 V, and the linearity errors are 300 nV. A transient response was obtained which states that the slew rate of the output voltage will be no worse than 2000 V/µs. A comparison of the metrological characteristics of the voltage buffers and the voltage scaler in the form of a set of cores and output push-pull DC amplifiers. It is proved that the use of these amplifiers allows significantly (by 3-4 orders of magnitude) to improve the load capacity of the circuits while maintaining the level of the input zero bias current, as well as scale and linearity errors.

A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

A 24–72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB SNDR at Nyquist. High SNDR at Nyquist is achieved by 16 parallel sampling switches driven by short clock pulses. Clock-pulse edges can be shifted digitally to reduce the impact of timing mismatch. A total of 64 asynchronous 8-b successive approximation (SAR) ADCs at low supply voltage convert sampled voltages. The SAR ADCs use a differential capacitive DAC, one comparator per decision, and include a reference voltage DAC and buffer. The ADC consumes 2.0 pJ/conversion at 48 GS/s and 3.3 pJ/conversion at 72 GS/s and is implemented in 14-nm CMOS FinFET on 0.15 mm2.

A CNTFET-C first order all pass filter

A compact, low voltage, low power and high frequency voltage mode first order all-pass-filter (APF) topology is presented using carbon nanotube field effect transistor (CNTFET) based inverting voltage buffer. The proposed resistor-less APF topology uses only one capacitor and two N-type CNTFETs. Adding one CNTFET based voltage controlled resistor to the proposed first order APF results into an electronically controlled first order APF with a tuneable frequency range between 1.913 and 40.2 GHz. The proposed circuits are potential candidate for low voltage analog applications as it uses only two transistors between its supply rails. Moreover, both the proposed topologies do not have any passive component matching constraint. The realized filter circuit performance is verified with HSPICE simulations, using well known Deng’s CNTFET model at 16 nm technology node with supply voltage of ± 0.7 V. The simulation results substantiate the theoretical predictions.

A Fully on-Chip Digitally Assisted LDO Regulator With Improved Regulation and Transient Responses

This paper presents a fully on-chip mixed-mode low-dropout (LDO) regulator with improved regulation and transient responses. With the help of the digital regulation part, the supported maximum load current is significantly improved, while the chip area overhead is very small. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area due to its wider voltage swing. A proof-of-concept LDO design is fabricated in a standard 0.18- $\mu \text{m}$ CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V, and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA, which is more than 480% improved over the traditional design without digital assistance.

A High Frame Rate Wearable EIT System Using Active Electrode ASICs for Lung Respiration and Heart Rate Monitoring

A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high-performance current driver capable of up to 6 mAp-p output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35- $\mu \text{m}$ high-voltage process technology. It operates from ±9 V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 $\Omega $ /frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated.

High performance voltage output filter realizations using second generation voltage conveyor

In this article, new voltage-output filter realizations based on second generation voltage conveyor (VCII) as basic building block are presented. The results of this study show that VCII is a suitable candidate for applications requiring a voltage as filter output signal, considering that the availability of a low impedance voltage output terminal in VCII makes unnecessary the use of extra voltage buffers at the filter output, resulting in filter implementations with simpler structure, reduced power consumption, and chip area. New configurations of VCII based filters with first order low-pass (LP), second order LP, and second order bandpass (BP) transfer functions are shown. The proposed circuits enjoy a very simple structure employing only one active element and four passive components. Simulation results for a VCII transistor implementation in a 0.35 μm standard CMOS technology and a supply voltage of ±1.65 V approve the presented theory.

Temperature Effect on the Linearity Performance of a CMOS Image Sensor

This article focuses on the effect of the operating temperature of a CMOS image sensor (CIS) on the pixel performance, especially the linearity behavior. As the temperature increases, the value of the integration capacitor C FD in the floating diffusion (FD) region increases as well. Moreover, the gain of the in-pixel voltage buffer decreases. These two factors lead to a reduced value of the conversion gain. Due to an increase in the nonlinear part of the C FD, the linearity of the CIS at a higher temperature will deteriorate. A digital calibration method proposed previously is used to improve the linearity of the CIS. Measurement results conducted on a prototype image sensor, designed with a 0.18- m CIS technology, agree well with an updated analytical model of the CIS and demonstrate an efficient linearity improvement at different temperatures.

500 MHz resonant photodetector for high-quantum-efficiency, low-noise homodyne measurement.

We design and demonstrate a resonant-type differential photodetector for a low-noise quantum homodyne measurement at 500 MHz optical sideband with 17 MHz of bandwidth. By using a microwave monolithic amplifier and a discrete voltage buffer circuit, a low-noise voltage amplifier is realized and applied to our detector. 12 dB of signal-to-noise ratio of the shot noise to the electric noise is obtained with 5 mW of a continuous-wave local oscillator. We analyze the frequency response and the noise characteristics of a resonant photodetector, and the theoretical model agrees with the shot noise measurement.