Voltage Buffer Research Articles

PUSH-PULL VOLTAGE BUFFER DEVICES ON BIPOLAR TRANSISTORS

The article proposes linear push-pull buffer devices on bipolar transistors. A highly linear push-pull voltage buffer device with parametric zero shift compensation is considered. A variant of the construction of a highly linear push-pull voltage buffer device on bipolar transistors with a minimum value of the input current is proposed. The purpose of the work is to minimize the additive error of the buffer device by significantly reducing the input current. Analytical relations are given that allow estimating the additive error of the zero shift. The schematic diagram of a two-stroke buffer device with an internal zero-shift compensation generator is also considered. It is noted that the technological spread of transistor parameters will not allow to significantly reduce this error. To eliminate this shortcoming, the authors proposed a method based on the introduction of a two-stroke output power amplifier into the circuit. Such a voltage buffer consists of two parts: a buffer element and a power amplifier. It is noted that the load capacity of the buffer element is not high, so the use of a power amplifier allows you to significantly increase it, and, accordingly, to increase the current supplied by the output bus of the device to the load. It is shown that the proposed scheme of the buffer device has a low level of input current (at the level of no more than 20nA). It is also noted that the presence of a power amplifier allows maintaining the balance between the input and output potentials of the circuit and ensuring high linearity of the transfer characteristic, regardless of possible changes in the output current in the specified range. It is proposed to implement the input stage of the buffer element on compound Shikla transistors, which ensures a significant reduction of the zero shift to the level of 20 nA. The presence of a power amplifier guarantees high linearity of the transmission characteristic in the output current range of ± 5 mA.

A transient-enhanced low-dropout regulator with dynamic current boost technique voltage buffer

In this paper, a dynamic current boost technique voltage buffer is presented to enhance the large signal response of low dropout regulators (LDOs). The proposed buffer consists of AC coupling networks and active RC network. Without consuming excess power, this LDO achieves substantial improvement in load transient response. Meanwhile, an enhanced recycling-folded-cascode (RFC) amplifier is employed due to its higher gain, bandwidth and slew rate. In order to ensure the stability of full load, this design adopts simple Miller compensation with a nulling resistor without external equivalent series resistance. Moreover, this paper makes a detailed analysis of LDO in theory and the extensive experimental data verified it. The proposed LDO is successfully fabricated in SMIC 0.18μm CMOS process. The input voltage is 1.8–2.2V and the maximum load current is 200 mA. The experiment results indicate that the undershoot is 84 mV and there is no overshoot when the load current is varied from 0 to 200 mA within 100 ns under the load of 1μF load capacitor.

Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic

This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.2\times - 17.3\times $ </tex-math></inline-formula> , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.

Optimized Anti-Windup Coordinating Strategy for Torque-Maximized High-Speed Flux-Weakening Operation of Constrained Induction Motor Drives

Due to the contradiction between torque-maximized requirements and limited voltage and current constraints, voltage closed-loop flux-weakening strategy is developed to circumvent the saturation problem for maximum torque control of induction motor when the accelerating speed enters high-speed region. At the same time, since voltage inconsistency caused by the saturation is employed to construct flux-weakening controller (FC), anti-windup (AW) item in current regulator needs to be cut off to avoid the conflict. However, the replacement discards part of AWs utility and results in the distortion of command voltage, thus compromising system’s dynamic performance and making the tuning process of proportional-integral controller (PI)-based FC much trickier. To address this issue, an equivalent saturation model is presented. An optimized AW coordinating strategy is proposed, combining a novel structure, so-called virtual voltage buffer, with FC. Through an equivalent proof, it can be transformed into over-modulation block for a convenient implementation. Through its compensation in the transient period, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$d$ </tex-math></inline-formula> -axis current can be quickly and smoothly manipulated in a more concise tuning process. As a result, the overall system possesses a fast acceleration capability with maximum torque and a wide speed range, while retaining a desirable system response. Simulation and experimental results verify the effectiveness of proposed method.

Optimizing the sensitivity and resolution of hyaluronan analysis with solid-state nanopores

Hyaluronan (HA) is an essential carbohydrate in vertebrates that is a potentially robust bioindicator due to its critical roles in diverse physiological functions in health and disease. The intricate size-dependent function that exists for HA and its low abundance in most biological fluids have highlighted the need for sensitive technologies to provide accurate and quantitative assessments of polysaccharide molecular weight and concentration. We have demonstrated that solid state (SS-) nanopore technology can be exploited for this purpose, given its molecular sensitivity and analytical capacity, but there remains a need to further understand the impacts of experimental variables on the SS-nanopore signal for optimal interpretation of results. Here, we use model quasi-monodisperse HA polymers to determine the dependence of HA signal characteristics on a range of SS-nanopore measurement conditions, including applied voltage, pore diameter, and ionic buffer asymmetry. Our results identify important factors for improving the signal-to-noise ratio, resolution, and sensitivity of HA analysis with SS-nanopores.

Low power class-AB VCII with extended dynamic range

In this paper we present a novel CMOS second generation voltage conveyor (VCII) topology featuring a wide voltage swing both at the X terminal and at the Z terminal. The VCII consists of a regulated common gate configuration at the Y current input terminal and a class-AB complementary-MOS closed loop output voltage follower that ensures the voltage buffering action between the voltage input X and the voltage output Z terminals. Spice simulation results using AMS 0.35 μm with a ±0.9 V supply voltage are provided to demonstrate the validity of the proposed topology. With a total power consumption of 28 µW, the VCII achieves a voltage swing at the X terminal of ±0.8 V, whereas a ±0.72 V is achieved on the Z terminal. Simulation results for DC and AC voltage and current gains are given, as well as harmonic distortions and noise figures. A final comparison table is also presented, where the proposed VCII is compared with other solutions presented in the literature.

Concurrent-Mode CMOS Detector IC for Sub-Terahertz Imaging System.

A CMOS detector with a concurrent mode for high-quality images in the sub-terahertz region has been proposed. The detector improves output-signal coupling characteristics at the output node. A cross-coupling capacitor is added to isolate the DC bias between the drain and gate. The detector is designed to combine a 180° phase shift based on common source operation and an in-phase output signal based on the drain input. The circuit layout and phase shift occurring in the cross-coupled capacitor during phase coupling are verified using an EM simulation. The detector is fabricated using the TSMC 0.25-μm mixed-signal 1-poly 5-metal layer CMOS process, where the size, including the pad, is 1.13 mm × 0.74 mm. The detector IC comprises a folded dipole antenna, the proposed detector, a preamplifier, and a voltage buffer. Measurement results using a 200-GHz gyrotron source demonstrate that the proposed detector voltage responsivity is 14.13 MV/W with a noise-equivalent power of 34.42 pW/√Hz. The high detection performance helps resolve the 2-mm line width. The proposed detector exhibits a signal-to-noise ratio of 49 dB with regard to the THz imaging performance, which is 9 dB higher than that of the previous CMOS detector core circuits with gate-drain capacitors.

A New Realization of Electronically Tunable Multiple-Input Single-Voltage Output Second-Order LP/BP Filter Using VCII

In this paper, a new realization of electronically tunable voltage output second-order low-pass (LP) and band-pass (BP) filter is presented. The circuit has a multiple-input single-output structure, and LP and BP outputs are provided using the same structure. One electronically variable second-generation voltage conveyor (VCII), whose impedance at the Y port can be electronically varied using a control current (Icon), two capacitors, and one resistor are used. By changing the value of Icon, the impedance value at the Y port can be electronically varied; therefore, the value of ω0 can be tuned. This feature helps to reduce the number of passive components used. Interestingly, the LP and BP outputs are provided at the low-impedance Z port of the VCII, and there is no need for an extra voltage buffer for practical use. The circuit enjoys a simple realization consisting of only 24 MOS transistors. Simulation results using PSpice and 0.18 μm CMOS parameters are provided. The value of ω0 can be varied from 1.2 MHz to 1.7 MHz, while Icon varies from 0 to 50 µA, with a power consumption variation from 244 µW to 515 µW.

ВИСОКОЛІНІЙНІ ДВОТАКТНІ БУФЕРНІ ПРИСТРОЇ НАПРУГИ З ПАРАМЕТРИЧНОЮ КОМПЕНСАЦІЄЮ ЗСУВУ НУЛЯ

The method of structural and functional organization of high-performance two-stroke voltage buffer devices with parametric zero offset compensation is considered. The relevance and practical feasibility of using a zero offset compensation generator in the buffer voltage devices to obtain low linearity error are substantiated.

A New VCII Application: Sinusoidal Oscillators

The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII−). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII+), since a single VCII+ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII−. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.

Design options for high-speed OA-based fully differential buffers able to drive large loads

This paper presents several options for the design of OA-based highly linear fully differential voltage buffers able to drive heavy loads at frequencies in the tens of MHz range. The buffer is first implemented by using a telescopic OA with enlarged voltage swing; two circuits for controlling the common mode level of the output voltage are proposed. Next, two implementations based on the folded cascode transconductor with a Monticelli-type complementary source-followers second stage are presented. One of them uses complementary source followers embedded into the Monticelli gain stage, in order to lower the buffer output impedance. The proposed circuits have been implemented in a standard 0.35 μm CMOS technology as design options for a voltage buffer required by a downhole sensor used in geological surveys. There, they have to drive a standard one-OA difference amplifier which presents heavy, unbalanced loads to their positive and negative outputs, respectively 1.5 kΩ and 500Ω. Simulation results validate the designs, demonstrating that all four circuits meet the requirements: they handle sine voltages with amplitudes up to 2VPPDIFF at frequencies up to 100 MHz, with THD values better than 0.4% for signals in the tens of MHz range, achieving CMRR and PSRR values above 40 dB at 100 MHz, while consuming between 5.3 mA and 8.3 mA from a 3.3V supply.

A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopperstabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of 0.036mm, an input referred noise of 1.32Vrms (1 Hz to 200 Hz) and 3.36Vrms (0.2kHz to 10kHz), power consumption of 13. W from 1.8V supply, as well as CMRR and PSRR 83dB at 50Hz.

Four quadrant analog multiplier based memristor emulator using single active element

This paper presents a novel Four Quadrant Analog Multiplier (FQAM) circuit and its applications using a single active element Current Differencing Transconductance Amplifier (CDTA) and two NMOS. This circuit has a cascadability feature as it produces current and voltage outputs at high and low impedance ports, respectively. It offers additional features such as resistor-less realization, operability in voltage and trans-conductance mode, and configurable structure. Further, the FQAM circuit is configured to develop a memristor emulator based on the proposed mathematical analogy. The proposed memristor circuit contains active elements (one CDTA, two NMOS, and one Inverting Voltage buffer) and only one grounded capacitor. It offers tunability using the transconductance gain of the CDTA block. Also, the proposed memristor emulator circuit doesn’t contain any additional multiplier block. The emulator circuit can be operated in both the Incremental and the Decremental mode of memristance variation. The results demonstrate the non-volatile property as well as hysteresis behavior for the wide frequency range. The effects of statistical variation in passive component, threshold voltage, and aspect ratios on the proposed circuits using Monte-Carlo simulation have been estimated. Also, the impact of non-idealities and the parasitic effects of the CDTA on the proposed circuits are investigated. In last, the capacitor-less version of the memristor emulator and its hysteresis characteristics have been demonstrated. The simulation results obtained using HSPICE, are agreed well with the theoretical analysis.

Voltage-Mode Multifunction Biquad Filter and Its Application as Fully-Uncoupled Quadrature Oscillator Based on Current-Feedback Operational Amplifiers

This research introduces a new multifunction biquad filter based on voltage mode (VM) current-feedback operational amplifier (CFOA) and a fully uncoupled quadrature oscillator (QO) based on the proposed VM multifunction biquad filter. The proposed VM multifunction biquad filter has high impedance to the input voltage signal, and uses three CFOAs as active components, while using four resistors and two grounded capacitors as passive components. The VM CFOA-based multifunction biquad filter realizes band-reject, band-pass, and low-pass transfer functions at high-input impedance node simultaneously, which has the feature of easy cascading in VM operation without the need for additional voltage buffers. Additionally, the filter control factor parameter pole frequency (ωo) and quality factor (Q) of the proposed VM multifunction biquad filter can be independently set by varying different resistors. By slightly modifying the VM multifunction biquad filter topology, a VM fully-uncoupled QO is easily obtained. The difference from the previous VM CFOA-based multifunction biquad filter is that the proposed VM CFOA-based multifunction biquad filter can be independently controlled by the filter control factor parameters, ωo and Q. The proposed VM CFOA-based multifunction biquad filter can be transformed into a VM QO with fully-uncoupled adjustable of the oscillation condition and the oscillation frequency. The oscillation condition and the oscillation frequency can be fully-uncoupled and controlled by varying two sets of completely different resistors. The proposed VM fully-uncoupled QO solves the amplitude instability. The constant amplitude ratio of two quadrature sinusoidal waveforms can be realized when tuning FO. PSpice simulation and experimental results prove the performances of the proposed VM multifunction filter and VM fully-uncoupled QO. Simulation and experimental results confirm the theoretical analysis of the proposed circuits.

High Breakdown Voltage and Low Buffer Trapping in Superlattice GaN-on-Silicon Heterostructures for High Voltage Applications.

The aim of this work is to demonstrate high breakdown voltage and low buffer trapping in superlattice GaN-on-Silicon heterostructures for high voltage applications. To this aim, we compared two structures, one based on a step-graded (SG) buffer (reference structure), and another based on a superlattice (SL). In particular, we show that: (i) the use of an SL allows us to push the vertical breakdown voltage above 1500 V on a 5 µm stack, with a simultaneous decrease in vertical leakage current, as compared to the reference GaN-based epi-structure using a thicker buffer thickness. This is ascribed to the better strain relaxation, as confirmed by X-Ray Diffraction data, and to a lower clustering of dislocations, as confirmed by Defect Selective Etching and Cathodoluminescence mappings. (ii) SL-based samples have significantly lower buffer trapping, as confirmed by substrate ramp measurements. (iii) Backgating transient analysis indicated that traps are located below the two-dimensional electron gas, and are related to CN defects. (iv) The signature of these traps is significantly reduced on devices with SL. This can be explained by the lower vertical leakage (filling of acceptors via electron injection) or by the slightly lower incorporation of C in the SL buffer, due to the slower growth process. SL-based buffers therefore represent a viable solution for the fabrication of high voltage GaN transistors on silicon substrate, and for the simultaneous reduction of trapping processes.

Series and parallel resonance active damping of three‐phase buck‐type dynamic capacitor for reactive compensation and harmonic suppression

Series and parallel resonance tend to occur and cause harmonic distortion when the distribution system contains a shunt power capacitor to compensate inductive load and dynamic capacitor (D-CAP) to suppress harmonics. This study focuses on the series and parallel resonance active damping of three-phase buck-type D-CAP, so as to achieve better power quality control. Two virtual resistor damping methods for series resonance, D-CAP power capacitor voltage or D-CAP front-end buffer inductor current feedback, are introduced and compared. Then, parallel resonance is damped by generating certain harmonic currents in the phase with the selective harmonic voltage at the point of common coupling (PCC), equivalent to controlling the D-CAP as a virtual harmonic resistor. In addition, the power balance of D-CAP is interpreted to ensure no additional energy control loop is needed for the active damping. To further improve the parallel resonance damping, the self-adjusted damping gain is proposed by the closed-loop regulation of harmonics in PCC voltage. Finally, coordinated control between reactive and multiple harmonic currents is introduced for the whole combined control to avoid over-modulation. A wide variety of experimental results from a 33 kVar/220 V laboratory prototype are provided to demonstrate the validity of the combined control.

A new versatile full wave rectifier using voltage conveyors

In this paper we propose a new versatile full wave rectifier circuit using voltage conveyor (VCs) as active blocks. The proposed circuit uses two VCs, a single grounded resistor and two diodes. Compared to other previously reported rectifier circuits, it shows a simple and compact structure, employing the minimum possible number of elements. Moreover, the rectified output is available in forms of both voltage and current signals, at low impedance voltage output Z port and high impedance X port of VC, respectively. Therefore, for practical use, the proposed rectifier is cascadable without the need for extra voltage and current buffers. In addition, also the input signal can be applied in both forms of a current and of a voltage. To validate the presented theory, SPICE simulations, using 0.35 µm CMOS technology parameters and supply voltage of ±1.65 V, are reported, together with a set of measurements conducted over an equivalent discrete-level circuit, where AD844s were used to mimic VCs behavior.

CMOS voltage and current feedback opamps: a comparison between two similar topologies

ABSTRACT The voltage feedback operational amplifier (VFOA) and the current feedback operational amplifier (CFOA) are the main voltage type output opamps currently used in electronics. The VFOA is a combination of an operational transconductance amplifier (OTA) used as an input stage and an output voltage buffer (VB). In this paper, the CFOA is described as a combination of an operational transconductance conveyor (OTC) used as an input stage and with an output voltage buffer. Two similar CMOS architectures are then defined, analysed and simulated in order to provide some elements of comparison. Results, from a typical CMOS 0.35μm transistor parameters, show the role of compensation capacitances in boosting the frequency performances of the non-inverting amplifier.

A Low Power Pre-Setting Based Sub-Radix-2 Approximation for Multi-bit/cycle SAR ADCs

A pre-setting based sub-radix-2 approximation technique for multi-bit/cycle successive-approximation-register (SAR) analog to digital converters (ADCs) is proposed in this paper. The proposed approximation technique enhances the conversion speed and relieves the power hungry reference voltage buffer. The sub-radix-2 approximation only adjusts the weights of original binary DAC array without introducing additional unit capacitors and leading to reduced silicon area and power consumption. An adder based backend encoding circuit is proposed, with negligible power and silicon area overhead. Furthermore, the non-ideal DNL/INL, which are caused by incomplete DAC settling, are characterized and analysed in this paper. The peak DNL/INL values are symmetrically located at 1/4 and 3/4 of full scale. With the presence of sub-radix-2 approximation, the peak INL/DNL could be significantly reduced. The simulation results show the better performance of sub-radix-2 approximation than binary approximation. Designed in CMOS 40nm technology, it could keep a higher (>9.5-bit) effective number of bits (ENOB) with short settling time of DAC buffer, and boost the sampling rate equivalently.

Статичні і динамічні характеристики високолінійних двотактних буферів напруги на біполярних транзисторах

Push-pull voltage buffer devices (BD) are widely used in various measuring analog - digital systems, in which the electrical signal (voltage) sensor must be connected to the converter devices using circuits that have a high input impedance (at least tens and hundreds of mega), as well as low output impedance (no more than ~ 1.0 Ohm) to ensure a constant value of the transmission coefficient in the specified ranges of amplitudes and frequencies of the input signal. The article considered the proposed circuits of high-linear push-pull voltage buffers on bipolar transistors, including composite Shiklai transistors with a high slew rate of the output signal. An approach to the construction of a BD is proposed, based on the use of current reflectors, which operate in a push-pull balanced mode, which will provide high performance with a sudden change in the input voltage. We also investigated such small-signal static characteristics as the input and output resistance of the BD, the zero offset of the input current, as well as the linearity error in the range of input and output voltages. It is shown that in comparison with known devices, the proposed solutions have better performance. The dynamic characteristics of the proposed circuits, such as frequency response, nonlinear distortion coefficient in the frequency range of the output signal, as well as transient characteristics, are analyzed. It has been proved that the obtained indicators exceed those for circuits based on operational amplifiers. The quantitative values of the static and dynamic characteristics of the proposed BD are obtained, which can serve as recommendations for the selection of existing options depending on the parameters of the input signal sensors and the output load resistance.