Voltage Buffer Research Articles

High-bandwidth FPGA based randomized voltage states for controlling optoelectronic devices in QKD systems

We have developed an inexpensive system for generating random voltage states (RVS) on a FPGA platform. This system can be used for controlling optoelectronic devices in a quantum-key-distribution (QKD) system. We use an all-digital operation at the FPGA layer to generate two uncorrelated Boolean bit strings. These bit strings are converted to RVS using a multiplexer and a voltage buffer in order to drive commercially available optoelectronic devices. A National Instruments (N.I) real-time IO (RIO) platform was used for FPGA implementation. The FPGA layer was coupled to the desktop layer for real-time monitoring and logging of the Boolean bit strings. We characterize the performance of the multiplexer and the buffer and describe how their engineering performance trades-off with the fidelity of RVS generation.

Unveiling a Multiplexed Sensing System for Advanced Biosensing Applications with Thread-Based Electrochemical Sensors

The miniaturization and portability of electrochemical sensing devices play a crucial role in a wide range of applications, including medical diagnostics, environmental monitoring, and point-of-care testing. Integrating a pseudo-reference electrode addresses challenges linked to traditional counterparts, ensuring enhanced portability and miniaturization without performance compromise. Our research delves into the significance of this innovation, emphasizing its impact on signal stability, reproducibility, and overall sensor reliability. The tailored pseudo-reference for compact electrochemical devices contributes to a highly efficient, cost-effective, and user-friendly design, ideal for point-of-care diagnostics and field applications. This work showcases the design, implementation, and performance evaluation of a portable electrochemical sensing system with a pseudo-reference-integrated readout circuit, improving reliability under diverse operating conditions. In the proposed research, we present the design and implementation of a dual-channel configurable multiplexed sensing platform utilizing thread-based electrochemical sensors for continuous potentiometric and amperometric measurements.For the pH sensor, the fabrication process initiates with the cleaning (using isopropyl alcohol) and subsequent plasma treatment of polysorb sutures. The cleaned sutures undergo multiple coatings (4 cycles) with conductive carbon ink, followed by baking at 60°C for 30 to 35 minutes to ensure uniform conductivity. Carbon-coated (CC) sutures undergo electrochemical pre-treatment in a solution of 0.50 M H2SO4 and 0.10 M KCl, followed by electrodeposition with polyaniline (PANI) using potentiometric deposition at 0.80 V in the presence of 0.50 M aniline in a solution containing 1.0 M H2SO4. An insulating polymer layer of 5% polyurethane (PU) is applied at the sensor's center, leaving ends exposed for electrical connections and subsequent hydrogel coating for real sample analysis. The O2 sensor fabrication involves cleaning silver-coated threads, coating with dielectric ink for a sensing region, and UV curing. Two identical threads serve as the cathode and anode, with an intentionally longer anode region as a common reference for the pH sensor. This comprehensive approach contributes to developing a versatile and efficient sensing system for multiplexed measurements, showcasing potential applications in diverse environments.The measurement system includes a signal conditioning circuit (denoted as analog front-end or AFE in Fig. 1) comprising a trans-impedance amplifier (TIA) and an op-amp in the unity-gain configuration: the former is used to convert the current into voltage which originates from the oxygen sensor whereas the latter is used to read out the open-circuit voltage (OCV) for the pH sensor. The outputs of the TIA and the voltage buffer are sequentially selected using a 2:1 multiplexer with a control bit (SEL) before digitizing using an analog-to-digital converter (ADC). There is also a digital-to-analog converter (DAC) generating a bias voltage (VBIAS) of 0.55V for the oxygen sensor as the oxygen electrode requires a certain potential to maximize the dynamic range of the current measurement. The microcontroller handles digital signal processing, which can be connected to a computer for data storage and visualization. The operation of the sensor multiplexing system is validated in standard buffer solutions and gel mediums with different pH and O2 concentrations. The proposed setup demonstrated a sensitivity of ~65 mV/pH for the pH sensor (n=3), and 0.6621 nA/mgL-1 for the O2 sensor (n=3) in a gel medium with common ions and electrolytes. The sensor results were validated against commercial oxygen and pH probes for the same solutions. The developed sensing platform and sensor can precisely monitor and track changes in pH and O2 levels within less than 2 minutes for repeated cycles. This architecture has the potential for extending the low-power multiplexed sensing to multiple biomarkers with an increased number of sensors for ingestible devices, wearable sensing, and cellular agriculture applications. KEYWORDS: Multiplexed sensing, pseudo-reference, pH and oxygen monitoring, miniaturized circuit, thread-based electrochemical sensor Figure 1

A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management

This paper presents a flipped voltage follower (FVF) based output-capacitor-less low-dropout regulator (OCL-LDO) with fast transient response, high power supply rejection (PSR), and low quiescent current for noise-sensitive circuits in internet-of-things (IoTs). An adaptive super source follower (ASSF) is proposed to effectively reduce the output impedance of the voltage buffer under heavy-loading conditions while keeping a low quiescent current under light-loading conditions. The active capacitor compensation management (ACCM) is proposed to solve the charge-sharing problem caused by the floating capacitors in the dynamic capacitor compensation circuit. The proposed OCL-LDO has been designed and fabricated in 22-nm CMOS technology. It can stabilize with load current ranging from 0 to 12 mA while consuming only 4.8-μA quiescent current. when the load current steps from 0.1 to 10 mA within 3.8 ns, the measured voltage undershoot is 55 mV and the recovery time is about 60 ns.

A 0.064 mm2 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach

In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 μm × 65 μm compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 μVrms. Power consumption is also tested, with a measured value of 3.77 μW per channel, corresponding to an overall consumption of about 60 μW. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results.

A 16 Bit 125 MS/s Pipelined Analog-to-Digital Converter with a Digital Foreground Calibration Based on Capacitor Reuse

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μm CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply.

Synthesis of electronically tunable multifunction biquad filter using voltage differencing differential input buffered amplifiers

AbstractBiquad filters are commonly used in analog circuits for various purposes in signal processing and communication applications. We synthesize an analog active biquad filter with five types of voltage‐mode filtering functions. The filter is synthesized using a parallel passive resistor‐inductor‐capacitor (RLC) network and unity‐gain voltage differencing amplifier. A voltage differencing differential input buffered amplifier (VD‐DIBA) is the main active component, and the biquad filter has a three‐input single‐output (TISO) topology. By replacing the passive inductor and resistor with VD‐DIBA‐based inductance and resistance simulators with a subtractor, the TISO voltage‐mode versatile filter is obtained from two VD‐DIBAs, one resistor, and two capacitors connected to the ground. The proposed filter can provide five types of voltage‐mode filtering functions: inverting bandpass and lowpass responses as well as noninverting band‐stop, high‐pass, and all‐pass responses. The all‐pass filter requires no additional active components. The three input voltage nodes have high impedance, and a low‐impedance output voltage node facilitates cascade connections without using additional voltage buffers. In addition, the natural frequency and quality factor can be electronically tuned. The quality factor is controlled without disturbing the passband gain and natural frequency. The proposed filter is simulated and verified experimentally in the Personal Simulation Program with Integrated Circuit Emphasis (PSPICE) and through laboratory tests employing VD‐DIBAs implemented using commercially available components.

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals From Sensors

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals From Sensors

Design and Verification of a New Universal Active Filter Based on the Current Feedback Operational Amplifier and Commercial AD844 Integrated Circuit.

This paper presents a triple-input and four-output type voltage-mode universal active filter based on three current-feedback operational amplifiers (CFOAs). The filter employs three CFOAs, two grounded capacitors, and six resistors. The filter structure has three high-input and three low-output impedances that simultaneously provide band-reject, high-pass, low-pass, and band-pass filtering functions with single-input and four-output type and also implements an all-pass filtering function by connecting three input signals to one input without the use of voltage inverters or switches. The same circuit configuration enables two unique filtering functions: low-pass notch and high-pass notch. Three CFOAs with three high-input and low-output impedance terminals enable cascading without voltage buffers. The circuit is implemented using three commercial off-the-shelf AD844 integrated circuits, two grounded capacitors, and six resistors and further implemented as a CFOA-based chip using three CFOAs, two grounded capacitors, and six resistors. The CFOA-based chip has lower power consumption and higher integration than the AD844-based filter. The circuit was simulated using OrCAD PSpice to verify the AD844-based filter and Synopsys HSpice for post-layout simulation of the CFOA-based chip. The theoretical analysis is validated and confirmed by measurements on an AD844-based filter and a CFOA-based chip.

First-Order Universal Active Filter Configuration Using Single VCII+

A new universal active filter configuration is presented in this paper which is capable of realizing all three first-order filter responses namely all pass (AP), low pass (LP) and high pass (HP) using a single second generation voltage conveyor (VCII+), a virtually grounded capacitor and two resistors. The proposed circuit offers tunability of the cut-off frequency, gain (for HP filter) and simultaneous availability of two filter outputs, one at a low impedance node (HP/AP), the other output, namely the LPF will require a voltage buffer to avoid loading. The nonideal analysis of filter responses based on the nonideal model of VCII+ is carried out by considering all the parasitic immittances and nonideal gains and found that they have no significant effect on the performance of the proposed filter structure. Sensitivity analysis with respect to active and passive components has also been carried out. The functionality of the presented circuit has been validated through simulations and experimental results, where the VCII+ was implemented using the macro model of the commercially available CFOA IC AD844. Additionally, the proposed circuit has been tested using a CMOS VCII+ implemented with 0.18[Formula: see text][Formula: see text]m TSMC technology parameters. The tests include advanced evaluations based on Monte Carlo simulations.

Very‐low frequency capacitively coupled AC amplifier with a current feedback operational amplifier

SummaryIn this paper, we propose the idea of using transimpedance amplifiers, in lieu of operational amplifiers (OAs) or transconductance amplifiers (OTAs) to design capacitively coupled AC amplifiers. The idea is demonstrated with a current feedback operational amplifier (CFOA) as an active element, which is actually an architecture consisting of voltage buffers and current copiers (mirrors). This last characteristic is further exploited to make the corner frequency of the AC amplifier tunable by means of bootstrapping low‐valued resistors with the output buffer. It is particularly suited to achieve very‐low corner frequencies as needed in applications such as bio‐ or seismic signals. The idea is demonstrated with simulations and experimental results with a discrete implementation.

A VCO-Based ADC With Direct Connection to a Microphone MEMS, 80-dB Peak SNDR and 438-μW Power Consumption

This article presents a microphone readout chip incorporating a voltage controlled oscillator (VCO)-based ADC that can be directly connected to a capacitive micro electro mechanical systems (MEMSs) sensor without requiring a voltage buffer. The ADC uses an open-loop pseudo-differential architecture with two ring oscillators followed by a coarse–fine frequency-to-digital converter. The proposed coarse–fine architecture optimizes power consumption, thanks to a new algorithm. The MEMS is connected to the ring oscillators with a source follower circuit that can be programed to interchange signal to noise ratio (SNR) by the power consumption in small steps. This feature enables always-on operation in voice recognition applications. The microphone is compatible with standard PDM audio interfaces. Total ADC power consumption ranges between 245 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$438 \mu \text{W}$ </tex-math></inline-formula> for peak signal-to-noise and distortion ratios (SNDRs) between 74 and 80.3 dB-A, including the ADC and MEMS coupling circuitry. The dynamic range (DR) achieves 108 dB at full performance with a total harmonic distortion (THD) of 1.5% at the acoustic overload point (AOP) of 128 dBSPL. The ADC occupies an area of 0.14 mm2 implemented in 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS.

ВИСОКОЛІНІЙНІ БУФЕРИ НАПРУГИ ДЛЯ ВИСОКОПРОДУКТИВНИХ АЦП І ЦАП

The article analyzes the proposed methods of structural and functional organization of highly linear voltage buffers built according to two-stroke symmetrical structures. In the first method, it is assumed to increase the resistance of the current outputs. Thanks to this, it is possible to stabilize the collector-emitter junction voltage of the transistors of the output stages. In the second method, it is proposed to reduce the influence of the base current of the transistors of the output stages, which will reduce the linearity error. In the third method, it is proposed to increase the linearity without reducing the speed level, by stabilizing the collector-emitter voltages of the output stages. It is shown that the use of voltage stabilization of the collector-emitter transitions makes it possible to improve the circuit characteristics by 1÷2 orders of magnitude. Analytical dependencies describing the linearity errors of the cores of voltage buffers, which are built according to a two-stroke symmetrical structure, are derived. It is shown that the proposed approaches allow to reduce the errors of linearity and zero shift by an order of magnitude or more. To determine the components that affect the appearance of the error, an equivalent scheme for replacing the output of the voltage buffer core is considered. It was determined that the proposed methods of building voltage buffers have a common drawback, namely, low load capacity, which is determined by the output resistances of the circuits. An approach that allows increasing the load capacity of voltage buffers is considered. It is shown that it makes it possible to reduce the output resistance by 2÷3 orders of magnitude. In order to increase the load capacity and maintain the specified linearity of the voltage buffer scheme, it is proposed to supplement it with a two-stroke two-channel current amplifier. The use of the proposed methods and approaches for the construction of voltage buffers allows obtaining such devices that have the necessary characteristics and can be used as part of high-performance ADCs and DACs.

Arbitrarily Tunable Phase Shift in Low-Frequency Multiphase Oscillator

A special electronically tunable multiphase oscillator with arbitrarily and continuously adjustable phase shifts is introduced. Our design assumes to set the phase around the asymptotical limit of 180°. These features cannot be easily achieved by a standard way, i.e., any simple single-phase oscillator supplemented by a first-order adjustable all-pass section (shifter). The proposed design uses an electronically linearly tunable quadrature oscillator with frequency range from 0.98 up to 12.54 kHz. It also offers multiples of 45° as the initial setting of the phase shift tuning region. The example of operation shows the adjustment of the phase shift at a specific frequency (10 kHz) within the range of ±45° and around -180°, -135° and -90°. This variability is not available in standard cases without the use of several all-pass sections. The current value of the phase shift of the presented oscillator is electronically controlled and does not influence the oscillation frequency and condition of oscillation. Output levels of produced signals are not influenced by this tuning process and are in the range of several hundred mV. Two applications of the oscillator are proposed. The first one focuses on low-bitrate modulation systems (phase shift keying) while in the second one our circuit represents a source of phase-adjustable signals in acoustic experiments. Discrete passive elements and active devices (special multipliers having current output terminals, unity-gain differential voltage buffers) fabricated in 0.35 μm I3T25 ON Semiconductor 3.3 V CMOS process are used in experimental verification.

A Fully-Differential CMOS Instrumentation Amplifier for Bioimpedance-Based IoT Medical Devices

The implementation of a fully-differential (FD) instrumentation amplifier (IA), based on indirect current feedback (ICF) and aimed to electrical impedance measurements in an Internet of Things (IoT) biomedical scenario, is presented. The IA consists of two FD transconductors, to process the input signal and feed back the output signal, a summing stage, used to add both contributions and generate the correcting current feedback signal, and a common-mode feedback network, which controls the DC level at the output nodes of the circuit. The transconductors are formed by a voltage-to-current conversion resistor and two voltage buffers, which are based on a super source follower cell in order to improve the overall response of the circuit. As a result, a compact single-stage structure, suitable for achieving a high bandwidth and a low power consumption, is obtained. The FD ICF IA has been designed and fabricated in 180 nm CMOS technology to operate with a 1.8-V supply and provide a nominal gain of 4 V/V. Experimental results show a voltage gain of 3.78 ± 0.06 V/V, a BW of 5.83 MHz, a CMRR at DC around 70 dB, a DC current consumption of 266.4 μA and a silicon area occupation of 0.0304 mm2.

0.6-V 1.65-μW Second-Order Gm-C Bandpass Filter for Multi-Frequency Bioimpedance Analysis Based on a Bootstrapped Bulk-Driven Voltage Buffer

A bootstrapping technique used to increase the intrinsic voltage gain of a bulk-driven MOS transistor is described in this paper. The proposed circuit incorporates a capacitor and a cutoff transistor to be connected to the gate terminal of a bulk-driven MOS device, thus achieving a quasi-floating-gate structure. As a result, the contribution of the gate transconductance is cancelled out and the voltage gain of the device is correspondingly increased. The technique allows for implementing a voltage follower with a voltage gain much closer to unity as compared to the conventional bulk-driven case. This voltage buffer, along with a pseudo-resistor, is used to design a linearized transconductor. The proposed transconductance cell includes an economic continuous tuning mechanism that permits programming the effective transconductance in a range sufficiently wide to counteract the typical variations that process parameters suffer during fabrication. The transconductor has been used to implement a second-order Gm-C bandpass filter with a relatively high selectivity factor, suited for multi-frequency bioimpedance analysis in a very low-voltage environment. All the circuits have been designed in 180 nm CMOS technology to operate with a 0.6-V single-supply voltage. Simulated results show that the proposed technique allows for increasing the linearity and reducing the input-referred noise of the bootstrapped bulk-driven MOS transistor, which results in an improvement of the overall performance of the transconductor. The center frequency of the bandpass filter designed can be programmed in the frequency range from 6.5 kHz to 37.5 kHz with a power consumption ranging between 1.34 μW and 2.19 μW. The circuit presents an in-band integrated noise of 190.5 μVrms and is able to process signals of 110 mVpp with a THD below −40 dB, thus leading to a dynamic range of 47.4 dB.

Four Unity/Variable Gain First-Order Cascaded Voltage-Mode All-Pass Filters and Their Fully Uncoupled Quadrature Sinusoidal Oscillator Applications.

This paper presents four new designs for a first-order voltage-mode (VM) all-pass filter (APF) circuit based on two single-output positive differential voltage current conveyors (DVCCs). The first two proposed VMAPFs with unity-gain, high-input (HI) impedance and low-output (LO) impedance use two DVCCs, a grounded capacitor, and a grounded resistor. The last two proposed first-order VMAPFs with HI impedance and variable-gain control are two resistors added to each of the first two VMAPFs. The last two proposed first-order VMAPFs with variable-gain control use two DVCCs, one grounded capacitor, and three grounded resistors and provide HI impedances, so that VMAPFs can be directly cascaded to obtain high-order filters without additional voltage buffers. The four implementation circuits based only on grounded passive components are particularly applicable for integrated circuits (ICs). To confirm the cascading characteristics, an application example of a fully-uncoupled quadrature sinusoidal oscillator (FQSO) is also proposed. PSpice simulation results have confirmed the feasibility of the proposed structures. VMAPF and FQSO circuits are also constructed from commercial AD8130 and AD844 ICs, and their experimentally measured time and frequency responses are compared to theoretical values. The supply voltages for both the AD8130 and AD844 ICs were ±5 V. The measured power dissipation of the proposed first-order VMAPF and second-order FQSO circuits is 0.6 W. The measured input 1-dB compression point for the four VMAPFs is about 19 dB. The measured total harmonic distortion of the four VMAPFs is less than 0.67% when the input voltage reaches 2.5 Vpp. The calculated figures of merit for the four VMAPFs are 628.2 × 103, 603.06 × 103, 516.53 × 103, and 496.42 × 103, respectively.

Design of 1.2 V CMOS flipped voltage follower based output-capacitor-less low dropout regulator with improved voltage buffer for impedance attenuation

Design of 1.2 V CMOS flipped voltage follower based output-capacitor-less low dropout regulator with improved voltage buffer for impedance attenuation

A 0.17 pJ/bit 28 Gb/s/pin Single-Ended PAM-4 Transmitter for On-Chip Short-Reach Unterminated Channels

This paper presents the design of a single-ended four-level pulse-amplitude modulation (PAM-4) transmitter for an on-chip short-reach unterminated channel. To achieve multi-output generation, a local voltage buffer consisting of a diode-connected device and a leaker transistor is introduced. By charge-sharing between a local reservoir capacitor and an unterminated channel, the proposed transmitter generates mid-level output voltages without using the DC current, thereby realizing multi-level signaling without significantly increasing the static current. A prototype chip was fabricated by 28 nm CMOS process, and the transmitter exhibits an energy efficiency of 0.17 pJ/bit at 28 Gb/s/pin, which is state-of-the-art energy efficiency as a multi-level transmitter having a data rate beyond 20 Gb/s.

High Gain, Low Noise and Power Transimpedance Amplifier Based on Second Generation Voltage Conveyor in 65 nm CMOS Technology.

A transimpedance amplifier (TIA) based on a voltage conveyor structure designed for high gain, low noise, low distortion, and low power consumption is presented in this work. Following a second-generation voltage conveyor topology, the current and voltage blocks are a regulated cascode amplifier and a down converter buffer, respectively. The proposed voltage buffer is designed for low distortion and low power consumption, whereas the regulated cascode is designed for low noise and high gain. The resulting TIA was fabricated in 65 nm CMOS technology for logic and mixed-mode designs, using low-threshold voltage transistors and a supply voltage of ±1.2 V. It exhibited a 52 dBΩ transimpedance gain and a 1.1 GHz bandwidth, consuming 55.3 mW using a ±1.2 V supply. Our preamplifier stage, based on a regulated cascode, was designed considering detector capacitance, bonding wire, and packaging capacitance. The voltage buffer was designed for low-power consumption and low distortion. The measured input-referred noise of the TIA was 22 pA/√Hz. The obtained total harmonic distortion of the TIA was close to 5%. In addition, the group delay is constant for the considered bandwidth. Comparisons against published results in terms of area (A), power consumption (P), bandwidth (BW), transimpedance gain (G), and noise (N) are were performed. Both figures of merit FoMs—the ratio √ (G × BW) and P × A—and FoM/N values demostrated the advantages of the proposed approach.

An Auto-Zero-Stabilized Voltage Buffer With a Quiet Chopping Scheme and Constant Sub-pA Input Current

This article describes an auto-zero stabilized voltage buffer that achieves low offset and low noise with sub-pA input current. A high gain stabilization loop is used to periodically cancel the buffer’s offset. The loop itself is periodically disconnected from the buffer and auto-zeroed, during which its bandwidth is reduced to reduce the associated noise folding. However, this also reduces its offset correction range, and so to avoid overloading, its initial offset is digitally trimmed. To break up the correlation between the residual low-frequency (LF) noise of the auto-zero and stabilization phases, the loop is periodically chopped, which significantly reduces the buffer’s LF noise. Finally, the duty-cycle of the two phases is optimized to bring the buffer’s LF noise density close to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {2}$ </tex-math></inline-formula> times its white noise density (14 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sqrt {\text {Hz}}$ </tex-math></inline-formula> ), which is the fundamental limit of an AZ amplifier. The buffer also achieves a constant and low input current (0.8 pA), as well as a state-of-the-art offset (0.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> ).