Solder Voids Research Articles

Impact of Solder Voids on IGBT Thermal Behavior: A Multi-Methodological Approach

This study investigates the thermal behavior of Insulated Gate Bipolar Transistors (IGBTs) with a focus on the influence of solder voids within the device. Utilizing a combination of Finite Element Method (FEM) simulations, X-ray imaging, and SEM-EDX analysis, we accurately modeled the internal structure of IGBTs to assess the impact of void characteristics on thermal resistance. The findings reveal that the presence and characteristics of solder voids—particularly their size, number, and distribution—significantly affect the thermal resistance of IGBT devices. Experimental measurements validate the FEM model’s accuracy, confirming that voids disrupt the heat flow path, which can lead to increased thermal resistance and potential device failure. Five regression models, including Gaussian process regression (GPR) and neural networks, were employed to predict the thermal resistance based on void characteristics, with the GPR models demonstrating superior performance. The optimal GPR RQ model consistently provided accurate predictions with an RMSE of 0.0050 and R2 of 0.9728. Using the void percentage as the only input parameter for the regression models significantly impacted the prediction accuracy, showing the importance of the void extraction method. This study shows the necessity of minimizing solder voids and offers a robust methodological framework for a better prediction of the reliability of IGBTs.

Effect of solder void on mechanical and thermal properties of flip-chip light-emitting diode: Statistical analysis based on finite element modeling

With the increasing demand for highly efficient lighting in the automotive industry, flip-chip light-emitting diodes (LEDs) have become widely used for both interior and exterior lighting. Solder, serving as a crucial interconnecting material, often develops voids during the reflow process, compromising the integrity and reliability of the connections. Thus, understanding the impact of these voids on the mechanical and thermal properties of the product is vital for improving reliability accuracy. This work employs computational methods alongside experimental approaches to address the challenges of replicating solder voids and controlling the solder void fraction. A comprehensive study investigates the effects of solder voids on shearing properties and thermal conductance. Random voids were introduced into the solder pads of an LED assembly within a finite element model (FEM), leading to predictions of maximum shear stress and LED junction temperature. The findings correlate well with the experimental data, validating the FEM's applicability. Furthermore, a statistical analysis was conducted to explore the relationship between solder void fraction, position, and size, aiming to provide objective guidelines for analyzing soldered assembly tomography in reliability assessments.

The effect of pre-existing voids on solder reliability at different thermomechanical stress Levels: Experimental assessment

After lead-free technology, pre-existing voids in Power-MOSFET device solder connections have been a hot topic. Previous studies have examined the mechanical performance of solders with manufacturing-induced voids typically by generating excessive voids intentionally using simulation analysis without/insufficient experimental results. Electronic assembly standards such as IEC 61191-2, J-STD-001G, and IPC-A-610G do not cover voiding due to conflicting opinions and insufficient experimental evidence. In this context, comprehensive experimental results are needed to verify simulation results and assist in setting the standard. Silicon-based Power MOSFET packages with different locations, sizes, and patterns of pre-existing voids with nearly the same percentage of voids (30–33%) have been chosen to address this critical issue. The Power MOSFET test samples underwent power cycling-based accelerated degradation testing at various stress levels and monitored the location and rate of solder degradation at specific time intervals. It is found that small dispersive voids in solder life are useful, but clusters can accelerate damage propagation. Contrary, large dispersive voids at the edges initiate solder damage, reducing solder life. Our experimental investigation findings indicate that pre-existing voids' positions, sizes, and patterns should be considered when establishing solder void inspection standards. This would improve power devices' reliability for end-user power supply and control.

Modeling the Effects of Thermal Pad Voiding on Quad Flatpack No-lead (QFN) Components

Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.

Simulation of crack propagation in solder layer of IGBT device under temperature shock by viscoplastic phase field method

Insulated Gate Bipolar Transistor (IGBT) is a key device in power system. During its service, due to the mismatch of thermal expansion coefficients, cracking of the solder layer may result in reliability concerns. However, the thickness of the solder layer is generally only tens of microns, so it is challenging to study the dynamic crack propagation in the solder layer. In this study, the viscoplastic phase field method is combined with the Anand viscoplastic model commonly used in solder alloys to simulate the dynamic fracture of the IGBT solder layer during temperature shock test (TST). The simulation results are compared with the experimental results and the results are very close. In this paper, the effect of solder voids and solder inclination on crack propagation is studied by using phase field method. It is found that the presence of voids promotes crack propagation, and the crack propagation rate is faster on the thin side when the solder is tilted.

Vacuum Reflow Process Optimization for Solder Void Size Reduction in Semiconductor Packaging Assembly

The undesirable impacts of solder void defects on the reliability of die packages have prompted stringent requirements on solder void size control in the semiconductor packaging industry. Vacuum reflow process using Pb95Sn5 solder was studied, where critical process parameters within temperature and pressure profiles were varied for enhanced solder void size reduction, in comparison to conventional reflow process. Higher reflow temperature profile, faster pressure pump-down rate, and longer vacuum dwell time above threshold levels are critical conditions required for consistently achieving minimum solder void sizes well below the industry criteria. Application of threshold conditions using large volume reflow oven with industrial settings has achieved the single and the total solder void size over die size well below the standard 2.5% and 5% requirements, respectively, with majority of the samples attained the single and the total solder void size over die size below 1% and 2%, respectively. Solder bond line thickness exhibited a significant influence on the solder void size reduction and thus needs to be administered appropriately during die packaging assembly to achieve the maximum solder void size reduction.

Solder void size reduction in semiconductor package by vacuum reflow and pressure cure processes

PurposeSemiconductor packaging industry has in recent years tightened the tolerance criteria for acceptable solder void size in the semiconductor packages due to the high usage in automotive applications. Semiconductor packaging component makers have strengthened the quality of the solder joint and its electrical conductivity by controlling the maximum solder void size reduction from 10-15% to 5% or below over die size. This paper aims to reduce the solder void size to minimum level that current industry could not achieve and introduce a new soldering processes by combining vacuum reflow and pressure cure to effectively reduce solder void.Design/methodology/approachThis study is using the empirical data collection to prove the feasible in achieve the goal. It is an engineering approach. This research study is even considering sufficient data (>22 units) in each evaluation to represent the actual performance.FindingsSuccessfully eliminate all the hollow solder void that current industry claimed as solder void. EDX analysis showed that the compressed solder voids remained in the solder are filled with solid carbon-based substances which could be originated from the trapped flux residues. It is empirical data proven in feasibility stage.Research limitations/implicationsThe study is able to produce solder void-less. This method is suitable for high volume manufacturing process also. This may lead a new pave way for industry to resolve solder void problem. The current pressure cure machine could not apply more than 200°C temperature which limits medium and high temperature solder paste or alloy testing. Therefore, only low temperature solder alloy Pb37Sn63 was able to be evaluated.Originality/valueThis study is original and has not been published elsewhere to produce high efficiency product in semiconductor packaging performance in electrical path and heat dissipation. It also improves package reliability due to solder joint used as interconnect in semiconductor packaging.

Relative importance of solder and wire bond defects on the maximum junction temperature of IGBT devices

The wear-out of interconnection packaging materials of Insulated-Gate Bipolar Transistors (IGBTs) during power cycling in Pulse Width Modulation (PWM) mode can induce a local temperature increase on the die surface, resulting in thermal runaway, and ultimately short-circuit failure. In this study, the effect of PWM power cycling on solder and wire bond aging states as well as on the surface temperature distribution and thermal resistance was measured by infrared camera and compared with microstructural analysis. Horizontal cracks in the solder close to the solder-die interface induced the highest thermal resistance increase. Comparatively, the impact of solder voids on the thermal resistance was lower, but this caused significant bow of the die due to solder redistribution. This may contribute to an increased stress intensity factor at the die edges and thus horizontal crack formation. Lift-off bonds can also locally increase the die surface temperature due to Joule heating at imperfect electrical contacts. Analytical expressions validated by measurements and electro-thermal Finite Element Modeling were developed to estimate the relative importance of the different defects for a wider range of module designs and operating conditions.

Bias Temperature Instability and Junction Temperature Measurement Using Electrical Parameters in SiC Power MOSFETs

Junction temperature sensing is an integral part of both online and offline condition monitoring where direct access to the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction-to-case thermal resistance, which is a key indicator of packaging failure mechanisms like solder voiding and cracks. The use of temperature sensitive electrical parameters (TSEPs) has widely been proposed as a means of junction temperature sensing; however, there are certain challenges regarding their use in SiC MOSFETs. Bias temperature instability (BTI) from charge trapping in the gate dielectric causes threshold voltage drift, which in SiC affects some of the key TSEPs including on -state resistance, body diode forward voltage as well as the current commutation rate. This article reviews the impact of BTI on the accurate junction temperature measurement using TSEPs in SiC MOSFETs.

Base solder voids identification of IGBT modules using case temperature

Solder voids has an important impact on healthy operation of insulated-gate bipolar transistor (IGBT) modules, but voids damage is difficult to be estimated accurately by conventional methods due to the lack of calculation in mutual thermal effect between chips. So this paper proposes a base solder voids identification method by using case temperature, takes into account both self-thermal diffusion and coupling inside module, and adopts case temperature distribution on bottom of baseplate to assess voids damage indirectly. Firstly, finite element method (FEM) of IGBT module with base solder voids was established to study junction and case temperature response with different voids distribution, the practicability of base solder voids identification based on case temperature is verified. Then the influence mechanism of voids on case temperature was discussed theoretically, voids identification is extended to dynamic load conditions, temperature-to-thermal resistance conversion and dynamic thermal resistance reference calibration with different power loss ratio were realized by improved thermal network, recursive least square (RLS) algorithm was designed for dynamic identification of real-time identifiable thermal resistance, the difference between RLS results and thermal resistance reference was compared to confirm the severity of base solder voids, two or more groups of comparison results with different power conditions are used to complete the voids analysis. Finally, validity of proposed method is demonstrated by simulation. Compared with conventional method, it shows better ability in dynamic identification.

Automated defect detection of insulated gate bipolar transistor based on computed laminography imaging

Void inspection is crucial for insulated gate bipolar transistors. X-ray computed laminography (CL) is an imaging method for plate-like objects such as insulated gate bipolar transistors. Hence, voids in CL images should be identified automatically and accurately. This paper proposes a fully automatic method of void inspection in the welding layer between a direct-bonded ceramic and a baseplate. No-reference image sharpness assessment is used to find the welding-layer slice, which confirms that the error is within one layer as compared to well-trained operators. Next, semantic segmentation network DeepLabv3+ is modified to segment the solder region and voids. Compared with conventional segmentation algorithms based on the edge and threshold, the proposed method for segmenting the solder region is free of tuning parameters. Its global accuracy and the class average accuracy can be greater than 96%. In addition, for the segmentation of voids, the proposed algorithm is found to be faster than the region-growing algorithm with an improvement in speed of about hundreds of times. Our algorithm potentially enables objective assessment of the heat exchange efficiency of IGBTs in industry.

Fully convolutional networks for void segmentation in X-ray images of solder joints

Whether in sensory or illumination applications, optoelectronic components are an essential part of our everyday life. To actually include them in smartphones, cars or other products, they need to be soldered onto the surface of a printed circuit board via surface-mounted technology. Hereby, the solder joint is formed by remelting the solder paste that was printed onto the board before the optical component was mounted. During this process, the evaporating flux causes porosities (voids) filled with gas that is caught in the solidifying alloy. Voids influence the thermal and electric properties of a solder joint and hence reduce its reliability. Because the solder joint is embedded between the device and the board, non-destructive X-ray inspection is used to visualize voids. However, the superposition of various structures in a noisy image acquisition process renders the semantic segmentation of solder joints and voids in X-ray images difficult. To the best of our knowledge, there is no method for automatic void segmentation in flat solder joints based on X-ray images aside from this work. We develop a fully convolutional network for pixel-wise classification of X-ray images and show, how our contributions enable automatic void inspection of soldered structures without protracted X-ray tomography of flat samples, so-called laminography.

The two-phase flow simulation and experimental research on the formation of solder voids in power module

This paper focuses on the formation of solder voids in the large-area die-attach (DA) in power modules. The finite volume simulation method was used to study the motion behaviors of bubbles in molten liquid solder. The experiments were carried out by changing the reflow atmosphere. The voids distribution in DA was characterized by X-Ray detection. Results suggest that vacuuming the molten solder can significantly reduce the void rate of the DA. The bubbles only need a short stroke to escape from the molten solder under the influence of negative pressure. From a mechanical point of view, the collapse of the solder during the phase change is one of the main forces for driving the bubble to coalesce and move horizontally, but it may also lead to an increase in void ratio due to the reduction of BLT (Bond Layer Thickness). Solders with larger wall contact angles tend to have a larger void rate due to the increase in viscous resistance. The nitrogen atmosphere has a positive effect on reducing the void rate by reducing the wall contact angle of liquid solder. Besides, the wall adhesion plays a leading role in the movement of the bubble, and the influence of the buoyancy is small.

The Influence of Solder Void on IGBT Temperature

The void in solder layer is the main factor that causes bad heat dissipation of IGBT (Insulated Gate Bipolar Transistor) module. Based on the seven-layer structure of IGBT, this article established a three-dimensional finite element model of IGBT module packaging structure and carried out its thermal analysis, then had a study on the effect of welding layer void on the temperature of IGBT chip. The overall distribution of IGBT module with or without solder hole is compared, meanwhile the article analyzed the effects of void type, size, shape, number and distribution on the temperature distribution of IGBT chips. The results show that the void in the solder layer of the chip has a great influence on the temperature of the chip. The influence of penetrating voids on chip temperature is greater than that of non-penetrating voids, the bigger the single hole is, the higher the temperature of IGBT chip. Voids of the same shape have greater influence on chip temperature at edge and corner positions than those inside the welding layer. The more concentrated the distribution of multiple holes, the higher the chip’s temperature. Therefore, in order to improve the reliability of IGBT, it is necessary to avoid voids in the chip welding layer during the packaging process.

Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules

Abstract System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity of packages increases (multi die, large number of passives, through mold via interposer for external memory, convergence of different technologies). This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. The prototype test package with three flip chip die was processed using different bump structures with bump height variation and differences in coplanarity. The underfill dispense pattern was optimized to eliminate underfill creep to the top of passive components that could lead to interfacial delamination. The interposer solder had no reliability risk due to the added mechanical strength of the underfill. Laser ablation formed through mold vias (TMV) on top of the interposers to connect to a package on package memory device. Partially defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination concerns were mitigated by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).

Experimental approach to thermal conductivity of macro solder joints with voids

Purpose The purpose of the paper is to experimentally evaluate the impact of voids on thermal conductivity of a macro solder joint formed between a copper cylinder and a copper plate by using reflow soldering. Design/methodology/approach A model of a surface mount device (SMD) was developed in the shape of a cylinder. A copper plate works as a printed circuit board (PCB). The resistor was connected to a power supply and the plate was cooled by a heat sink and a powerful fan. A macro solder joint was formed between a copper cylinder and a copper plate using reflow soldering and a lead-free solder paste SAC305. The solder paste was printed on a plate through stencils of various apertures. It was expected that various apertures of stencils will moderate the various void contents in solder joints. K-type thermocouples mounted inside cylinders and at the bottom of a plate underneath the cylinders measured the temperature gradient on both sides of the solder joint. After finishing the temperature measurements, the cylinders were thinned by milling to thickness of about 2 mm and then X-ray images were taken to evaluate the void contents. Finally the tablets were cross-sectioned to enable scanning electron microscopy (SEM) observations. Findings There was no clear dependence between thermal conductivity of solder joints and void contents. The authors state that other factors such as intermetallic layers, microcracks, crystal grain morfologyof the interface between the solder and the substrate influence on thermal conductivity. To support this observation, further investigations using metallographic methods are required. Originality/value Results allow us to assume that the use of SAC305 alloy for soldering of components with high thermal loads is risky. The common method for thermal balance calculation is based on the sum of serial thermal resistances of mechanical compounds. For these calculations, solder joints are represented with bulk SAC305 thermal conductivity parameters. Thermal conductivity of solder joints for high density of thermal energy is much lower than expected. Solder joints’ structure is not fully comparable with bulk SAC305 alloy. In experiments, the average value of the solder joint conductivity was found to be 8.1 W/m·K, which is about 14 per cent of the nominal value of SAC305 thermal conductivity.

Characterization of SAC – x NiO nano-reinforced lead-free solder joint in an ultra-fine package assembly

PurposeThis study aims to investigate the NiO nano-reinforced solder joint characteristics of ultra-fine electronic package.Design/methodology/approachLead-free Sn-Ag-Cu (SAC) solder paste was mixed with various percentages of NiO nanoparticles to prepare the new form of nano-reinforced solder paste. The solder paste was applied to assemble the ultra-fine capacitor using the reflow soldering process. A focussed ion beam, high resolution transmission electron microscopy system equipped with energy dispersive X-ray spectroscopy (EDS) was used in this study. In addition, X-ray inspection system, field emission scanning electron microscopy coupled with EDS, X-ray photoelectron spectroscopy (XPS) and nanoindenter were used to analyse the solder void, microstructure, hardness and fillet height of the solder joint.FindingsThe experimental results revealed that the highest fillet height was obtained with the content of 0.01 Wt.% of nano-reinforced NiO, which fulfilled the reliability requirements of the international IPC standard. However, the presence of the NiO in the lead-free solder paste only slightly influenced the changes of the intermetallic layer with the increment of weighted percentage. Moreover, the simulation method was applied to observe the distribution of NiO nanoparticles in the solder joint.Originality/valueThe findings are expected to provide a profound understanding of nano-reinforced solder joint’s characteristics of the ultra-fine package.

Solderable Polymer Thick-film Conductors for Low Temperature Substrates

Abstract For decades, polymer thick-film (PTF) systems have provided a low cost, non-fired option for screen-printing simple electronic circuits. The ability to apply these types of pastes on temperature sensitive substrates such as PET, polycarbonate, polyimide, and other polymers has facilitated a variety of applications, for instance membrane touch-switch keypads, buss bars for touch screens, various types of sensors, and flexible circuitry. Polymer thick-film is also one of the primary technology solutions utilized in the rapidly emerging Printed Electronic market, where flexible, durable materials are paramount to the success of these technologies. One of the largest emerging markets for polymer thick-film is wearable electronics, where engineers are designing “smart fabrics” with active circuitry for medical monitoring, performance enhancement in sports, and personal comfort. Polymer thick-film pastes include silver pastes for conductors, carbon pastes for resistive applications, silver-silver chloride fillers for glucose sensors, and dielectric pastes. The major challenge with PTF silver conductors is that they are not conducive to soldering. This hinders the ability to attach components, leads, dies, wires, or other features to the prints. As copper is solderable, one possible solution would be a copper polymer thick-film metallization; however they start oxidizing at the typical paste curing temperatures, 110 – 130°C, rendering them unsuitable for the vast majority of conductive applications. In order to meet these challenges, Heraeus has developed a new line of solderable polymer thick-film conductors based on a high-performance silver-coated copper conductive filler. These metallizations are solderable, resistant to solder leaching, and result in sheet resistivities approaching that of pure silver polymer conductors. The prints do not degrade in performance when cured at temperatures as high as 200°C. The new product line was formulated to accept different types of solders, especially traditional SAC-305, which provides a complete matched solution for designers. The new metallization opens up new applications given its ability to print polymer circuitry on a variety of substrates including aluminum, steel, FR4, Kapton, Mylar, and glass. The technology also allows for the fabrication of more complex circuitry on these types of substrates, giving circuit designers a powerful new tool in their toolbox in applications such as LED lighting, sensors, and heaters. Finally, these materials may provide a lower-cost option for solderable flexible polymer end terminations for components used in vibration sensitive applications, for instance the automotive industry. In our paper, we will present the properties of the new pastes and printed conductors. Performance testing includes surface resistivity, solderability, solder leach resistance, voiding, and adhesion on two substrates: FR4 and Kapton. Furthermore, we show that the solderable PTF conductor will provide a potential cost- savings over the current technology used on FR4 boards, stamped copper films. By replacing the stamped copper with our solderable PTF conductor, manufacturers will have the advantage of replacing a subtractive process for etching their patterns with an additive, environmentally friendly process, not only saving processing time but eliminating a large, dangerous copper waste stream. Finally, we will summarize the applications that the new technology enables.

Structural Assessment of Lead Free Solder Joint of Miniaturized Electronics Assembly

This paper presents a study on structural assessment of ultra-fine package assembly with nano-composites lead free solder joint after reflow soldering process. In this work, various nanoparticles (i.e. TiO2, Fe2O3 and NiO) with different weightage percentage (i.e., 0.01, 0.05 and 0.15 wt.%) were successfully incorporated into SAC305 solder paste using the mechanical solder paste mixer to synthesize novel lead-free composite solders. Effects of the nanoparticles addition on the quality of joining and fillet height between various weightage (wt.%) for the ultra-fine package assembly in the reflow soldering process have been investigated after the reflow soldering process by using the scanning electron microscope (SEM) system equipped with an energy dispersive X-ray spectroscopy (EDS) and XTV 160 x-ray inspection system. The experimental results show the increment of TiO2, Fe2O3 and NiO nanoparticles addition to 0.15wt.%, 0.05wt.% and 0.01wt.%, respectively, produce highest fillet height of each composition of nanoparticles solder paste. Among all these new composition of nanoparticles solder paste, NiO nanoparticles reinforced solder paste with 0.01wt.% yielded highest fillet height The miniaturized solder joints do not cause any problem in terms of solder voids. The findings show the capability of the reflow soldering process in assembling miniaturized electronics assembly and expected to provide a reference in electronic package industry.

A computational investigation of the effect of three-dimensional void morphology on the thermal resistance of solder thermal interface materials

Process-induced solder voids have three-dimensional shapes and show spatially random distribution with polydisperse geometric dimensions. There exists no analytical formulation of thermal resistances which incorporates void shapes, distribution and polydispersity variables. This paper uses finite element methods to investigate the effect of realistic void morphology on the thermal resistance of solder thermal interface materials (STIMs). The study has developed two computationally efficient methods for generating voids that show the features of real voids. Cylindrical and spherical void morphologies have been studied. The study is the first attempt, in literature, of characterizing the holistic effects of such realistic three-dimensional void morphologies on the thermal resistance of STIM layers. We have shown a qualitative agreement between our results and simplistic analytical predictions. However, the influence of void shapes, distribution and polydispersity have been shown to contribute to increased thermal resistances. The findings should provide significant insight to electrical/electronics engineers, micro-electronics chips manufacturers and academic research groups working on thermodynamics design of chip scale package (CSP) devices. It is also a framework for investigating objectively, the consequence of voids on the thermo-mechanical response of solder joints.