VLSI Layout Design Research Articles

An Efficient Data Structure Layout Design for Spatial Data Organization in Geographic Information System

This paper presents a design for map reading based on Corner Stitching for handling the spatial data. Corner Stitching is a technique for representing the rectangular two dimensional objects. It is a technique initially used in VLSI layout editing systems. GIS systems store spatial data using rectangular objects. The concept of corner stitching has been used to reduce the space complexity as well as time complexity pertaining to VLSI Layout Design. These rectangular objects are stitched together at their corners called corner stitches. The data organization & various operations seen, has similarity with certain operations to be performed on spatial data. The data organization is designed in order to support the parallel operations. A query processor for this new data organization has also been developed. The aim of this paper is to explore the extent to which the use of Corner Stitching can be helpful in GIS based system.

An Optimization Algorithm Based On Grid-Graphs For Minimizing Interconnect Delay In VLSI Layout Design

In this paper, we describe a routing optimization algorithm based on grid-graphs for application in a deep-submicron VLSI layout design. The proposed algorithm, named S-RABILA (for Simultaneous Routing and Buffer Insertion with Look-Ahead), constructs a maze routing path, simultaneously with buffer insertion and wire sizing, taking into account wire and buffer obstacles, such that the interconnect delay from source to sink is minimized. In current nanometer VLSI layout design, the interconnect delay has become the dominant factor affecting system performance. Research has shown that routing algorithms, which include simultaneous buffer insertion and wire-sizing, have been proven to be very effective in solving the timing optimization problem in VLSI interconnect design. A key contribution of this work is a novel look-ahead scheme applied to speed up the runtime of the algorithm, and aids in finding the exact solution. Hence, the algorithm is accurate, fast, scalable with problem size, and can handle large routing graphs. Experimental results show the effectiveness of the look-ahead scheme and indicate that S-RABILA provides significant performance improvements over similar existing VLSI routing algorithms.

Trade-Offs between Stretch Factor and Load-Balancing Ratio in Routing on Growth-Restricted Graphs

An unweighted graph has density rho and growth rate k if the number of nodes in every ball with radius r is bounded by rhork. The communication graphs of wireless networks and peer-to-peer networks often have constant bounded density and small growth rate. In this paper, we study the trade-off between two quality measures for routing in growth-restricted graphs. The two measures we consider are the stretch factor, which measures the lengths of the routing paths, and the load-balancing ratio, which measures the evenness of the traffic distribution. We show that if the routing algorithm is required to use paths with stretch factor c, then its load-balancing ratio is bounded by O(rho1/k(n/c)1-1/k), and the bound is tight in the worst case. We show the application and extension of the trade-off to the wireless network routing and VLSI layout design. We also present a load-balanced routing algorithm with the stretch factor constraint in an online setting, in which the routing requests come one by one.

MAkE: Multiobjective algorithm for k-way equipartitioning of a point set

The classical problem of partitioning a given set of points, has applications in several areas such as facility location, scattered network, and in hierarchical design of VLSI circuits. While equipartitioning is traditionally associated with the single objective of minimum cutcost, the above application areas appear to demand more. In this paper, we introduce the problem of multiobjective k-way equipartitioning of a point set. Brief discussions on the above applications are followed by their generic formulation as a multiobjective k-way equipartitioning problem of a given point set. The non-commensurate multiobjective criteria addressed include (i) minimizing overall areas of the partitions, (ii) maximizing area of the individual partitions, (iii) minimizing the total compactness of the partitions, and (iv) minimizing the total geometric diversity of the obtained partitions. Since this optimization problem is computationally expensive in time and space, a technique based on genetic algorithm is proposed in order to obtain high quality results. Crossover and mutation operators specific to the k-way equipartitioning problem, have been designed and a new greedy operator named compaction is proposed to accelerate convergence. To illustrate the utility of the proposed formulation and the algorithm, a problem in VLSI layout design is considered. Results on synthetic data sets as well as those extracted from layouts of benchmark circuits demonstrate the effectiveness of the proposed multiobjective approach.

A Surjective Mapping from Permutations to Room-to-Room Floorplans

A floorplan is a subdivision of a rectangle into rectangular faces with horizontal and vertical line segments. Heuristic search algorithms are used to find desired floorplans in applications, including sheet-cutting, scheduling, and VLSI layout design. Representation of floorplan is critical in floorplan algorithms, because it determines the solution space searched by floorplan algorithms. In this paper, we show a surjective mapping from permutations to room-to-room floorplans. This mapping gives us a simple representation of room-to-room floorplans.

A Graph Based Soft Module Handling in Floorplan

In the VLSI layout design, a floorplan is often obtained to define rough arrangement of modules in the early design stage. In the stage, the aspect ratio of each soft module is also determined. The aspect ratio can be changed in the designated range keeping its area of each module. In this paper, in order to determine the aspect ratio, we propose a graph-based one dimensional compaction method which determines the aspect ratio quickly under the constraint that topology of a floorplan must not be changed. The proposed method is divided into two steps: (1) Selection of a minimal set of soft modules to adjust the aspect ratio. (2) Decision on the aspect ratio. (1) is formulated as the minimal cut problem in graph theory. We solve the problem by transforming it to the shortest path problem. (2) is divided into two operations. One is to determine the increment limit in height or width of each soft module and the other is to determine the aspect ratio of each soft module by Newton-Raphson method. The experimental comparisons show effectiveness of the proposed method.

Simulated annealing search through general structure floor plans using sequence‐pair

AbstractIn VLSI layout design, a “floor plan” is often derived prior to solving the placement problem. The floor plan is obtained by dividing the square representing the chip into several rectangular rooms, to which modules are assigned, and then the locations of the module and interconnects are approximately determined. In floor plan study, the use of slice structures is common. Recently, however, a method of converting the sequence‐pair, as a representation of the rectangular packing, to the floor plan has been proposed. Hence, it is now possible to list all floor plans with general configurations including the nonslice structure. However, in such a method there is the deficiency that an “empty room” without an assigned module may be generated. In the present paper, an adjacent solution is proposed for effective search of only the general configuration floor plan without empty rooms by using the simulated annealing method. An ingenious technique for effectively deriving this adjacent solution is described. The diameter of this solution space is proven to be of polynomial size. Also, the proposed solution space is experimentally compared with the solution space of slice structures. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 88(6): 28–38, 2005; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/ecjc.10003

Equidistance routing in high-speed VLSI layout design

In VLSI layout design, certain nets in a given net set are required to propagate their signals within a tolerable skew of delays. Though the delay of the signal on a wire is determined by a complex environment, it is hard to satisfy this requirement unless all the concerned nets are routed within a certain skew of length. In this paper, we propose L-equidistance routing, which routes the concerned nets with a prescribed length L. After a basic technique of L-equidistance routing of a single 1-sink net, an algorithm is presented for the channel routing of plural multi-sink nets. The key idea is in the symmetric-slant grid interconnect scheme by which the problem is reduced to a grid routing problem. In L-equidistance routing of a channel, the total length of a n-sink net is not unique for n⩾3. An algorithm based on dynamic programming to solve this minimization problem is presented. Then, L-equidistance switch-box routing is discussed based on the L-equidistance channel routing. Algorithms are explained on the Euclidean space. But it is shown that a straightforward transformation of the routes to those on the Manhattan grid is possible keeping the property of equidistance. The proposing channel routing algorithm was implemented and applied to random data to demonstrate their ability.

An evolutionary constraint satisfaction solution for over the cell channel routing

A novel evolutionary assignment-ordering approach for combinatorial optimization using constraint satisfaction problem (CSP) modeling is presented. In the assignment of values to variables, the order of assignment is determined by an ordering function combined with problem-specific features. No a priori information is available on the assignment-ordering function and it is completely determined by evolutionary optimization to produce the best assignment results. Indeed, experimental evaluations show that the proposed method outperforms very well-known approaches for the solution of NP-hard combinatorial optimization problems from VLSI layout design, namely, channel routing and multi-layer over the cell channel routing.

On finding an empty staircase polygon of largest area (width) in a planar point-set

This paper presents an algorithm for identifying a maximal empty-staircase-polygon (MESP) of largest area, among a set of n points on a rectangular floor. A staircase polygon is an isothetic polygon bounded by two monotonically rising (falling) staircases. A monotonically rising staircase is a sequence of alternatingly horizontal and vertical line segments from the bottom-left corner of the floor to its top-right corner such that for every pair of points α=( x α , y α ) and β=( x β , y β ) on the staircase, x α ⩽ x β implies y α ⩽ y β . A monotonically falling staircase can similarly be defined from the bottom-right corner of the floor to its top-left corner. An empty staircase polygon is a MESP if it is not contained in another larger empty staircase polygon. The problem of recognizing the largest MESP is formulated using permutation graph, and a simple O( n 3) time algorithm is proposed. Next, based on certain novel geometric properties of the problem, an improved algorithm is developed that identifies the largest MESP in O( n 2) time and space. The algorithm can be easily tailored for identifying the widest MESP in a similar environment. The general problem of locating the largest area/width MESP among a set of isothetic polygonal obstacles, can be solved easily. These geometric optimization problems have several applications to VLSI layout design, robot motion planning, to name a few.

Monotone bipartitioning problem in a planar point set with applications to VLSI

A new problem called monotone bipartitioning of a planar point set is identified which is found to be useful in VLSI layout design. Let F denote a rectangular floor containing a set A of n points. The portion of a straight line formed by two points from the set A is called a line segment. A monotone increasing path ( MP ) in F is a connected and ordered sequence of line segments from the bottom-left corner of F to its top-right corner, such that the slope of each line segment is nonnegative, and each pair of consecutive line segments share a common point of A . An MP is said to be maximal ( MMP ) if no other point in A can be included in it preserving monotonicity. Let A L denote the subset of A corresponding to the end points of the line segments in an MMP , L . The path L partitions the set of points A \ A L into two subsets lying on its two sides. The objective of monotone bipartitioning is to find an MMP L , such that the difference in the number of points in these two subsets is minimum. This problem can be formulated as finding a path between two designated vertices of an edge-weighted digraph (the weight of an edge being an integer lying in the range [- n, n ]), for which the absolute value of the algebraic sum of weights is minimized. An O ( n × e ) time algorithm is proposed for this problem, where e denotes the number of edges of the graph determined from the geometry of the point set. The monotone bipartitioning problem has various applications to image processing, facility location, and plant layout problems. A related problem arises while partitioning a VLSI floorplan. Given a floorplan with n rectangular blocks, the goal is to find a monotone staircase channel from one corner of the floor to its diagonally opposite corner such that the difference in the numbers of blocks lying on its two sides is minimum. The problem is referred to as the staircase bipartitioning problem. The proposed algorithm for a point set can be directly used to solve this problem in O ( n 2 ) time. However, an improved O ( n ) time algorithm is reported for this special case. This leads to an O ( n log n ) time algorithm for hierarchical decomposition of a floorplan with a sequence of staircase channels. Staircase bipartitioning has many applications to channel and global routing.

VLSI layout design of analog hardware neuron model based on CMOS negative resistance

VLSI layout design of analog hardware neuron model based on CMOS negative resistance

An Edge‐endpoint‐based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.Our work proposes an edge‐endpoints‐based method for performing Manhattan geometry checking and a general scalable architecture for DRC. We then demonstrate our approach by applying this architecture to a set of design rules for MOSIS SCN4N_SUB process. We have implemented several design rule checks within a single Xilinx XC4013 FPGA and demonstrated overall speedups in excess of 25X over software methods. We have used a Compaq Pamette board to do the hardware prototyping and have achieved a clock rate of 33 MHz.

On the crossing distribution problem

VLSI layout design is typically decomposed into four steps: placement, global routing, routing region definition, and detailed routing. The crossing distribution problem occurs prior to detailed routing [Groenveld 1989; Mared-Sadowska and Sarrafzadeh 1995; Wang and Shung 1992]. A crossing is defined as the intersection of two nets. The problem of net crossing distribution is important in layout design, such as design of dense chips, multichip modules (MCM), critical net routing, and analog circuits [Groenveld 1989; Sarrafzadah 1995; Wang and Shung 1992]. It is observed that nets crossing each other are more difficult to route than those that do not cross. The layout of crossing nets has to be realized in more than two layers and requires a larger number of vias In this paper we study the crossing distribution problem of two-terminal nets between two regions. We present an optimal O(n2) time algorithm for two-sided nets, where n is the number of nets. Our results are superior to previous ones [Markek-Sadowska and Sarrafzadeh 1995; Wang and Shung 1992]. We give an optimal O(n 2 ) time algorithm for the crossing distribution problem with one-sided nets. We solve optimally the complete version of the crossing distribution problem for two-terminal nets in two regions that has not been studied before.

Developing the VLSI laboratory for the computer architecture course

The paper presents an alternative way of having a hardware laboratory for the computer architecture course that is taught in every computer science curricula. For institutions like CSUSB, with no College of Engineering, having an actual hardware laboratory will be cost prohibitive. An alternative way is to have a set of computer-aided design (CAD) tools where students can design hardware and then test their designs using simulation. This has been done at CSUSB. By using MAGIC (a VLSI layout design tool) and IRSIM (a functional logic simulator) the VLSI Design Laboratory was developed for the computer architecture course in the Department of Computer Science. The VLSI Design Laboratory was implemented using the machines obtained from a matching equipment grant from IBM which consists of five IBM RS/6000s and 15 XStations. The paper presents how the laboratory complements the lecture and how the students learn the hierarchical design methodology of VLSI circuits. Future directions of the VLSI Design Laboratory are also presented.

VLSI module placement based on rectangle-packing by the sequence-pair

The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement.

On the efficiency of a routing model: KKD

Routing is a crucial problem in the VLSI layout design automation process. In this paper we study the channel routing problem for multiterminal nets in the knock-knee diagonal model (KKD), where the grid consits of right and left tracks displayed at +45° and −45°. We give three results in KKD by a unified and simple algorithm. Let d be the density of a given channel routing problem and w the width of channel. We have: (a) if all nets are two-terminal nets, then d + 1 is an upper bound to w (solved optimally); (b) if all nets are two- or three-terminal nets, then [ 3d 2 ] + 1 is an upper bound to w; (c) 2d is always an upper bound to w in KKD.

An optimal channel-routing algorithm in the times square model

Channel routing is an important, time-consuming, and difficult problem in VLSI layout design, In this paper, we consider the two-terminal channel routing problem in the new routing model, called times square model (TSM); see, Lodj, Info. Proc. Lett., vol. 35, p. 41, 1990.; where the grid is composed of horizontal tracks, right tracks (with slope +60/spl deg/) and left tracks (with slope -60/spl deg/). We show a new lower bound [2d/3]-1 to the width of channel and present an optimal algorithm for two-terminal channel routing problems, which obtains [2d/3]+2 as an upper bound to the channel width where d is the channel density. The algorithm not only utilizes the horizontal tracks, but also the zig-zag connections, thus achieving the routing optimality.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An efficient DM switchbox router

Routing is an important problem in the computer-aided VLSI layout design process. We consider the switchbox routing problem in a new routing model, diagonal model (DM)[11], whose grid consists of right and left diagonal tracks displayed at +45° and -45° on two layers. We present an efficient DM switchbox router. It attempts to reach the optimality to maximum extent locally and globally. Experimental results demonstrate that it completes successfully the routing for many known benchmark examples.

A PARALLEL SIMULATED ANNEALING-BASED CHANNEL ROUTER

The routing problem of VLSI layout design is very compute intensive. Consequently, the routing task often turns out to be a bottleneck in the layout design of large circuits. Parallel processing of the routing problem holds promise for mitigating this situation. In this context, we present a parallel channel routing algorithm that is targetted to run on loosely coupled computers like hypercubes. The proposed parallel algorithm employs the simulated annealing technique for obtaining near- optimum solutions. Initially, the number of tracks in the channel is made equal to the number of nets, and partitions of the channel are appropriately assigned to the nodes of the hypercube. Each node carries out concurrent perturbations to obtain new channel states that satisfy the constraints for a given net list. The algorithm minimizes the number of tracks iteratively by using the simulated annealing technique. For efficient execution, we attempt to reduce the communication overheads by restricting the broadcast updates to cases of interprocessor net transfers only. Performance evaluation studies of the algorithm show promising results.