Simulated annealing search through general structure floor plans using sequence‐pair

Abstract

AbstractIn VLSI layout design, a “floor plan” is often derived prior to solving the placement problem. The floor plan is obtained by dividing the square representing the chip into several rectangular rooms, to which modules are assigned, and then the locations of the module and interconnects are approximately determined. In floor plan study, the use of slice structures is common. Recently, however, a method of converting the sequence‐pair, as a representation of the rectangular packing, to the floor plan has been proposed. Hence, it is now possible to list all floor plans with general configurations including the nonslice structure. However, in such a method there is the deficiency that an “empty room” without an assigned module may be generated. In the present paper, an adjacent solution is proposed for effective search of only the general configuration floor plan without empty rooms by using the simulated annealing method. An ingenious technique for effectively deriving this adjacent solution is described. The diameter of this solution space is proven to be of polynomial size. Also, the proposed solution space is experimentally compared with the solution space of slice structures. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 88(6): 28–38, 2005; Published online in Wiley InterScience (www.interscience. wiley.com). DOI 10.1002/ecjc.10003