Simulated annealing search through general structure floorplans using sequence-pair

Abstract

VLSI floorplan is a rectangular dissection of a chip rectangle where dissection lines correspond to wiring channels and each module is assigned to a separate room. Floorplans are often represented by the slicing structures. Recently, sequence-pair (seq-pair) has been proposed as the description of the rectangle packing and later on a method to map a seq-pair to a floorplan has been proposed. However, such floorplans made of seq-pairs often include rooms with no module assigned, and so it is difficult to make good solution space by seq-pair. In this paper, we propose a novel solution space of floorplans for simulated annealing (SA) which consists of the all general floorplans with exact n rooms, where n is the number of given modules, using seq-pair. By using ingenious data structure, a feasible adjacent floorplan can be obtained in O(n/sup 2/) time and the reachability from any floorplan to any other in the proposed solution space is proved. The experimental results show the effectiveness of the solution space.