VLSI Implementation Research Articles

VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier

In this brief, we present the design and evaluation of a high speed and energy-efficient truncated multiplier for unsigned multiplication, such that the average absolute error due to truncation and rounding is kept minimal. The proposed algorithm eliminates a few least significant Partial Product (PP) bits and adds correction bias at appropriate PP bit positions to minimize the total error. From the literatures reviewed, it is clear that there is scope for reducing delay in multiplication using sutras of ancient vedic mathematics. This work uses a simple “crosswise and vertical sutra” of Vedic mathematics to generate PP bits. The proposed methodology groups the input into [Formula: see text]/2 bits, eliminates least subgroup multiplication ([Formula: see text]) and deletes few least significant bits in other subgroup multiplications to reduce area and power dissipation. In addition, correction biase are added at appropriate bit positions to reduce the overall absolute error due to the elimination of few PP bits and rounding of final product. Experimental evaluation of the proposed truncated design is carried out through structural level VHDL modeling and simulations using Synopsys design compiler. Performance analysis revealed Chip-Area Ratio (CAR%) to be 33.81% and Power-Delay Product (PDP) of 14.84[Formula: see text]pJ of proposed truncated design for an [Formula: see text] multiplication.

VLSI Implementation of Constructive Neural Network for Skin Cancer Detection

A novel method for Constructive Neural Networks has been proposed to detect the skin cancer stages by using C-MANTEC algorithm. This algorithm produces compact architecture. To analyze the skin cancer at the early stage adaptive region growing is proposed. For the execution of skin malignancy identification there are four phases included. First stage is pre-processing by anisotropic diffusion filter, second stage is segmentation, and third stage is GLCM feature extraction by using MATLAB. Utilizing constructive neural network algorithm in fourth stage is used to detect various stages of the cancer which is further implemented using Xilinx.

VLSI Implementation of High Performance Montgomery Modular Multiplication

VLSI Implementation of High Performance Montgomery Modular Multiplication

A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition

Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size FFT hardware accelerator, which fully supports the IEEE-754 single-precision floating-point standard and the FFT calculation with a wide size range from 2 to 220 points. First, a parallel Cooley–Tukey FFT algorithm based on matrix transposition (MT) is proposed, which can efficiently divide a large size FFT into several small size FFTs that can be executed in parallel. Second, guided by this algorithm, the FFT hardware accelerator is designed, and several FFT performance optimization techniques such as hybrid twiddle factor generation, multibank data memory, block MT, and token-based task scheduling are proposed. Third, its VLSI implementation is detailed, showing that it can work at 1 GHz with the area of 2.4 mm2 and the power consumption of 91.3 mW at 25 °C, 0.9 V. Finally, several experiments are carried out to evaluate the proposal’s performance in terms of FFT execution time, resource utilization, and power consumption. Comparative experiments show that our FFT hardware accelerator achieves at most $18.89\times $ speedups in comparison to two software-only solutions and two hardware-dedicated solutions.

Hardware Implementation of the Compressed Beamforming Weights Calculation for the Practical Wireless MIMO-OFDM Communication System

The compressed beamforming weights (CBWs) feedback is used in the IEEE 802.11n/ac WLAN, an example of the practical beamforming multiple input multiple output-orthogonal frequency division multiplexing system, to reduce the amount of feedback information so that the beamformee can respond rapidly to the beamformer. The CBW associated with each sub-carrier includes the quantized angles obtained from QR-decomposition (QRD) of the right singular vectors of each corresponding channel matrix. Efficient matrix QRD and singular value decomposition (SVD) together are therefore desirable for computing the CBWs associated with all sub-carriers. Considering the exemplary antenna configuration of 4 beamformer and 2 beamformee antennas, we propose to apply the same matrix triangulation to compute the SVD of a 2-by-4 matrix and to compute the QRD of a 4-by-2 matrix. We can achieve gate count reduction by exploiting only one matrix triangulation module in our architecture. The VLSI implementation results under the TSMC 90-ns CMOS technology reveal that our architecture requires 194.25K gates while operating at frequency 200.75 MHz. Additionally, with better normalized matrix throughput and gate efficiency, our architecture outperforms one earlier architectural design to compute the CBWs.

A low power VLSI implementation of distortion correction in image processing ASIC

A low power VLSI implementation of distortion correction in image processing ASIC

A low power VLSI implementation of distortion correction in image processing ASIC

Digital video surveillance has emerged to become widely employed in public, medical, private locations, military bases, and so on. Conventional cameras can have coverage of only a small area, resulting in 'blind spots'. They are capable of monitoring about 180° or 360° and therefore they take the place of numerous cameras. This technical work explains about a novel camera system, which employs normal cameras for achieving a broad field of view along with selective focus of interest. This research discusses about a novel non-linear technique for the removal of Barrel distortion in camera images. In order to reduce the complexity, 1-D real chaotic polynomial map is used for approximation. In this proposed work, by using 0.18 μm technology the design can achieve the frequency of 218 MHz having 1490 logic elements. This technique decreases the cost incurred in hardware and the memory usage requirements in comparison with the earlier techniques.

Low Latency IDMA With Interleaved Domain Architecture for 5G Communications

Non-orthogonal multiple access (NOMA) is a promising candidate for the future fifth generation systems because of its ability to provide greater spectral efficiency. Interleave division multiple access (IDMA) is one of the NOMA techniques that can support multiple access for a large number of users in the same bandwidth. One of the problems in the hardware implementation of IDMA is its high latency due to iterative processing. In this paper, we propose a novel architecture for the IDMA receiver with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially handles deinterleaving, despreading, spreading, and interleaving for multi-user detection. The proposed architecture which we call interleaved domain multi-user detection can perform multi-user detection directly without deinterleaving the received frame in the interference canceller iteration resulting in the decrease of latency by almost half. We also describe the memory design which is able to implement the proposed architecture. The results show that due to the reduction of the latency by half, the throughput can be increased by twice compared with the conventional architecture. VLSI implementation results show that the proposed architecture has reduced circuit area and power consumption by 53% and 58%, respectively, compared with the conventional architecture with the same throughput condition.

VLSI Implementation Multimodal Biometric Recognition System Using Improved Pulse Coupled Neural Network for Digital Nano-CMOS Technology

VLSI Implementation Multimodal Biometric Recognition System Using Improved Pulse Coupled Neural Network for Digital Nano-CMOS Technology

Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology

A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3 V interface. A new level converter realized with +1.8 V devices that can convert 0/1 V voltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.

Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation.

Compressed sensing (CS) is a promising approach to the compression and reconstruction of electrocardiogram (ECG) signals. It has been shown that following reconstruction, most of the changes between the original and reconstructed signals are distributed in the Q, R, and S waves (QRS) region. Furthermore, any increase in the compression ratio tends to increase the magnitude of the change. This paper presents a novel approach integrating the near-precise compressed (NPC) and CS algorithms. The simulation results presented notable improvements in signal-to-noise ratio (SNR) and compression ratio (CR). The efficacy of this approach was verified by fabricating a highly efficient low-cost chip using the Taiwan Semiconductor Manufacturing Company’s (TSMC) 0.18-μm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The proposed core has an operating frequency of 60 MHz and gate counts of 2.69 K.

Vedic algorithm for cubic computation and VLSI implementation

Algorithm of cubic computation and its VLSI implementation is described in this paper through ‘Vedic mathematics’ formulae. An N-bit cubic implementation circuit was structured into two cubic subgroups (bit length=N2 or lesser), multiplier and adder. VLSI aspects such as propagation delay and dynamic power consumption of such circuitry were lessened down notably by reducing the number of partial products. Designs implementation and estimation of performance parameters: delay and power consumption were figured out by spice spectre with 90nm CMOS technology. The estimated values for propagation delay and power consumption of the reported 8-bit cubic circuitry were ∼5.5ns and ∼2.6mW respectively. Propagation delay has been enhanced by ∼12% and power consumption dropped down by ∼22% in comparison to its counterpart (traditional architecture).

Fast and Efficient VLSI Implementation of DWT for Image Compression

Fast and Efficient VLSI Implementation of DWT for Image Compression

A Random Linear Network Coding Accelerator in a 2.4GHz Transmitter for IoT Applications

Random linear network coding (RLNC) is an emerging coding technique, which can provide several advantages in wireless networks, such as throughput gains, increased data robustness, and better utilization of network resources. In this paper, we present the first custom VLSI implementation of RLNC, integrated with an ultralow-power 2.4-GHz transmitter. We examine its energy efficiency and error recovery performance in the context of Internet of Things applications, and we perform experiments quantifying its benefits when it operates separately and jointly with physical layer forward error correction (FEC) codes, as a joint channel and network coding scheme. The chip is fabricated in a 65-nm CMOS process, occupies $2 \times 1.3 ~{\mathrm{ m}}{\mathrm{ m}}^{2}$ and consumes 580 pJ/bit for processing and transmitting data at 1 Mbps. The digital packet processor and encoder occupies $200\times 200 ~\mu {\mathrm{ m}}^{2}$ , consists of an on-chip memory, a multi-rate convolutional encoder, and a RLNC accelerator with configurable redundancy, and consumes $15\mu \text{W}$ , operating at 0.4 V. For improved spectral efficiency, an on-chip pulse shaping filter is implemented, reducing side lobes by 28 dB while consuming $15\mu \text{W}$ . According to our over-the-air experiments, RLNC can provide an effective SNR improvement of 5.6 dB when combined with FEC rate 1/2, and 3.4 dB without FEC, at a packet error rate of $10^{-2}$ .

Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities

This paper presents a framework based on the logarithmic number system to implement adaptive filters with error nonlinearities in hardware. The framework is demonstrated through pipelined implementations of two recently proposed adaptive filtering algorithms based on logarithmic cost, namely, least mean logarithmic square (LMLS) and least logarithmic absolute difference (LLAD). To the best of our knowledge, the proposed architectures are the first attempts to implement both LMLS and LLAD algorithms in hardware. We derive error computing algorithms to realize the nonlinear error functions for LMLS and LLAD and map them onto hardware. We also propose a novel variable- $\alpha $ scheme to enhance the original LMLS algorithm and prove its robustness and suitability for VLSI implementations in practical applications. Detailed bit width and error analysis are carried out for the proposed VLSI fixed point implementations. Postlayout implementation results show that with an additional multiplier over conventional least mean square (LMS), 7-dB improvement in steady-state mean square deviation performance can be achieved and with the proposed variable- $\alpha $ scheme, 12-dB improvement can be achieved without compromising the convergence. We will show that LMLS can potentially replace LMS in practical applications, by demonstrating a proof-of-concept by extending the framework to transform domain adaptive filters.

Design and Implementation of Power Efficient Modified Russian Peasant Multiplier using Ripple Carry Adder

FIR filters, microprocessor and digital signal processor are the core system of multipliers. MAC is the most important building block in DSP system. The key element of high throughput multiplier and accumulator unit (MAC) is to achieve a high-performance digital signal processing application. In this paper, Modified Russian Peasant Multiplier (MRPM) using Ripple Carry Adder (RCA) has been proposed. According to Russian Rule‟s, Divide and conquer technique is used in the multiplication process. But, in perspective of digital design, only shifters and adders are used in Russian Peasant Multiplier to produce Partial Product Generation (PPG). A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Here, ripple carry adder is used for low power application. Reducing the chip size, increasing the speed and reducing the power consumption are main crucial factors in VLSI System design environment. The goal of this research work is to design the VLSI implementation of MAC for high-speed DSP applications. For designing the Multiplication and accumulation unit, different kinds of multipliers and adders are considered in this paper. The total operation is coded with Verilog HDL using ModelSim 6.3C, synthesized by using Xilinx ISE 12.4i design tool.

Hardware Design for VLSI Implementation of Acoustic Feedback Canceller in Hearing Aids

Acoustic feedback is one of the major issues associated with the hearing aid users which limits the maximum amount of gain available for amplification and degrades the sound quality. In this paper, partitioned time-domain block LMS (PTBLMS) algorithm is proposed for efficient hardware realization of acoustic feedback cancellers (AFCs) in hearing aids. A full-parallel and a folded structure is derived using the proposed PTBLMS algorithm. The folded structure utilizing the time multiplexing of convolution and correlation operation and performing them in one arithmetic unit enables better hardware utilization. A low-complexity design is employed for realization of power normalization unit (for calculating normalized convergence factor) which involves squaring and division operations. The theoretical analysis illustrates that the proposed AFC structures offer L times higher throughput rate and requires proportionately less hardware resource than the existing one where L is the block length. ASIC synthesis results reveal that the proposed folded structure involves nearly 79$$\%$$% less area-delay product and 86$$\%$$% less energy per sample compared to the existing structure.

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

An Innovative Approach of Binary Double Stage Multiplier for Real Time Applications

In today’s world of portable and super fast electronic gadgets, speed is major concern point. Multiplication is used in many applications such as Fourier transform, discrete cosine transform, and digital filtering. If the multipliers too slow, the performance of entire circuits will be reduced. On VLSI implementation level, the area also becomes quite important as more area means more system cost. So, speed and area are two important parameters in VLSI Design. This paper presents the design a Double Stage multiplier for 32*32 binary bit number multiplication. The proposed system consists of 2 stages of operation. The two stages of operation is used to complete the operation of multiplier. By extending the bits of generator an additional product of Double Stage multiplier is obtained. By lowering the complexity of the product of partial reduction we can reduce the area and delay. So, multiplication operation is performed by the Double Stage is efficient with the less area and it reduces delay i.e., speed is increased.

VLSI Implementation of Lifting Based 3-D DWT

VLSI Implementation of Lifting Based 3-D DWT