Hardware Implementation of the Compressed Beamforming Weights Calculation for the Practical Wireless MIMO-OFDM Communication System

Abstract

The compressed beamforming weights (CBWs) feedback is used in the IEEE 802.11n/ac WLAN, an example of the practical beamforming multiple input multiple output-orthogonal frequency division multiplexing system, to reduce the amount of feedback information so that the beamformee can respond rapidly to the beamformer. The CBW associated with each sub-carrier includes the quantized angles obtained from QR-decomposition (QRD) of the right singular vectors of each corresponding channel matrix. Efficient matrix QRD and singular value decomposition (SVD) together are therefore desirable for computing the CBWs associated with all sub-carriers. Considering the exemplary antenna configuration of 4 beamformer and 2 beamformee antennas, we propose to apply the same matrix triangulation to compute the SVD of a 2-by-4 matrix and to compute the QRD of a 4-by-2 matrix. We can achieve gate count reduction by exploiting only one matrix triangulation module in our architecture. The VLSI implementation results under the TSMC 90-ns CMOS technology reveal that our architecture requires 194.25K gates while operating at frequency 200.75 MHz. Additionally, with better normalized matrix throughput and gate efficiency, our architecture outperforms one earlier architectural design to compute the CBWs.