VLSI Design Process Research Articles

Implementation of Seed Flipping Test Pattern to Detect Faults in LBIST

Design and manufacturing challenges posed by the increasing transistor count and shrinking feature size in modern chips have significantly heightened the occurrence of defects. As a result, rigorous testing has become indispensable in the VLSI design process. Unfortunately, amidst the lengthy design cycles, test procedures often take a back seat, overshadowed by the primary focus on design development. To ensure high quality and reliability, it is imperative that any VLSI design be entirely fault-free before deployment. Design for Testability (DFT) techniques play a crucial role in facilitating error detection and ensuring robustness during testing phases. Among these techniques, Logic Built in Self-Test (LBIST) stands out for its effectiveness in achieving comprehensive fault coverage. Here it is implemented LBIST with a focus on enhancing fault coverage for a 16-bit test pattern using SFRG (Seed Flipping Ring Generator). This approach not only maximizes fault detection capabilities but also optimizes area and power efficiency compared to alternative pattern generators. By leveraging this test pattern, we aim to address the growing complexity and reliability demands of modern integrated circuits effectively. The code is written in HDL language with Verilog code, and it is implemented using Xilinx Vivado software tool.

Data Mining Software Tools and Methodologies for VLSI Design

Modern VLSI design process employs numerous EDA tools to produce large-size report files. It is time consuming as well as the possibility to miss some violations from EDA report files. We developed two data mining software tools targeting for the timing, noise and power grid analysis report files in one high-performance SOC design project. The software extracts, sorts and displays the key information from EDA report files into HTML forms, which can be viewed by designers using the web browser. Organization of EDA report files, configure files, program execution flows and output HTML forms are described for the developed data mining software tools.

Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques

The threat of hardware reverse engineering is a growing concern for a large number of applications. A main defense strategy against reverse engineering is hardware obfuscation. In this paper, we investigate physical obfuscation techniques, which perform alterations of circuit elements that are difficult or impossible for an adversary to observe. The examples of such stealthy manipulations are changes in the doping concentrations or dielectric manipulations. An attacker will, thus, extract a netlist, which does not correspond to the logic function of the device-under-attack. This approach of camouflaging has garnered recent attention in the literature. In this paper, we expound on this promising direction to conduct a systematic end-to-end study of the VLSI design process to find multiple ways to obfuscate a circuit for hardware security. This paper makes three major contributions. First, we provide a categorization of the available physical obfuscation techniques as it pertains to various design stages. There is a large and multidimensional design space for introducing obfuscated elements and mechanisms, and the proposed taxonomy is helpful for a systematic treatment. Second, we provide a review of the methods that have been proposed or in use. Third, we present recent and new device and logic-level techniques for design obfuscation. For each technique considered, we discuss feasibility of the approach and assess likelihood of its detection. Then we turn our focus to open research questions, and conclude with suggestions for future research directions.

An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm

Due to the compl ex growth in very large scale integration circuits, the task of optimal analog integrated circuit design by hand is very difficult. Optimization is a time consuming process having many conflicting criteria and a wide range of design parameters. Characterization of complex tradeoffs between nonlinear objectives while assuring required specifications makes analog circuit design a tedious process. The design and optimization processes have to be automated with high accuracy. Evolutionary technique may be a proficient implement for automatic design of analog integrated circuits that has been one of the most challenging topics in VLSI design process. This paper presents a competent approach for optimal designs of two analog circuits, namely, complementary metal oxide semiconductor two-stage comparator with P-type metal oxide semiconductor input driver and n-channel input, folded-cascode operational amplifier. The evolutionary technique used is particle swarm optimization (PSO) with an aging leader and challenger (ALC-PSO). The main aim is to optimize the MOS transistors’ sizes using ALC-PSO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. To exhibit the performance parameters of the circuits, simulation program with integrated circuit emphasis simulation has been carried out by using the optimal values of MOS transistor sizes and other design parameters. Simulation results demonstrate that design specifications are closely met and required functionalities are accommodated. The simulation results also show that the ALC-PSO is superior to the other algorithms in terms of MOS area, and performance parameters like gain, power dissipation, etc. for the examples considered.

A Swarm Random Walk Based Method for the Standard Cell Placement Problem

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

Artificial bee colony for the standard cell placement problem

Placement is an important step in the VLSI design process, of which standard cell placement SCP is a well-studied problem. The four 'pure' major algorithms for placement include simulated annealing, quadratic placement, min-cut placement, and force-directed placement. The four pure algorithms are inadequate for today's complex problems; hybrid methods are better able to solve the current SCP problem sizes. The objective of this paper is to present a swarm intelligence-based method for SCP. The method used to solve the SCP problem is the artificial bee colony ABC algorithm, in conjunction with hMetis, a partitioning package. Our artificial bee colony PLacer tool abcPL, has been tested on the PEKU benchmark suite. Results obtained show that ABC is a promising approach for solving the SCP problem.

Automated design debugging in a testbench-based verification environment

Debugging is one of the major bottlenecks in the current VLSI design process as design size and complexity increase. Efficient automation of debugging procedures helps to reduce debugging time and to increase diagnosis accuracy. This work proposes an approach for automating the design debugging procedures by integrating SAT-based debugging with testbench-based verification. The diagnosis accuracy increases by iterating debugging and counterexample generation, i.e., the total number of fault candidates decreases. The experimental results show that our approach while not requiring a formal specification is as accurate as exact formal debugging in 71% of the experiments.

Framework for Managing the Very Large Scale Integration Design Process

Problem statement: The VLSI design cycle was described in terms of successive states and substages; it starts with system specification and ends with packaging. At the next descriptive level, currently known methodologies (e.g., flowchart based, object-oriented based) lack a global conceptual representation suitable for managing the VLSI design process. Technical details were intermixed with tool-dependent and implementation issues such as control flow and data structure. It was important to fill the gap between these two levels of description because VLSI chip manufacturing was a complex management project and providing a conceptual detailed depiction of the design process would assist in managing operations on the great number of generated artifacts. Approach: This study introduces a conceptual framework representing flows and transformations of various descriptions (e.g., circuits, technical sketches) to be used as a tracking apparatus for directing traffic during the VLSI design process. The proposed methodology views a description as an integral element of a process, called a flow system, constructed from six generic operations and designed to "handle" descriptions. It draws maps of flows of representations (called flowthings) that run through the design flow. These flowthings are created, transformed (processed), transferred, released and received by various functions along the design flow at different levels (a hierarchy). The resultant conceptual framework can be used to support designers with computer-aided tools to organize and manage chains of tasks. Results: The proposed model for managing the VLSI design process was characterized by being conceptual (no technical or implementation details) and can be uniformly applied at different levels of design and to various kinds of artifacts. The methodology is applied to describe the VLSI physical design stage that includes partitioning, floorplanning and placement, routing, compaction and extraction and verification. Conclusion: The resultant conceptual picture demonstrates a viable description method that can be adapted for different stages and used in developing systems for managing the VLSI design process.

Minimizing Leakage of Sequential Circuits through Flip-Flop Skewing and Technology Mapping

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers’ effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

Incremental Design Debugging in a Logic Synthesis Environment

In today's complex and challenging VLSI design process, multiple logic errors may occur due to the human factor and bugs in CAD tools. The designer often faces the challenge of correcting an erroneous design implementation. This study describes a simulation-based logic debugging solution for combinational circuits corrupted with multiple design errors. Unlike other simulation-based techniques that identify all errors at once, the proposed method works incrementally. At each iteration of incremental debugging, a single candidate location is rectified with linear time algorithms. This is done so that the functionality of the erroneous design gradually matches the correct one. A number of theorems, heuristics and data structures help identify a single candidate solution at each iteration and they also guide the search in the large solution space. Experiments on benchmark circuits confirm the effectiveness of incremental logic debugging.

Automatic circuit extractor for HDL description using program slicing

Design extraction and reduction have been extensively used in modern VLSI design process. The extracted and reduced design can be efficiently processed by various applications, such as formal verification, simulation, automatic test pattern generation (ATPG), etc. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of the method include that it is fine grain; it has no hardware description language (HDL) coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The results of practical designs show the significant benefits of the approach.

The practical engineer [A multi-level approach to low-power IC design

The need of popular portable electronics for long battery life is placing power reduction at the top of every IC design engineer's to-do list. A new breed of design automation tools is helping them scrimp on power at every step of the VLSI design process. The automation tools can be differentiated, to a first order, by the level of abstraction on which they operate. Lowest of all are the transistor level tools. These possess the best accuracy, but commensurately require the longest run times and have the smallest capacities-the size of the circuit that can be analyzed. While transistor level tools can assist with analyses earlier in the design process, they are typically used to characterize cells and modules for use at the higher abstraction levels. The next level of abstraction embraces the logic-level power analysis tools. The highest abstraction level for which power analysis tools exist today is the architectural level. This type of tool analyzes abstract design representations such as Verilog or VHDL RTL code. The use of these tools in power reduction design is outlined.

Statistical Module Level Area and Delay Estimation

The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of adder and shifter modules can be modeled to with in 5% accuracy while the error in delay model is bounded by 4%. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coeificient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the template.

Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors

Design-rule checking, whose efficiency depends greatly on the speed in finding an object's neighbors, is an indispensable component of any VLSI design process. Given a design, the objects it contains are usually represented by their smallest enclosing rectangles, and neighbor search is defined as the operation to find, among the collection of rectangles, the ones that are within the specified distance of a rectangle. Commonly, the rectangles are stored in a tree structure, and a region query that searches the tree starting at its root is used to find a rectangle's neighbors. In this paper, we introduce the hinted quad tree, or HQT, that supports neighbor searches directly without always starting a search at the root of the tree. We show that HQT achieves the highest neighbor-search performance among the data structures compared and uses a reasonable amount of storage.

Genetic algorithm for test scheduling with different objectives

Test scheduling is one of the hard optimization problems involved in any VLSI design process. Depending on the overall design objectives, the objective of test scheduling may differ. Since it is computationally infeasible to solve this problem optimally, different approximation schemes are employed for different objectives resulting in different formulations. In this paper we show that test scheduling with different objective functions can be formulated and approximately solved in a common framework using genetic algorithms. The genetic algorithm is presented and experimental results for three different formulations are shown. The results show that the proposed genetic algorithm provides a uniform framework for obtaining near optimal solutions for the test scheduling problem with different objectives. Comparison with branch and bound method solutions reveal the superiority of the genetic algorithm.

General-purpose parallel hardware approach to the routing problem of VLSI layout

A novel solution to the important problem of speeding up the routing process in integrated circuit (IC) design, involving the use of general-purpose parallel computing hardware, is introduced. In the past, attempts to speed up any one stage of the VLSI design process have often resulted in a very expensive, dedicated piece of hardware which cannot be used to speed up other phases of the design process. In the case of routing, dedicated hardware has been designed to accelerate specifically the maze routing algorithm, which is more useful for routing PCBs rather than VLSI designs. As more general-purpose parallel hardware has become available, especially in the form of workstations, there has been an increasing need to exploit parallelism in many computationally intensive applications. The paper addresses the problem of exploiting parallelism in the computationally intensive problem of routing for VLSI design. This is performed hierarchically and involves two stages: global and detailed routing. A parallel routing framework was proposed to fit into such a structure. Not only some of the ideas in the framework but also a general evaluation of the different parts of the framework are presented.

Automatic test pattern generation on parallel processors

Test generation for combinational circuits is an important step in the VLSI design process. Unfortunately, the problem is highly computation-intensive and for circuits encountered in practice, test generation time can often be enormous. In this paper, we present a parallel formulation of the backtrack search algorithm called PODEM, which is a highly used algorithm for this problem. It is known that the sequential PODEM algorithm consumes most of its execution time in generating tests for ‘hard-to-detect’ (HTD) faults and is often unable to detect them even after a large number of backtracks. Our parallel formulation overcomes these limitations by dividing the search space and searching it concurrently using multiple processes. We present a number of experimental results and show that these match our theoretical results presented elsewhere. We show that the search efficiency of the parallel algorithm improves and even beats that of the sequential algorithm as the ‘hardness’ of a fault increases. We present speedup results and performance analyses of our formulation on a 128 processor Symult s2010 multicomputer. We also present preliminary results on a network of Sun workstations. Our results show that parallel search techniques provides good speedups as well as high fault coverage of the HTD faults in reasonable time when compared to the uniprocessor implementation. Our experimental validation of most of our theoretical results builds confidence in the following theoretical prediction: our parallel formulation of PODEM is highly scalable on a variety of commercially-available, large MIMD parallel processors (in additions to the ones with which we experimented).

Hierarchical modeling of the VLSI design process

A description is given of the Kinden environment, which combines object-oriented modeling and model-based reasoning to capture, integrate, and manage VLSI design process attributes and hierarchies. Related work is briefly reviewed, and the modeling of the design process is discussed, focusing on the Kinden approach. The model-based reasoning on which Kinden's knowledge-processing architecture is based is described. The present implementation of Kinden is examined. >

A knowledge-based approach to VLSI-design in an open CAD-environment

A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI technique can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge - strategic and task-specific - in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design.

Introducing VLSI computer-aided design into the EE curriculum: a case study

The authors describe a case study at Purdue University's School of Electrical Engineering in the successful integration of VLSI CAD (computer-aided design) into both the undergraduate and graduate curriculum. The courses in VLSI chip design use the Manassas VLSI Interactive System for Automation (MVISA), a CAD program that implements all stages in the VLSI design process including logic entry (schematic capture), logic simulation, timing analysis, design rule checking, placement of cells, and automatic and manual wiring. The successful integration was due to several factors, including university-industry-government cooperation; the development of a comprehensive set of interactive tutorials and notes describing the lab procedures and VLSI issues considered in the class; and a coherent, structured approach to teaching system design as well as the use of CAD tools in this process. Modern educational techniques, including computer-aided instruction and videotaped lectures on VLSI, also played a part in the development of the CAD courses. >