General-purpose parallel hardware approach to the routing problem of VLSI layout

Abstract

A novel solution to the important problem of speeding up the routing process in integrated circuit (IC) design, involving the use of general-purpose parallel computing hardware, is introduced. In the past, attempts to speed up any one stage of the VLSI design process have often resulted in a very expensive, dedicated piece of hardware which cannot be used to speed up other phases of the design process. In the case of routing, dedicated hardware has been designed to accelerate specifically the maze routing algorithm, which is more useful for routing PCBs rather than VLSI designs. As more general-purpose parallel hardware has become available, especially in the form of workstations, there has been an increasing need to exploit parallelism in many computationally intensive applications. The paper addresses the problem of exploiting parallelism in the computationally intensive problem of routing for VLSI design. This is performed hierarchically and involves two stages: global and detailed routing. A parallel routing framework was proposed to fit into such a structure. Not only some of the ideas in the framework but also a general evaluation of the different parts of the framework are presented.