VLIW Architecture Research Articles

Optimizing computer vision algorithms with TVM on VLIW architecture based on RVV

Optimizing computer vision algorithms with TVM on VLIW architecture based on RVV

Evaluation of the efficiency of automated system based on processors with VLIW and X86-64 architectures through testing

Evaluation of the efficiency of automated system based on processors with VLIW and X86-64 architectures through testing

Research on Compilation Methods for Fixed Iteration Count Loop Dual-Mode Unrolling in VLIW Architectures

Research on Compilation Methods for Fixed Iteration Count Loop Dual-Mode Unrolling in VLIW Architectures

Instruction mapping techniques for processors with very long instruction word architectures

Abstract This paper presents an instruction mapping technique for generating a low-level assembly code for digital signal processing algorithms. This technique helps developers to implement retargetable kernel functions with the performance benefits of the low-level assembly languages. The approach is aimed at exceptionally long instruction word (VLIW) architectures, which benefits the most from the proposed method. Mapped algorithms are described by the signal-flow graphs, which are used to find possible parallel operations. The algorithm is converted into low-level code and mapped to the target architecture. This process also introduces the optimization of instruction mapping priority, which leads to the more effective code. The technique was verified on selected kernels, compared to the common programming methods, and proved that it is suitable for VLIW architectures and for portability to other systems.

Selective Code Duplication for Soft Error Protection on VLIW Architectures

Very Long Instruction Word, or VLIW, architectures have received much attention in specific-purpose applications such as scientific computation, digital signal processing, and even safety-critical systems. Several compilation techniques for VLIW architectures have been proposed in order to improve the performance, but there is a lack of research to improve reliability against soft errors. Instruction duplication techniques have been proposed by exploiting unused instruction slots (i.e., NOPs) in VLIW architectures. All the instructions cannot be replicated without additional code lines. Additional code lines are required to increase the number of duplicated instructions in VLIW architectures. Our experimental results show that 52% performance overhead as compared to unprotected source code when we duplicate all the instructions. This considerable performance overhead can be inapplicable for resource-constrained embedded systems so that we can limit the number of additional NOP instructions for selective protection. However, the previous static scheme duplicates instructions just in sequential order. In this work, we propose packing-oriented duplication to maximize the number of duplicated instructions within the same peroformance overhead bounds. Our packing-oriented approach can duplicate up to 18% more instructions within the same performance overheads compared to the previous static duplication techniques.

A VLIW architecture stream cryptographic processor for information security

As an important branch of information security algorithms, the efficient and flexible implementation of stream ciphers is vital. Existing implementation methods, such as FPGA, GPP and ASIC, provide a good support, but they could not achieve a better tradeoff between high speed processing and high flexibility. ASIC has fast processing speed, but its flexibility is poor, GPP has high flexibility, but the processing speed is slow, FPGA has high flexibility and processing speed, but the resource utilization is very low. This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms. By analyzing the structure model, processing characteristics and storage characteristics of stream ciphers, a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented, which has separate/cluster storage structure and is oriented to stream cipher operations. The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths, parallelism among stream cipher processing with different data bit widths, and parallelism among branch control and stream cipher processing with high instruction level parallelism; the designed separate/clustered special bit registers and general register heaps, key register heaps can satisfy cryptographic requirements. So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms. It has been implemented with 0.18μm CMOS technology, the test results show that the frequency can reach 200MHz, and power consumption is 310mw. Ten kinds of stream ciphers were realized in the processor. The key stream generation throughput of Grain-80, W7, MICKEY, ACHTERBAHN and Shrink algorithm is 100Mbps, 66.67Mbps, 66.67Mbps, 50 Mbps and 800Mbps, respectively. The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

A VLIW architecture stream cryptographic processor for information security

As an important branch of information security algorithms, the efficient and flexible implementation of stream ciphers is vital. Existing implementation methods, such as FPGA, GPP and ASIC, provide a good support, but they could not achieve a better tradeoff between high speed processing and high flexibility. ASIC has fast processing speed, but its flexibility is poor, GPP has high flexibility, but the processing speed is slow, FPGA has high flexibility and processing speed, but the resource utilization is very low. This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms. By analyzing the structure model, processing characteristics and storage characteristics of stream ciphers, a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented, which has separate/cluster storage structure and is oriented to stream cipher operations. The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths, parallelism among stream cipher processing with different data bit widths, and parallelism among branch control and stream cipher processing with high instruction level parallelism; the designed separate/clustered special bit registers and general register heaps, key register heaps can satisfy cryptographic requirements. So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms. It has been implemented with 0.18μm CMOS technology, the test results show that the frequency can reach 200MHz, and power consumption is 310mw. Ten kinds of stream ciphers were realized in the processor. The key stream generation throughput of Grain-80, W7, MICKEY, ACHTERBAHN and Shrink algorithm is 100Mbps, 66.67Mbps, 66.67Mbps, 50 Mbps and 800Mbps, respectively. The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

Performance Evaluation of a Recognition System on the VLIW Architecture by the Example of the Elbrus Platform

This paper overviews modern computing devices based on the Elbrus VLIW architecture and presents experimental results for the performance evaluation of the Smart IDReader document recognition system on these devices. Methods for speeding up the recognition system on the Elbrus platform are described, experimental estimates of the speedup improvements are presented, and the performance of various devices based on Elbrus processors is compared.

On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage

On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage

Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors

Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable computing. In this scenario, our work proposes three low overhead fault tolerance approaches based on instruction duplication with zero latency detection, which uses a rollback mechanism to correct soft errors in the pipelanes of a configurable VLIW processor. The first uses idle issue slots within a period of time to execute extra instructions considering distinct application phases. The second works at a finer grain, adaptively exploiting idle functional units at run-time. However, some applications present high instruction-level parallelism (ILP), so the ability to provide fault tolerance is reduced: less functional units will be idle, decreasing the number of potential duplicated instructions. The third approach attacks this issue by dynamically reducing ILP according to a configurable threshold, increasing fault tolerance at the cost of performance. While the first two approaches achieve significant fault coverage with minimal area and power overhead for applications with low ILP, the latter improves fault tolerance with low performance degradation. All approaches are evaluated considering area, performance, power dissipation, and error coverage.

Advanced Vecliw Architecture For Executing Multi-Scalar/Vector Instructions On Unified Datapath

This paper proposes new processor architecture for accelerating data-parallel applications based on the combination of VLIW and vector processing paradigms. It uses VLIW architecture for processing multiple independent scalar instructions concurrently on parallel execution units. Data parallelism is expressed by vector ISA and processed on the same parallel execution units of the VLIW architecture. The proposed processor, which is called VecLIW, has unified register file of 64x32-bit registers in the decode stage for storing scalar/vector data. VecLIW can issue up to four scalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results. However, it cannot issue more than one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to data cache. Four 32-bit results can be written back into VecLIW register file. The complete design of our proposed VecLIW processor is implemented using Verilog HDL.

A reconfigurable block cryptographic processor based on VLIW architecture

An Efficient and flexible implementation of block ciphers is critical to achieve information security processing. Existing implementation methods such as GPP, FPGA and cryptographic application-specific ASIC provide the broad range of support. However, these methods could not achieve a good tradeoff between high-speed processing and flexibility. In this paper, we present a reconfigurable VLIW processor architecture targeted at block cipher processing, analyze basic operations and storage characteristics, and propose the multi-cluster register-file structure for block ciphers. As for the same operation element of block ciphers, we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme. The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations, but also realizes dynamic configuration for cryptographic processing units. It has been implemented with 0.18μm CMOS technology, the test results show that the frequency can reach 350MHz, and power consumption is 420mw. Ten kinds of block and hash ciphers were realized in the processor. The encryption throughput of AES, DES, IDEA, and SHA-1 algorithm is 1554Mbps, 448Mbps, 785Mbps, and 424Mbps respectively, the test result shows that our processor's encryption performance is significantly higher than other designs.

Parameter Space Representation of Pareto Front to Explore Hardware-Software Dependencies

Embedded systems design requires conflicting objectives to be optimized with an appropriate choice of hardware-software parameters. A simulation campaign can guide the design in finding the best trade-offs, but due to the big number of possible configurations, it is often unfeasible to simulate them all. For these reasons, design space exploration algorithms aim at finding near-optimal system configurations by simulating only a subset of them. In this work, we present PS, a new multiobjective optimization algorithm, and evaluate it in the context of the embedded system design. The basic idea is to recognize interesting regions—that is, regions of the configuration space that provide better configurations with respect to other ones. PS evaluates more configurations in the interesting regions while less thoroughly exploring the rest of the configuration space. After a detailed formal description of the algorithm and the underlying concepts, we show a case study involving the hardware/software exploration of a VLIW architecture. Qualitative and quantitative comparisons of PS against a well-known multiobjective genetic approach demonstrate that while not outperforming it in terms of Pareto dominance, the proposed approach can balance the uniformity and granularity qualities of the solutions found, obtaining more extended Pareto fronts that provide a wider view of the potentiality of the designed device. Therefore, PS represents a further valid choice for the designer when objective constrains allow it.

FPGA BASED 128-BIT CUSTOMISED VLIW PROCESSOR FOR EXECUTING DUAL SCALAR/VECTOR INSTRUCTIONS

This paper proposes new processor architecture for accelerating data-parallel applications based on the combination of VLIW and vector processing paradigms. It uses VLIW architecture for processing multiple independent scalar instructions concurrently on parallel execution units. Data parallelism is expressed by vector ISA and processed on the same parallel execution units of the VLIW architecture. The proposed processor, which is called VLIW, has unified register file of 64x32-bit registers in the decode stage for storing scalar/vector data. VLIW can issue up to four scalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results. However, it cannot issue more than one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to data cache.. The complete design of our proposed VLIW processor is implemented using Verilog. our proposed VLIW processor is implemented using Verilog targeting the Xilinx FPGA Virtex-5, XC5VLX110T-3FF1136 device. The required numbers of slice registers and LUTs are 20292 and 24214 out of 28800 respectively.

Instruction selection and scheduling for DSP kernels

As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modeling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation.

A systematic approach for optimized bypass configurations for application-specific embedded processors

The diversity of today's mobile applications requires embedded processor cores with a high resource efficiency, that means, the devices should provide a high performance at low area requirements and power consumption. The fine-grained parallelism supported by multiple functional units of VLIW architectures offers a high throughput at reasonable low clock frequencies compared to single-core RISC processors. To efficiently utilize the processor pipeline, common system architectures have to cope with data hazards due to data dependencies between consecutive operations. On the one hand, such hazards can be resolved by complex forwarding circuits (i.e., a pipeline bypass) which forward intermediate results to a subsequent instruction. On the other hand, the pipeline bypass can strongly affect or even dominate the total resource requirements and degrade the maximum clock frequency. In this work the CoreVA VLIW architecture is used for the development and the analysis of application-specific bypass configurations. It is shown that many paths of a comprehensive bypass system are rarely used and may not be required for certain applications. For this reason, several strategies have been implemented to enhance the efficiency of the total system by introducing application-specific bypass configurations. The configuration can be carried out statically by only implementing required paths or at runtime by dynamically reconfiguring the hardware. An algorithm is proposed which derives an optimized configuration by iteratively disabling single bypass paths. The adaptation of these application-specific bypass configurations allows for a reduction of the critical path by 26%. As a result, the execution time and energy requirements could be reduced by up to 21.5%. Using Dynamic Frequency Scaling (DFS) and dynamic deactivation/reactivation of bypass paths allows for a runtime reconfiguration of the bypass system. This ensures the highest efficiency while processing varying applications.

LUCAS

Clustered VLIW architectures are statically scheduled wide-issue architectures that combine the advantages of wide-issue processors along with the power and frequency scalability of clustered designs. Being statically scheduled, they require that the decision of mapping instructions to clusters be done by the compiler. State-of-the-art code generation for such architectures combines cluster-assignment and instruction scheduling in a single unified pass. The performance of the generated code, however, is very susceptible to the inter-cluster communication latency. This is due to the nature of the two clustering heuristics used. One is aggressive and works well for low inter-cluster latencies, while the other is more conservative and works well only for high latencies. In this paper we propose LUCAS, a novel unified cluster-assignment and instruction-scheduling algorithm that adapts to the inter-cluster latency better than the existing state-of-the-art schemes. LUCAS is a hybrid scheme that performs fine-grain switching between the two state-of-the art clustering heuristics, leading to better scheduling than either of them. It generates better performing code for a wide range of inter-cluster latency values.

Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures

Soft errors are becoming a critical concern in embedded system designs. Code duplication techniques have been proposed to increase the reliability in multi-issue embedded systems such as VLIW by exploiting empty slots for duplicated instructions. However, they increase code size, another important concern, and ignore vulnerability differences in instructions, causing unnecessary or inefficient protection when selecting instructions to be duplicated under constraints. In this article, we propose a compiler-assisted dynamic code duplication method to minimize the code size overhead, and present vulnerability-aware duplication algorithms to maximize the effectiveness of instruction duplication with least overheads for VLIW architecture. Our experimental results with SoarGen and Synopsys simulation environments demonstrate that our proposals can reduce the code size by up to 40% and detect more soft errors by up to 82% via fault injection experiments over benchmarks from DSPstone and Livermore Loops as compared to the previously proposed instruction duplication technique.

A Function-Oriented Local Scheduling Framework for VLIW Architectures in Assembly-Level

A Function-Oriented Local Scheduling Framework for VLIW Architectures in Assembly-Level

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture

Worst-Case Execution Time (WCET) is one of the most important metrics in real-time embedded system design. For embedded systems with clustered VLIW architecture, register allocation, instruction scheduling, and cluster assignment are three key activities to pursue code optimization which have profound impact on WCET. At the same time, these three activities exhibit a phase ordering problem: Independently performing register allocation, scheduling and cluster assignment could have a negative effect on the other phases, thereby generating sub-optimal compiled codes. In this paper, a compiler level optimization, namely WCET-aware Re-scheduling Register Allocation (WRRA), is proposed to achieve WCET minimization for real-time embedded systems with clustered VLIW architecture. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling and cluster assignment on the quality of generated code are taken into account for WCET minimization. These three compilation processes are integrated into a single phase to obtain a balanced result. The proposed technique is implemented in Trimaran 4.0. The experimental results show that the proposed technique can reduce WCET effectively, by 33% on average.