Vivado High-level Synthesis Research Articles

Expanding hardware accelerator system design space exploration with gem5-SALAMv2

With the prevalence of hardware accelerators as an integral part of the modern systems on chip (SoCs), the ability to model accelerators quickly and accurately within the system in which it operates is critical. This paper presents gem5-SALAMv2 as a novel system architecture for LLVM-based modeling and simulation of custom hardware accelerators integrated into the gem5 framework. It overcomes the inherent limitations of state-of-the-art trace-based pre-register-transfer level (RTL) simulators by offering a truly “execute-in-execute” LLVM-based model. It enables scalable modeling of multiple dynamically interacting accelerators with full-system simulation support. To create long-term sustainable expansion compatible with the gem5 system framework, gem5-SALAM offers a general-purpose and modular communication interface and memory hierarchy integrated into the gem5 ecosystem, streamlining designing and modeling accelerators for new and emerging applications. gem5-SALAMv2 expands upon the framework established in gem5-SALAMv1 with improved LLVM-based elaboration and simulation, improved and more extensible system integration, and new automations to simplify rapid prototyping and design space exploration. 11Conference Paper Extension: This work extends the work presented in gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling from MICRO 2020 (Rogers et al., 2020). This work expands on the aforementioned work by revamping the gem5-SALAM internals to provide more robust and extensible simulations, introducing new automation tools for expanding and simplifying design space exploration, and demonstrates the new capabilities of gem5-SALAMv2 by exploring multiple configurations of simple neural network architectures.Validation on the MachSuite (Reagen et al., 2014) benchmarks presents a timing estimation error of less than 1% against the Vivado High-Level Synthesis (HLS) tool. Results also show less than a 4% area and power estimation error against Synopsys Design Compiler. Additionally, system validation against implementations on an Ultrascale+ ZCU102 shows an average end-to-end timing error of less than 2%. Lastly, we demonstrate the upgraded capabilities of gem5-SALAMv2 by exploring accelerator platforms for two deep neural networks, LeNet5 and MobileNetv2. In these explorations, we demonstrate how gem5-SALAMv2 can simulate such systems and guide architectural optimizations for these types of accelerator-rich architectures. 22The most up-to-date version of gem5-SALAMv2 is available at https://github.com/TeCSAR-UNCC/gem5-SALAM..

A New Optimized Hybridization Approach for in silico High Throughput Molecular Docking on FPGA Platform.

The development process of a new drug should be a subject of continuous evolution and rapid improvement as drugs are essential to treat a wide range of diseases of which many are life-threatening. The advances in technology resulted in a novel track in drug discovery and development known as in silico drug design. The molecular docking phase plays a vital role in in silico drug development process. In this phase, thousands of 3D conformations of both the ligand and receptor are generated and the best conformations that create the most stable drug-receptor complex are determined. The speed in finding accurate and high-quality complexes depends on the efficiency of the search function in the molecular docking procedure. The objective of this research is to propose and implement a novel hybrid approach called hABCDE to replace the EMC searching part inside the BUDE docking algorithm. This helps in reaching the best solution in a much accelerated time and higher solution quality compared to using the ABC and DE algorithms separately. In this work, we have employed a new approach of hybridization between the Artificial Bee Colony (ABC) algorithm and the Differential Evolution (DE) algorithm as an alternative searching part of the Bristol University Docking Engine (BUDE) in order to accelerate the search for higher quality solutions. Moreover, the proposed docking approach was implemented on Field Programmable Gate Array (FPGA) parallel platform using Vivado High-Level Synthesis Tool (HLST) in order to optimize and enhance the execution time and overall efficiency. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The results showed that the execution time for the BUDE with the new proposed hybridization approach was improved by 9,236 times. Our novel approach was significantly effective to improve the functionality of docking algorithms (Bristol University Docking Engine (BUDE)).

Notification Oriented Paradigm to Digital Hardware — A benchmark evaluation with Random Forest algorithm

The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative minimal entities. This inference implicitly allows achieving decoupled solutions, thereby enabling parallelism at a granularity level as fine-grained as possible in the envisaged computational platform. Previous research has proposed a digital circuit solution based on the NOP model, which is called NOP to Digital Hardware (DH), as a sort of High-Level Synthesis (HLS) prototype tool. The results with NOP-DH were encouraging indeed. However, the previous NOP-DH works lack benchmarks that exploit well-known algorithms against known HLS tools, such as the Vivado HLS tool, which is one of the suitable commercial HLS solutions. This work proposes evaluating the NOP-DH applied to develop the well-known Random Forest algorithm. The Random Forest is a popular Machine Learning algorithm used in several classification and regression applications. Due to the high number of logic-causal evaluations in the Random Forest algorithm and the possibility of running them in parallel, it is suitable for envisaged benchmark purpose. Experiments were performed to compare NOP-DH, and two Vivado HLS approaches (an ad hoc code and a hls4ml tool-based code) in terms of performance, amount of logic elements, maximum frequency, and the number of predictions per second. Those experiments demonstrated that NOP-DH circuits achieve better results concerning the number of logical elements and prediction rates, with some scalability limitations as a drawback. On average, the NOP-DH uses 52.5% fewer resources, and the number of predictions per second is 4.7 times higher than Vivado HLS. Finally, our codes are made publicly available at https://nop.dainf.ct.utfpr.edu.br/nop-public/nop-dh-random-forest-algorithm.

FPGA implementation of QUasi-Affine TRansformation evolutionary algorithm

The QUasi-Affine TRansformation Evolutionary (QUATRE) algorithm, a new intelligence optimization algorithm, has been widely used in many optimization fields. In this paper, a hardware-based QUATRE algorithm is designed and implemented on a field-programmable gate array (FPGA). To facilitate the implementation of the QUATRE algorithm on hardware, this paper simplifies the co-evolutionary matrix generation process. Compared with the original QUATRE algorithm, the simplified QUATRE algorithm may reduce latency and resource occupation. The Vivado High-Level Synthesis (HLS) design tool is used to complete the IP core design of the QUATRE algorithm. Through the benchmark function test under different population sizes, compared with the QUATRE algorithm implemented by software, both the running speed and optimization performance of the QUATRE algorithm implemented by hardware are significantly better than the former. Compared with the GA, DE, and PSO algorithms implemented by hardware, the QUATRE algorithm also shows strong competitiveness.

Accelerated FPGA-Based Vector Directional Filter for Real-Time Color Image Denoising with Enhanced Performance

This paper presents an accelerated implementation of the Vector Directional Filter (VDF) on a Field Programmable Gate Array (FPGA) for real-time denoising of color images. The VDF effectively suppresses noise while preserving edges and fine details, making it ideal for a range of applications such as satellite and multispectral biomedical imaging. However, the filter's high computational complexity poses challenges for real-time processing. Existing solutions either fail to meet real-time execution requirements or compromise image quality through hardware implementation approximations. To overcome these challenges, we first model the VDF using C/C++ programming, and subsequently design an efficient floating-point hardware architecture employing the High-Level Synthesis (HLS) flow. Optimal directives are selected using the Xilinx Vivado HLS tool. The VDF architecture is then integrated as a coprocessor with the Cortex-A53 hardcore processor in the XCZU9EG FPGA. To enhance data bandwidth between software and hardware components, three Direct Memory Access (DMAs) units are utilized to transfer three image lines in parallel. Furthermore, internal memory is implemented on the XCZU9EG FPGA, providing increased flexibility for managing the restored image. The VDF Software/Hardware (SW/HW) design's robustness and accuracy are validated through experimental studies on the ZCU102 board. Our design accelerates the filtering process by 21 times, maintaining visual quality and effectively removing noise from color images compared to the VDF SW design. Additionally, our solution outperforms existing approaches in terms of filtered image quality and processing time, showing a 24% improvement in the worst-case scenario.

A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs

Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC)-based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. Different data placement policies may lead to different system performance, and finding an optimal data placement policy is a nontrivial problem. For instance, we show counter-intuitive results that traditional frequency and locality-based data placement strategy designed for CPU architecture leads to nonoptimal system performance in CPU-FPGA HMPSoCs. In this work, we first propose an automatic data placement framework for field programmable gate array (FPGA) kernels to determine whether each array object should be accessed via the on-chip BRAM, shared CPU L2-cache, or DDR memory to achieve the optimal performance. Moreover, we find that when the CPU kernel and the FPGA kernel are executed in parallel, memory contentions may degrade the performance and the optimal data placement policy designed for the FPGA kernel alone will not achieve the optimal overall system performance. In this article, we proposed to use cache partitioning to alleviate the impact brought by memory contentions. We extend the framework designed for FPGA by adding the cross-layer memory contentions analysis to automatically generate an optimal data placement policy and cache partitioning mechanism for the parallel executing kernels. The proposed data placement framework can be seamlessly integrated with the commercial Vivado HLS. The experimental results on the Zedboard platform show an average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> performance speedup for FPGA kernels compared with a greedy-based allocation strategy. When FPGA kernels and CPU kernels are executed in parallel, the FPGA kernel and the CPU kernel have a performance speedup of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.62\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.10\times $ </tex-math></inline-formula> on average, respectively.

Neuromorphic circuit based on the un-supervised learning of biologically inspired spiking neural network for pattern recognition

One of the most sophisticated platforms for hosting intelligent systems is bio-inspired. This study proposes pattern recognition hardware using a biologically inspired Spiking Neural Network (SNN) and the new dimensionality reduction approach. The SNN model is based on real neural networks consisting of spiking neurons linked by excitatory and inhibitory synapses activated by excitatory and inhibitory neurotransmitters. Also, a semi-supervised (un-supervised STDP based learning with supervised weight initialization), spike-based learning strategy based on the learning procedure of the nervous system is used to teach the spiking output layer neurons, albeit that the hardware implementation benefits from a semi-supervised approach. The goal of this research is to accurately categorize patterns in the MNIST and CIFAR10 datasets using an SNN-based hardware platform. Due to the limitations of the latter’s resources, a dimensionality reduction based on principal component analysis (PCA) is proposed to speed up the processing procedure and reduce the hardware implementation cost. The presented pattern recognition platform is implemented using the Xilinx® VIVADO high-level synthesis platform (HLS). Finally, optimization approaches are used to improve the used space, reduce hardware implementation delay, and speed up the design process.

Implementation and Hardware Acceleration of Wiener filter algorithm using Vivado High Level Synthesis HLS for X-ray baggage Images

Many computer vision applications require a real-time image de-noising technique. In recent years to detecting hazardous materials using X-ray baggage images is important means of airport security applications. The image denoising functions to aid decision making by humans is a predictable area of critical need. However, implementing the image processing approach in Hardware Description Language is time consuming and difficult to debug. With High Level Synthesis HLS, the designer may take advantage of libraries to reap the benefits of working at a higher level of abstraction while producing high-performance hardware. HLS tools, on the other hand, provide prospective solutions to hardware design. HLS tools provide us with extensive design assessment capabilities as well as a wide range of optimization strategies. In this research article, Intellectual Property IP core of wienerfilter algorithm is built utilizing HLS and implemented on ZYNQ platform for X-ray baggage image screening applications. We used Pipeline Pragma techniques added to the HLS environment improved performance, and the results were far better than predicted. The solution using the Pragma method with pipelining was to optimize area and 89 percent clock cycle reduction, and the relevance of the pipeline with this speed was well suitable to improve real time performance.

Hardware Acceleration of Video Edge Detection with Hight Level Synthesis on the Xilinx Zynq Platform

The study conducted in the current paper consists of validating an original design flow for the rapid prototyping of real-time image and video processing applications on FPGAs. A video application for edge detection with Simulink HDL coder and Vivado High-Level Synthesis (HLS) has been designed as if the code was going to be executed on a conventional processor. The developed tools will automatically translate the code into VHDL hardware language using an advanced compilation technique. This amounts to embedding processors on Xilinx Zynq-7000 System on-Chip (SoC) device in an optimal manner. This automated hardware design flow reduces the time to create a prototype since only the high-level description is required. The design of the video edge detection system is implemented on Xilinx Zynq-7000 platform. The result of the implementation gave effective resource utilization and a good frame rate (95 FPS) under 170MHz frequency.

An FPGA Design for Real-Time Image Denoising

The increasing use of images in miscellaneous applications such as medical image analysis and visual quality inspection has led to growing interest in image processing. However, images are often contaminated with noise which may corrupt any of the following image processing steps. Therefore, noise filtering is often a necessary preprocessing step for the most image processing applications. Thus, in this paper an optimized field-programmable gate array (FPGA) design is proposed to implement the adaptive vector directional distance filter (AVDDF) in hardware/software (HW/SW) codesign context for removing noise from the images in real-time. For that, the high-level synthesis (HLS) flow is used through the Xilinx Vivado HLS tool to reduce the design complexity of the HW part. The SW part is developed based on C/C++ programming language and executed on an advanced reduced instruction set computer (RISC) machines (ARM) Cortex-A53 processor. The communication between the SW and HW parts is achieved using the advanced extensible Interface stream (AXI-stream) interface to increase the data bandwidth. The experiment results on the Xilinx ZCU102 FPGA board show an improvement in processing time of the AVDDF filter by 98% for the HW/SW implementation relative to the SW implementation. This result is given for the same quality of image between the HW/SW and SW implementations in terms of the normalized color difference (NCD) and the peak signal to noise ratio (PSNR).

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for all Transform Unit (TU) block size, including 4 × 4, 8 × 8, 16 × 16 and 32 × 32. This architecture is designed using the High-Level Synthesis (HLS) and the Low-Level Synthesis (LLS) methods in order to compare and determine the best method to implement in real-time the DE/IT module. In fact, the C/C++ programming language is used to generate an optimized hardware design for DE/IT module through the Xilinx Vivado HLS tool. On the other hand, the LLS hardware architecture is designed by the VHSIC Hardware Description language (VHDL) and using the pipeline technique to decrease the processing time. The experimental results on the Xilinx XC7Z020 FPGA show that the LLS design increases the throughput in term of frame rate by 80% relative to HLS design with a 4.4% increase in the number of Look-Up Tables (LUTs). Compared with existing related works in literature, the proposed architectures demonstrate significant advantages in hardware cost and performance improvement.

FPGA-based DFT system design, optimisation and implementation using high-level synthesis

In this paper, a discrete Fourier transform (DFT) algorithm is designed and optimised for the FPGA implementation using the Xilinx VIVADO High-Level Synthesis (HLS) tool. The DFT algorithm is written by C++ programming and simulated for functional verification in the HLS and MATLAB. For hardware validation, the DFT module is packaged as an IP core and tested in a VIVADO project. A Xilinx SDK application written by C language is developed and used for testing the DFT module on a Zynq FPGA development board, ZedBoard. For visualisation of the DFT magnitude spectrum generated in FPGA, a GUI is developed by C# programming and related commands/data can be communicated between the GUI and ZedBoard over the serial port. Experimental results are presented with discussion. The DFT module design, optimisation and implementation as well as the VIVADO project development methods can be extended to other FPGA applications.

Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism

Performance optimization is an important goal for High-level Synthesis (HLS). Existing HLS scheduling algorithms are all based on Control and Data Flow Graph (CDFG) and will schedule basic blocks in sequential order. Our study shows that the sequential scheduling order of basic blocks is a big limiting factor for achievable circuit performance. In this article, we propose a Dependency Graph (DG) with two important properties for scheduling. First, DG is a directed acyclic graph. Thus, no loop breaking heuristic is needed for scheduling. Second, DG can be used to identify the exact instruction parallelism. Our experiment shows that DG can lead to 76% instruction parallelism increase over CDFG. Based on DG, we propose a bottom-up scheduling algorithm to achieve much higher instruction parallelism than existing algorithms. Hierarchical state transition graph with guard conditions is proposed for efficient implementation of such high parallelism scheduling. Our experimental results show that our DG-based HLS algorithm can outperform the CDFG-based LegUp and the state-of-the-art industrial tool Vivado HLS by 2.88× and 1.29× on circuit latency, respectively.

High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing

In this paper, we discuss the implementation strategies of an explicit matrix inversion technique based on the recursive Gram matrix inversion update (RGMIU) algorithm. These strategies are explicitly chosen to optimize the design for high throughput dictated by the enhanced mobile broad band (eMBB) use case and by the low latency imposed by the ultra-reliable low-latency communications (URLLCs) use case. The RGMIU algorithm is recently proposed to implement the zero forcing (ZF) problem encountered in massive multiple-input multiple-output (MIMO) detection task. We therefore compare and analyse the performance in terms of symbol error rate (SER) against popular implicit and explicit methods such as optimized coordinate descent (OCD), Gauss-Seidel (GS) and Neumann series expansion (NSE) algorithms. To determine the optimal word length, a fixed-point analysis shows that 16 bits are enough to reach a floating-point precision. We, thereafter, use Vivado High-Level Synthesis tools and optimization directives to implement the RGMIU algorithm based on three strategies to infer key insights and design trade-offs from the resource's utilization, latency, throughput and energy efficiency.

A Highly Configurable High-Level Synthesis Functional Pattern Library

FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synthesis (HLS) allows developers to design FPGA circuits more efficiently with a more familiar programming language, a higher level of abstraction, and automatic adaptation of timing constraints. When using HLS tools, such as Xilinx Vivado HLS, specific design patterns and techniques are required in order to create high-performance circuits. Moreover, designing efficient concurrency and data flow structures requires a deep understanding of the hardware, imposing more learning costs on programmers. In this paper, we propose a set of functional patterns libraries based on the MapReduce model, implemented by C++ templates, which can quickly implement high-performance parallel pipelined computing models on FPGA with specified simple parameters. The usage of this pattern library allows flexible adaptation of parallel and flow structures in algorithms, which greatly improves the coding efficiency. The contributions of this paper are as follows. (1) Four standard functional operators suitable for hardware parallel computing are defined. (2) Functional concurrent programming patterns are described based on C++ templates and Xilinx HLS. (3) The efficiency of this programming paradigm is verified with two algorithms with different complexity.

Implementation of Efficient Stopping Criteria for Turbo Decoding

The cellular systems with 4th generation, Long Term Evolution (LTE) standard have been transmitted the data at higher rates than the 3G, and 2G systems, in an ever-crowded frequency spectrum. This transmission needs more accuracy, high reliability, and throughput with a low area and power consumption. Therefore, it requires an efficient error control coding. Turbo code is used for LTE system for its good error correction ability at low signal to noise power ratio which can approach Shannon limit performance for large frame lengths. This paper presents a simple and efficient modification that can be applied to all present stopping criterion (SC) to achieve the quality of service mentioned previously. It’s proved that using a trimmed sequence of log-likelihood values (LLR) instead of the full length in the algorithms of stopping the iterative decoding has a significant impact on the utilized silicon area and throughput without a significant sacrifice in performance. It also presents a comparison of designing the Soft-Output Viterbi (SOVA) decoder using different arbitrary-precision fixed data types that offers by Vivado high-level synthesis (HLS) instead of the costlier float representation to reduce processing time and consumed area. Due to its high flexibility in designing and implementing prototype systems, the FPGA device (Kintex-7, Xilinx part number XC7K325T-2FFG900C) was utilized with different parallelism and loop pipelining directives to ensure acquiring the targeted initiation interval and silicon area.

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use high-level synthesis (HLS) to speed up register-transfer level (RTL) code generation from C++ or OpenCL source code, placement and routing issues, such as congestion, can still prevent achieving an FPGA programming bitstream or dramatically reduce the FPGA implementation performance. Congestion reports from physical design tools refer to thousands of RTL signal names instead of developer-accessible identifiers and statements, considerably complicating the developer understanding and resolution of the issues at the source level. We propose a high-level back-annotation flow that summarizes the routing congestion issues at the source level by analyzing the reports from the FPGA physical design tools and the internal debugging files of the HLS tools. Our flow describes congestion using comments back-annotated on the source code and identifies if the congestion causes are the on-chip memories or the DSP units (multipliers/adders), which are the shared resources very often associated with routing problems on FPGAs. We demonstrate on realistic large designs how the information provided by our flow helps to quickly spot congestion causes at the source level and to solve them using appropriate HLS directives.

Design, optimisation and implementation of a DCT/IDCT-based image processing system on FPGA

In this paper, a Discrete Cosine Transform (DCT) and its inverse transform IDCT are designed and optimised for FPGA using the Xilinx VIVADO High-Level Synthesis (HLS) tool. The DCT and IDCT algorithms along with a filter logic written by C/C++ are simulated for functional verification and optimised through HLS and packaged as custom IPs. The IPs are incorporated into a VIVADO project to form an image processing system for hardware validation. The VIVADO design along with a Xilinx SDK application written by C language is implemented on a Zynq FPGA development board, ZedBoard. A C# GUI is developed to transfer image data to/from the FPGA and display the original and processed images. Experimental results are presented with discussion. The FPGA development method including the DCT/IDCT IP design, optimisation and implementation via HLS as well as the VIVADO project integration can be extended to a wider range of FPGA applications.

The 3D-DTW Custom IP based FPGA Hardware Acceleration for Action Recognition

Abstract This article proposes an implementation of an action recognition system, which allows the user to perform operations in real time. The Microsoft Kinect (RGB-D) sensor plays a central role in this system, which provides the skeletal joint information of humans directly. Computationally efficient skeletal joint position features are considered for describing each action. The dynamic time warping algorithm (DTW) is a widely used algorithm in many applications such as similarity sequence search, classification, and speech recognition. It provides the highest accuracy compared to all other algorithms. However, the computational time of the DTW algorithm is a major drawback in real world applications. To speed up the basic DTW algorithm, a novel three-dimensional dynamic time warping (3D-DTW) classification algorithm is proposed in this work. The proposed 3D-DTW algorithm is implemented in both software and field programmable gate array (FPGA) hardware modeling techniques. The performance of the 3D-DTW algorithm is evaluated for 12 actions in which each action is described with the feature vector size of 576 over 32 frames. From our software modeling results, it has been shown that the proposed algorithm performs the action classification accurately. However, the computation time of the 3D-DTW algorithm increases linearly when we increase either the number of actions or the feature vector size of each action. For further speedup, an efficient custom 3D-DTW intellectual property (IP) core is developed using the Xilinx Vivado high-level synthesis (HLS) tool to accelerate the 3D-DTW algorithm in FPGA hardware. The CPU centric software modeling of the 3D-DTW algorithm is compared with its hardware accelerated custom IP core. It has been shown that the developed 3D-DTW Custom IP core computation time is 40 times faster than its software counterpart. As the hardware results are promising, a parallel hardware software co-design architecture is proposed for the Xilinx Zynq-7020 System on Chip (SoC) FPGA for action recognition. The HLS simulation and synthesis results are provided to support the practical implementation of the proposed architecture. Our proposed approach outperforms many of the existing state-of-the-art DTW based action recognition techniques by providing the highest accuracy of 97.77%.

RETRACTED: FPGA-Based Motion Estimation Algorithm Optimization

The new international video compression standards (HEVC) are referred to as video motion detection and efficient physical education video encoding. HEVC is determined by calculating the increasing complexity of video compression efficiency of the remarkable possible. Motion estimation is the most complicated arithmetic unit video encoder. Integer motion estimation and HEVC 70%, accounted for, and the video encoder's complexity calculates fractional motion estimation. High-Level Synthesis (HLS) tools algorithms have been successfully used in digital signal processing on FPGA. According to the actual requirements of the project, it is set as sports video management, target detection, video acquisition and target tracking. In order to adapt the smoothing time, the hardware configure ration consists of two parts: the intermediate results of the final optical flow vector and the optical flow calculating module generates the derivative calculation to adapt the smoothing time. Run built processor, software. FPGA chip, designed for directing data flow management and hardware components. Recommend using a first interpolation HEVC FPGA implementation scores and Vivado HLS motion estimation. The sports video target detection and tracking system designed in this paper analyzes the scene to be detected, further analyzes the moving target trajectory, and tracks the target according to the trajectory.