Vision Chip Research Articles

VCS‐IV: A real‐time vision system using a digital vision chip

AbstractA real‐time visual processing system based on a vision chip that aggregates per pixel digital processing circuitry is presented. The system supports the authors' latest vision chip and achieves high‐speed, high‐performance visual processing using an implementation that is small yet highly expandable and versatile. The main feature of the system is that the image capture function is programmable, with the operation of the internal pixel A–D conversion controlled from software at high time resolutions. The performance of the system is evaluated by application to basic visual processing and measurement systems, and examples of applications of the enhanced image capture function are presented. © 2006 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 89(6): 34–43, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20269

An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays

Massively parallel processor-per-pixel single-instruction multiple data arrays are being successfully used for early vision applications in smart sensor systems; however, they are inherently inefficient when executing algorithms involving propagation of binary signals, such as the geodesic reconstruction. Yet, these algorithms, at the interface between pixel-level and object-level image processing, should be implemented on the vision chip to facilitate data reduction at the sensor level. A cellular asynchronous network is presented in this paper, which can be used to execute binary propagation operations. The proposed circuit is optimized in terms of speed and power consumption. In 0.35-/spl mu/m technology, the simulated propagation speed is 0.18 ns per pixel and the total energy expended per propagation is 0.37 pJ per cell. In this brief, implementation issues are discussed and simulation results including image processing examples are presented.

수광 회로와 윤곽 검출 회로의 분리를 통한 윤곽 검출용 시각칩의 해상도 향상

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with <TEX>$128{\times}128$</TEX> pixel array has been designed and fabricated by using <TEX>$0.35{\mu}m$</TEX> 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

Adaptive ON-OFF spiking photoreceptor

An adaptive spike generator circuit for intelligent vision chips is presented. A pulse frequency modulation spike encoder, capable of providing very high dynamic ranges with power consumption similar to an animal retina, has been developed. The circuit is inspired by the ON-OFF opponency algorithm used by the human eye.

302 高速ビジュアルフィードバックによるリアルタイムロボット制御システムの構築(G15-1 ロボット,G15 ロボティクス・メカトロニクス)

This study concerns constructing a system which can control the attitude of a robot by Visual Information Technology (VIT). One content is the construction of High Speed Visual Feedback System for robot control. The other is the creation of the program which controls the attitude of a robot with this system. An image sensor, the Vision Chip(VC), was used for attainment of High Speed Visual Feedback System. The inverted pendulum (IP) was used as a controlled object. The feature is that VC is directly attached to a pendulum arm. In conclusion, it was showed that IP can be stabilized by this System.

３２×３２画素キャパシティブフィードバックリセット型パルス周波数変調方式低電圧ビジョンチップの試作と評価

We fabricated a low-voltage 32×32-pixel pulse-frequency-modulation vision chip with an image processing function executed in a pulse domain in a standard 0.35-μm CMOS technology. We showed the characteristics and feasibility of our vision chip architecture.

1A1-E27 高速キャッチングロボットシステム

A multifingered hand system which can catch a thrown ball at a high-speed by visual feedback control is developed. The system consists of 1ms vision chip system, high-speed multifingered hand system, and visual feedback control system. A ball is thrown from a launcher, and it arrives at a multifingered hand about within 0.1s. The hand catches the ball by its fingertips. This is a result of the project "Artificial Hand and Brain Based on Sensory-Motor Fusion Theory" in the Core Research for Evolutional Science and Technology (CREST) program of the Japan Science and Technology Agency (JST). It has been exhibited in the National Museum of Emerging Science and Innovation since July 2005.

A Low Power Analog CMOS Vision Chip for Edge Detection Using Electronic Switches

An analog CMOS vision chip for edge detection with power consumption below 20 mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts: one is a logarithmic compression photocircuit, and the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is off, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with 128 × 128 pixels, was below 20 mW. The vision chip was designed using 0.25 µm 1-poly 5-metal standard full custom CMOS process technology.

University of Manchester develops vision chip for new generation of “human” robots

University of Manchester develops vision chip for new generation of “human” robots

A Pixel-Parallel Algorithm for Detecting and Tracking Fast-Moving Modulated Light Signals

We developed a pixel-parallel image processing algorithm for detecting and tracking temporally modulated light signals for use as optical ID tags. The proposed algorithm requires no wavelength filters and obtains position information on signals at a high frame rate while decoding transmitted data. We implemented the proposed algorithm in a digital vision chip, a pixel-parallel processor embedded in a CMOS image sensor, and proved it to be operationally feasible.

A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA

We discuss a cellular-automata (CA) LSI core that extracts early features of objects in images, such as sizes and skeletons. A CMOS-image sensor with a CA core enables high-speed image processing. We propose an efficient CA algorithm based on rotated template matching. Each cell circuit in the proposed CA is implemented by a digital circuit, and transistors in each cell circuit number 198 in full customized design. The CA LSI consists of a large number of cell circuits operating in parallel to ensure fast, efficient object extraction as the number of cells increases. With a 0.25μm CMOS process, the total area of each cell circuit is 30×30μm². Simulation results indicated that image processing with 320×240 cells operates at up to 25MHz.

Real-Time Shape Recognition Using a Pixel-Parallel Processor

We propose a method to realize robust real-time shape recognition against noise and occlusion by using information of an entire image, and by performing image processing in a pixel parallel manner. The evaluation by simulation showed that the proposed method was effective for images with noise or partially occluded images. We implemented the algorithm to a vision chip which performs pixel-parallel processing and confirmed real-time operation. We also estimated the performance of the method on an ideal processor.

픽셀의 고정 패턴 잡음을 감소시킨 윤곽 검출용 시각칩

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using <TEX>$0.35\;{\mu}m$</TEX> 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

Multi-Target Tracking Using a Vision Chip and its Applications to Real-Time Visual Measurement

Real-time image processing at high frame rates could play an important role in various visual measurement. Such image processing can be realized by using a high-speed vision system imaging at high frame rates and having appropriate algorithms processed at high speed. We introduce a vision chip for high-speed vision and propose a multi-target tracking algorithm for the vision chip utilizing the unique features. We describe two visual measurement applications, target counting and rotation measurement. Both measurements enable excellent measurement precision and high flexibility because of high-frame-rate visual observation achievable. Experimental results show the advantages of vision chips compared with conventional visual systems.

A Complementary Metal-Oxide-Semiconductor Vision Chip for Edge and Motion Detection with a Function for Output Offset Cancellation

We have designed and fabricated a complementary metal-oxide-semiconductor (CMOS) vision chip by modeling cells of the human retina as hardware that are involved in edge and motion detection. There are several fluctuation factors which affect the characteristics of metal-oxide-semiconductor field effect transistors (MOSFETs) through the CMOS fabrication process and this effect appears as the output offset of the vision chip, which is composed of pixel arrays and readout circuits. The vision chip which detects edge and motion information from an input image is used for the input stage of other systems. Therefore, the output offset of the vision chip determines the efficiency of the entire system. In order to eliminate the offset at the output stage, we designed a vision chip utilizing the correlated double sampling (CDS) technique. The chip has been fabricated using a 0.6 μm standard CMOS process. With reliable output characteristics, this chip can be used at the input stage for various applications. © 2005 The Optical Society of Japan

2P1-N-096 ビジョンチップによる背景存在下での高速トラッキング(ロボットビジョン2,生活を支援するロボメカ技術のメガインテグレーション)

2P1-N-096 ビジョンチップによる背景存在下での高速トラッキング(ロボットビジョン2,生活を支援するロボメカ技術のメガインテグレーション)

2P1-N-094 Development of a High Speed Eye Tracking System Using the Vision Chip(Robot Vision 2,Mega-Integration in Robotics and Mechatronics to Assist Our Daily Lives)

2P1-N-094 Development of a High Speed Eye Tracking System Using the Vision Chip(Robot Vision 2,Mega-Integration in Robotics and Mechatronics to Assist Our Daily Lives)

2P1-N-095 CFPEアーキテクチャに基づく高解像度ビジョンチップの設計と試作(ロボットビジョン2,生活を支援するロボメカ技術のメガインテグレーション)

2P1-N-095 CFPEアーキテクチャに基づく高解像度ビジョンチップの設計と試作(ロボットビジョン2,生活を支援するロボメカ技術のメガインテグレーション)

2A1-N-096 ネットワーク接続機能を実装した高速ビジョンチップシステム(ロボットビジョン1,生活を支援するロボメカ技術のメガインテグレーション)

2A1-N-096 ネットワーク接続機能を実装した高速ビジョンチップシステム(ロボットビジョン1,生活を支援するロボメカ技術のメガインテグレーション)

A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.