Virtual Substrate Research Articles

Influence of strain, donor concentration, carrier confinement, and dislocation density on the efficiency of luminescence of Ge‐based structures on Si substrate

Electroluminescence (EL) of light‐emitting diodes (LED) with different active regions and photoluminescence (PL) of Ge layers embedded in Si barriers on Si substrates has been studied. Increasing the tensile strain in the active region of Ge LEDs by using GeSn virtual substrate technology leads to an enhancement of the direct band luminescence. An intensity increase by a factor of four is achieved due to n‐type doping with an antimony concentration of 3 × 1019 cm−3. The EL of LEDs with a GeSn/Ge multi quantum well structure as active region show an increased direct band luminescence of GeSn by a factor of 16 compared to an intrinsic Ge LED, revealing the advantage of carrier confinement. A high density of threading dislocations, due to the lattice mismatch of Ge and Si, causes a huge drop of PL intensity in the range of one to two orders of magnitude in the temperature range from 80 to 350 K. Thin and pseudomorphically grown Ge layers between Si barrier layers exhibit a huge PL intensity due to the absence of threading dislocations. Taking into account the thickness of the active region the direct band luminescence intensity is increased by two orders of magnitude.

Terahertz quantum cascade laser with an X-valley-based injector

We present a novel terahertz (THz) quantum cascade laser (QCL) design where Γ-valley states are used for lasing transition and X-valley states—in particular, Xz-states—are used as injector subbands. Since the lasing states in our proposed structure are populated and depopulated mainly through the interface roughness assisted Γ-Xz electron scattering, we present a model to describe this intervalley carrier transport. In the injector region of the proposed THz QCL, we use a quaternary AlGaAsP material to introduce tensile strain, which plays a crucial role in increasing the gain. To compensate the strain per period, we propose to grow the periodic heterostructure on a GaAs0.94P0.06 virtual substrate. To simulate the carrier transport and hence calculate the gain and lasing performance of the proposed THz QCL, we use a simplified density matrix formalism that considers resonant tunneling, dephasing, and the important intersubband scattering mechanisms. Since electron temperature significantly varies from lattice temperature for QCLs, we take their difference into account using the kinetic energy balance method. We show that the proposed structure is capable of lasing up to a maximum lattice temperature of ∼119 K at 4.8 THz. For future improvements of the device, we identify major performance-degrading factors of the proposed design.

Metalorganic chemical vapor deposition-regrown Ga-rich InGaP films on SiGe virtual substrates for Si-based III-V optoelectronic device applications

Ga-rich InGaP materials are attractive applications for yellow-green spectral range optoelectronics such as light-emitting diodes and solar cells on silicon substrate. Bulk, Ga-rich InGaP films grown by metalorganic chemical vapor deposition on SiGe virtual substrates were investigated in the V/III compositional ratio range of 44.3–402 using chamber pressures from 100 to 200 mbar. These films were nominally lattice matched to the SiGe virtual substrate with a bandgap energy of 2.07–2.09 eV at low temperature (10 K). The authors show that the surface morphology of the Ga-rich InGaP films was dependent on the growth conditions, including the V/III gas phase ratio, pressure, and growth rate. By optimizing the growth conditions, the authors achieved improved surface morphologies of the Ga-rich InGaP films. The hillock density of the films produced using a V/III gas phase ratio of 44.3 and 75.4, a growth pressure of 100 mbar, and a growth rate of 0.9 μm/h was about an order of magnitude lower (30.3–50 × 104 cm−2) than that observed using higher V/III gas phase ratios such as 201 and 402. An increase in luminescence efficiency of Ga-rich InGaP materials was observed when the hillock density is lower. The authors discuss the mechanisms of the hillock formation.

Graphene-Mesoporous Si Nanocomposite as a Compliant Substrate for Heteroepitaxy.

The ultimate performance of a solid state device is limited by the restricted number of crystalline substrates that are available for epitaxial growth. As a result, only a small fraction of semiconductors are usable. This study describes a novel concept for a tunable compliant substrate for epitaxy, based on a graphene-porous silicon nanocomposite, which extends the range of available lattice constants for epitaxial semiconductor alloys. The presence of graphene and its effect on the strain of the porous layer lattice parameter are discussed in detail and new remarkable properties are demonstrated. These include thermal stability up to 900 °C, lattice tuning up to 0.9 % mismatch, and compliance under stress for virtual substrate thicknesses of several micrometers. A theoretical model is proposed to define the compliant substrate design rules. These advances lay the foundation for the fabrication of a compliant substrate that could unlock the lattice constant restrictions for defect-free new epitaxial semiconductor alloys and devices.

Electrically pumped continuous-wave 1.3 µm InAs/GaAs quantum dot lasers monolithically grown on on-axis Si (001) substrates.

We report on the first electrically pumped continuous-wave (cw) InAs/GaAs quantum dot (QD) lasers monolithically grown on on-axis Si (001) substrates without any intermediate buffer layers. A 400 nm antiphase boundary (APB) free epitaxial GaAs film with a small root-mean-square (RMS) surface roughness of 0.86 nm was first deposited on a 300 mm standard industry-compatible on-axis Si (001) substrate by metal-organic chemical vapor deposition (MOCVD). The QD laser structure was then grown on this APB-free GaAs/Si (001) virtual substrate by molecular beam epitaxy (MBE). Room-temperature cw lasing at ~1.3 µm has been achieved with a threshold current density of 425 A/cm2 and single facet output power of 43 mW. Under pulsed operation, lasing operation up to 102 °C has been realized, with a threshold current density of 250 A/cm2 and single facet output power exceeding 130 mW at room temperature.

Growth and Optical Properties of Direct Band Gap Ge/Ge0.87Sn0.13 Core/Shell Nanowire Arrays

Group IV semiconductor optoelectronic devices are now possible by using strain-free direct band gap GeSn alloys grown on a Ge/Si virtual substrate with Sn contents above 9%. Here, we demonstrate the growth of Ge/GeSn core/shell nanowire arrays with Sn incorporation up to 13% and without the formation of Sn clusters. The nanowire geometry promotes strain relaxation in the Ge0.87Sn0.13 shell and limits the formation of structural defects. This results in room-temperature photoluminescence centered at 0.465 eV and enhanced absorption above 98%. Therefore, direct band gap GeSn grown in a nanowire geometry holds promise as a low-cost and high-efficiency material for photodetectors operating in the short-wave infrared and thermal imaging devices.

Monolithic integration of AlGaAs distributed Bragg reflectors on virtual Ge substrates via aspect ratio trapping

High quality AlxGa1-xAs distributed Bragg reflectors (DBRs) were successfully monolithically grown on on-axis Si (100) substrates via a Ge layer formed by aspect ratio trapping (ART) technique. The GaAs/ART-Ge/Si-based DBRs have reflectivity spectra comparable to those grown on conventional bulk off-cut GaAs substrates and have smooth morphology and reasonable periodicity and uniformity. Antiphase domain formation is significantly reduced in GaAs on ART-Ge/Si substrates, and etch pit density of the GaAs base layer on the ART-Ge substrates ranges from 105 to 6 × 106 cm−2. These results paved the way for future VCSEL growth and fabrication on these ART-Ge substrates and also confirm that virtual Ge substrates via ART technique are effective Si platforms for optoelectronic integrated circuits.

Simulated characteristics of a heterojunction phototransistor with Ge1-xSnx alloy as base

Groups III-V compound semiconductors and their alloys are the main photodetecting elements for the entire fiber optic telecommunication band. However, the recent successful growth of Ge1-xSnx alloy on Ge virtual substrates on Si platform makes the group IV alloys a potential competitor. Ge1-xSnx alloy shows direct band gap and has an absorption coefficient almost 10 times higher than that of Ge. The photonic devices are complementary metal–oxide–semiconductor compatible. We have considered an n-Ge/p+-Ge1-xSnx/n-Ge1-xSnx heterojunction phototransistor (HPT) and studied the variations of terminal currents by considering the Gummel Poon model of HPT, and values of optical and current gains, photocurrent, and responsivity have been obtained. The performance of the device as a photodetector at fiber optic communication wavelengths seems quite encouraging to justify the use of GeSn-based HPTs as a replacement of III-IV semiconductor-based photodetectors.

Group IV heteroepitaxy on silicon for photonics

Abstract

Germanium-on-insulator virtual substrate for InGaP epitaxy

In this work, we investigate the bonding processes to improve Germanium-on-insulator (GOI) quality for III–V integration, and an InGaP LED has been grown and characterized on this GOI substrate. The threading dislocation density (TDD) of GOI was reduced from 5.1±0.8×108cm−2 to 4.3±0.4×107cm−2 by chemical mechanical polishing (CMP) processes. The thermal and mechanical properties of the CMPed GOI have been characterized. It showed that a 200nm thermal oxide layer effectively absorbed the hydrogen generated from the bonding by-product reactions, which avoided the formation of thermal bubbles and provided sufficient stability during high temperature epitaxy processes. After post-bonding annealing, a high bonding strength of 1720.6mJ/cm2 was achieved. Then, an AlInGaP/InGaP multi-quantum well (MQW) LED was grown on GOI substrate. Compared to LED on bulk Ge substrate, LED on GOI showed high leakage current due to the presence of high TDD in the Ge layer and the LED junctions. The electroluminescence of LED on GOI was approximately 50% of the light output of LED on bulk Ge.

Investigation of the thermal stability of metastable GeSn epitaxial layers

A stack of five elastically strained metastable GeSn layers with a thickness of 200 nm each separated by Ge spacer layers with a thickness of 20 nm is grown on a (001) Si/Ge virtual substrate. The molar fraction of Sn in the GeSn layers is 0.005, 0.034, 0.047, 0.072, and 0.10. After growth the structure is subjected to thermal annealing for 2 min at a temperature of 400°C. It is demonstrated that during the course of annealing the GeSn alloy, along with plastic relaxation, undergoes phase separation; this phase separation begins before the end of plastic relaxation. The structural degradation of the GeSn layers increases with increasing concentration of Sn accumulated on the structure surface in the form of an amorphous layer.

Design and Modeling of GeSn-Based Heterojunction Phototransistors for Communication Applications

We propose the use of Ge $_{1-x}$ Sn $_x$ heterojunction phototransistors (HPTs) as efficient optical receivers on Si substrates and analyze their performance. Our designs use n-Ge/p-Ge $_{1-x}$ Sn $_x$ /n-Ge $_{1-x}$ Sn $_x$ layers pseudomorphically grown on Si wafers via a Ge virtual substrate, which offers compatibility with complementary metal–oxide–semiconductor (CMOS) technology. By incorporating Sn into the Ge photon-absorbing layer to shrink the bandgap, the photodetection range can be significantly extended to the mid-infrared (MIR) region with a considerably enhanced optical response. The use of HPT structures provides optical conversion gain to further enhance the optical responsivity, thereby enabling efficient photodetection in the short-wave infrared region. We develop theoretical models to calculate the composition-dependent band alignments, the band structures (by taking into account the nonparabolic effect), the absorption coefficient, and the optical responsivity for the proposed GeSn HPTs. As the Sn content increases, the conduction band nonparabolicity becomes increasingly significant and considerably impacts the optical absorption coefficient. Moreover, analysis of the spectral response for the Ge $_{1-x}$ Sn $_x$ HPTs shows that efficient photodetection covering the entirety of the fiber-optic telecommunication bands, as well as the emerging 2- $\mathbf {\mu }$ m MIR communication band, can be achieved. These results indicate that the proposed Ge $_{1-x}$ Sn $_x$ HPTs are attractive for use as high-responsivity CMOS-compatible photodetectors in communication applications.

Virtual network embedding with multiple priority classes sharing substrate resources

Network virtualization is a promising approach for virtual network operators to configure their own inter-cloud networks flexibly on an inter-cloud substrate network. Virtual network operators specify multiple priority classes in order to satisfy different latency requirements for their inter-cloud network services with a variety of delay-sensitivities on their virtual networks. Furthermore, they may require substrate resource sharing among multiple priority classes in order to reduce the amount of substrate resources assigned to them. Meanwhile, it is desirable for a substrate network provider that multiple virtual networks can share substrate resources since the total amount of substrate resources required can be reduced due to the effect of statistical multiplexing. This paper formulates a novel virtual network embedding problem and proposes a heuristic virtual network embedding method to minimize the total substrate resources required when the virtual network operators request substrate resource sharing among multiple priority classes within their virtual networks. Based on the proposed method, multiple virtual networks can maximally share substrate resources with one another while sharing substrate resources on an equal basis. The effect of substrate resource sharing among multiple priority classes and multiple virtual networks is quantitatively assessed through extensive simulations, and advantageous topologies for requested virtual networks and substrate networks are also presented.

Materials design parameters for infrared device applications based on III-V semiconductors

The collaborative development of infrared detector materials by the Army Research Laboratory and Stony Brook University has led to new fundamental understandings of materials, as well as new levels of control and flexibility in III-V semiconductor crystal growth by molecular beam epitaxy. Early work on mid-wave strained layer superlattice (SLS) cameras led to a subsequent focus on minority carrier lifetime studies, which resulted in the proposal of the Ga-free SLS on GaSb substrates. The later demonstration of virtual substrate technology allowed the lattice constant to become a design parameter and enabled growth of undistorted bulk InAsSb. When grown in that manner, InAsSb has a bandgap bowing parameter large enough to cover absorption wavelengths across the entire long-wavelength band (8-12μm). Even longer wavelengths are achieved with a general Ga-free SLS approach, with a virtual substrate having a lattice constant significantly larger than that of GaSb and with InAsSb in both bi-layers in the period. Since these layers can also be made very thin, the general Ga-free SLS does not suffer from the relatively low optical absorption and poor hole transport, which is characteristic of the special Ga-free SLS on GaSb for long-wavelength designs. Finally, the general Ga-free InAsSb SLS provides a method to induce and control sustained atomic ordering, which is yet another new design parameter.

Suppression of Rotational Twin Formation in Virtual GaP/Si(111) Substrates for III–V Nanowire Growth

Planar GaP epilayers on Si(111) are considered as virtual substrates for III–V-related optoelectronic devices such as high-efficiency nanowire-based tandem absorber structures for solar energy conversion, next generation LEDs, and fast photodetectors. Rotational twin domains in such heteroepitaxial epilayers are found to strongly impede vertical nanowire growth. We investigate the twin-induced defect density and surface morphology of B-type GaP/Si(111) virtual substrates in dependence on the GaP nucleation process by metalorganic chemical vapor deposition. By employing quantitative high-resolution X-ray diffraction (HR-XRD)), scanning electron and atomic force microscopy (SEM and AFM), we reveal the significant influence of nucleation temperature and substrate miscut direction on the formation of rotational twin domains during a two-step GaP growth approach. The epilayer defect density is drastically decreased by low temperature GaP nucleation on Si(111) misoriented 3° toward [112], where rotational twi...

Room Temperature Electroluminescence from Tensile-Strained Si0.13Ge0.87/Ge Multiple Quantum Wells on a Ge Virtual Substrate.

Direct band electroluminescence (EL) from tensile-strained Si0.13Ge0.87/Ge multiple quantum wells (MQWs) on a Ge virtual substrate (VS) at room temperature is reported herein. Due to the competitive result of quantum confinement Stark effect and bandgap narrowing induced by tensile strain in Ge wells, electroluminescence from Γ1-HH1 transition in 12-nm Ge wells was observed at around 1550 nm. As injection current density increases, additional emission shoulders from Γ2-HH2 transition in Ge wells and Ge VS appeared at around 1300–1400 nm and 1600–1700 nm, respectively. The peak energy of EL shifted to the lower energy side superquadratically with an increase of injection current density as a result of the Joule heating effect. During the elevation of environmental temperature, EL intensity increased due to a reduction of energy between L and Γ valleys of Ge. Empirical fitting of the relationship between the integrated intensity of EL (L) and injection current density (J) with L~Jm shows that the m factor increased with injection current density, suggesting higher light emitting efficiency of the diode at larger injection current densities, which can be attributed to larger carrier occupations in the Γ valley and the heavy hole (HH) valance band at higher temperatures.

Room temperature direct band gap emission characteristics of surfactant mediated grown compressively strained Ge films

Compressively strained Ge films have been grown on relaxed Si0.45Ge0.55 virtual substrates using molecular beam epitaxy in the presence of Sb as a surfactant. Structural characterization has shown that films grown in the presence of surfactant exhibit very smooth surfaces with a relatively higher strain value in comparison to those grown without any surfactant. The variation of strain with increasing Ge layer thickness was analyzed using Raman spectroscopy. The strain is found to be reduced with increasing film thickness due to the onset of island nucleation following Stranski–Krastanov growth mechanism. No phonon assisted direct band gap photoluminescence from compressively strained Ge films grown on relaxed Si0.45Ge0.55 has been achieved up to room temperature. Excitation power and temperature dependent photoluminescence have been studied in details to investigate the origin of different emission sub-bands.

Investigation of the Low Temperature / High Temperature Approach to Produce Si0.5Ge0.5 and Pure Ge Strain Relaxed Buffers

Several microns thick, constant composition SiGe layers (with Ge contents typically in the 20% to 50% range) grown directly on Si(001), with sometimes thick Ge layers on top, are coming back in force as the core materials of mid and long infra-red waveguides. The impact of growth parameters and thickness on surface roughness, degree of strain relaxation and threading dislocations density (TDD) are not that well known, however. SiGe Virtual Substrates (VS), with several microns thick SiGe graded layers capped by constant composition layers or pure Ge grown directly on Si(001) are indeed preferentially used as templates for sSi layers, donors for GeOI fabrication or active media in near IR photo-detectors. We have thus explored whether or not the Low Temperature / High Temperature (LT/HT) approach (+ Thermal Cycling) used for pure Ge growth on Si yielded high quality Si0.5Ge0.5 Strain-Relaxed Buffers (SRBs) that could serve afterwards as templates for thick Ge layers. To that end, we have grown various thickness Si0.48Ge0.52 layers at 550°C, 20 Torr and with a SiH4 + GeH4 chemistry, in order to have a satisfying Growth Rate (GR = 48 nm min.-1) at such a low temperature. As soon as those layers were relaxed (88% for 380 nm), the growth temperature was increased to 850°C and Si0.50Ge0.50 layers grown on top thanks to SiH2Cl2 + GeH4 (GR = 151 nm min.-1at 20 Torr). As soon as the 1.7 µm thick Si0.5Ge0.5 SRBs were completed, a 3 x (850°C, 10s / 975°C, 10s) TC was used to minimize defect density. Then, the growth temperature was reduced to 400°C and 130 nm of pure Ge grown at 100 Torr thanks to GeH4 (GR = 17 nm min.-1). The growth temperature was then ramped up to 750°C (and the growth pressure down to 20 Torr) and various thickness Ge layers grown on top (GR = 55 nm min.-1) until 1.3 µm was reached. Finally, another 3 x (750°C, 10s / 875°C, 10s) TC was used to minimize defect density and smoothen the surface. 20 µm x 20 µm Atomic Force Microscopy (AFM) images of the surfaces of our stacks at various stages of their completion can be found in Figure 1. Omega-2Theta scans around the (004) X-Ray Diffraction order for the same samples are provided in Figure 2, together with a (004) Reciprocal Space Map of a whole {1.7 µm thick Si0.5Ge0.5 SRB / 1.3 µm Ge} stack with the 2 aforementioned TCs. What is easily seen is that the surface of the Si0.48Ge0.52 layers is rough. The spatial wavelength of that roughness increases when the Si0.50Ge0.50 HT layer thickness increases and when a TC is used. The surface morphology definitely changes when Ge is added, first at LT then at HT. Large diameter hills are then formed and a cross-hatch appears when a TC is used. We have plotted in Figure 3 the surface root mean square roughness and the macroscopic degree of strain relaxation associated with our stacks as a function of the SiGe + Ge thickness, in order to see what is happening. We have, as soon as the Si0.48Ge0.52 layers plastically relax, a surface roughening which is not recovered by the HT growth of Si0.5Ge0.5 (rms roughness: 5 nm). Adding Ge @ LT roughens the surface even more. Thickening it with Ge @ HT and using a TC yields a slight surface roughness decrease, however (down to 3.5 nm). Those roughness values are in-between those associated with cross-hatched Si0.5Ge0.5 VS (12 nm) and pure Ge layers (1 nm). What is also noticeable is that the HT Si0.5Ge0.5and pure Ge layers are slightly tensily strained. This is due to thermal expansion coefficient differences between Si and SiGe (Ge) which come into play during the cooling-down to room temperature. We have otherwise used the Ayers theory (J. Cryst. Growth 125 (1992) 329) in order to convert the full widths at half maximum of SiGe and Ge omega scans (from XRD RSMs) into actual TDDs. We would then have, for 60° misfit dislocations in our stacks, the following values: 6.0x108 cm-2 (3.5x108 cm-2) in as-grown (annealed) 1.7 µm thick Si0.5Ge0.5 SRBs and 2.8x108 cm-2 (1.6x108 cm-2) in as-grown (annealed) 1.3 µm thick Ge layers on top. Those values are definitely higher than those in 1.4 µm thick, cyclically annealed pure Ge layers grown directly on Si (3.8x107 cm-2) and in ~ 6 µm thick Si0.5Ge0.5 VS (2x105 cm-2). Plane view and cross-sectional Transmission Electron Microscopy is underway to confirm those TDDs. Figure 1

Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges

Silicon germanium (SiGe) strain relaxed buffers (SRB) have been an active area of investigation both in academia as well as the semiconductor industry for a number of years [1, 2]. These relaxed epitaxial layers act as virtual substrates or templates for subsequent growth of tensile or compressively strained layers that can serve as N and PMOS channels for continued scaling of Si CMOS technology. The most well established methodology, proposed by Fitzgerald et al. [1], for growing SiGe SRB’s is by grading the Ge concentration throughout the layer, typically 2-3 µm thick, which leads to the creation of a series of low lattice mismatched interfaces. By managing the lattice mismatch using this grading method the threading dislocation density (TDD) can be reduced significantly. In the work reported here, we have studied thick graded SRB layers from a holistic perspective that involves growth, defect density optimization followed by the growth of strained Si/SiGe layers on these virtual substrates. The focus during this study was on the high temperature growth regime (> 900 oC) which helps reduce TDD due to the higher dislocation velocity resulting in a higher number of dislocation annihilation events. Depicted in Fig. 1 is one such example, where a 2 µm graded layer (0-20 % Ge grading) was grown followed by a 1 µm layer at 20 % Ge analyzed using SIMS. The growth for this sample was carried out using Dichlorosilane (SiH2Cl2 or DCS) and Germane (GeH4) at 900 oC and 80 Torr under H2 ambient in an Applied Materials CenturaTM RP Epi reactor. From a morphology perspective these films are extremely rough after growth due to the well-known cross hatch pattern formation as shown in the AFM scan in Fig. 2 (a). In order to enable growth of strained and atomically smooth channel layers on top of this SRB, a chemical-mechanical planarization (CMP) step is required to remove the cross-hatch and leave behind a much smoother template. As shown in Fig. 2(b), Applied Materials ReflexionTM LK CMP tool was able to polish these substrates down to an RMS roughness of ~ 1.3 Å, compared to a starting RMS roughness of ~ 66 Å, after ~ 0.2 µm removal of the 20 % Ge constant composition layer. To characterize the TDD for this layer, plan view transmission electron microscopy (PV-TEM) was performed and the results are shown in Fig. 3. As seen in this case, 2 threading dislocations are visible in a 100 µm2 area which translates to a TDD of ~ 2 x 10 6 /cm2. PV-TEM however, has limited resolution and led us to explore large area defect etching utilizing vapor phase hydrochloric acid (HCl) in the epi reactor itself [3]. HCl based defect etching was done on SRB samples grown at various temperatures in the 900 – 1100 oC range after they had gone through CMP. The resulting etch pits, which in essence are highlighted threading dislocations, were inspected optically on a 300 µm2 area as shown in Table 1 where 1100 oC growth resulted in the lowest TDD ~ 5 x 10 4 /cm2. For temperatures greater than 1000 oC, GeCl4 was used instead of GeH4 in order to keep the process chamber walls clean. Another critical aspect of SRB integration is the growth of strained Si or SiGe layers on top of this relaxed layer. These strained layers serve as the channel material for N or PMOS transistors. Figure 4 represents one such illustration in the form of a cross-section TEM where we have grown a Si layer under tensile strain, 436 Å in thickness, on a 30 % Ge graded SRB layer post CMP. This Si layer appears to be defect free, and based on the (224) reciprocal space map (RSM: In Fig. 5) acquired using X-ray diffraction techniques, it is < 5 % relaxed with respect to the underlying SRB. A systematic optimization of epi pre-clean and H2 pre-bake had to be performed to achieve defect free Si or SiGe (~ 60-70 % Ge) growth on SRB templates. In summary, we have explored the growth and integration of SiGe SRB layers in order to enable scaling for future generation CMOS technology beyond 7 nm. Higher growth temperatures (> 1000 oC) were effective in improving the TDD by almost two orders of magnitude. Pseudomorphically strained N and P channel growth on SiGe SRB has also been achieved by optimizing the pre-clean and prebake conditions.

(Invited) Graphene Synthesis and Processing on Ge Substrates

Graphene is considered as a material which can enable new functionalities and performance improvements in a large variety of applications, among them in microelectronics [1, 2]. In microelectronics, techniques required for commercial large scale fabrication of graphene devices are not yet in place and further progress towards wafer-scale processing is required. Development of a wafer-scale Si technology-compatible graphene synthesis method and a toolbox of processes dedicated to handling, cleaning, patterning as well as integration of graphene with semiconductors, insulators, and metals is viewed as a prerequisite to practical applications of this material in electronic and photonic devices [3]. Semiconducting Ge surfaces appeared recently as attractive substrates for chemical vapor deposition (CVD) of graphene. There are several advantages of using them instead of metals. Firstly, the risk of metallic contaminations [4] is eliminated, ensuring the front-end-of-line compatibility in the device manufacturing process. Secondly, the thermal expansion coefficient mismatch between the Ge substrate and graphene is significantly lower than in the Cu-graphene system. This provides an opportunity to reduce the density of wrinkles which originate from thermal stress release and cause scattering of charge carriers in graphene. Furthermore, as a result of very low carbon solubility in Ge, the graphene growth on Ge can proceed, similarly to Cu substrates, in a “self-limiting” manner enabling more straightforward process control than for example on Ni. Finally, synthesis on patterned semiconducting Ge may enable direct use of graphene in some device concepts without the need of transfer which is inevitable in case of metallic substrates. In this talk, we will review the recent progress in graphene synthesis on Ge achieved by IHP and our collaborators starting from proof-of-concept molecular beam growth experiments [5], through low- [6] and high-pressure [7] CVD on Ge single crystals and Ge epi-layers on Si, to 200 mm wafer-scale CVD synthesis on Ge(100)/Si(100) virtual substrates. As an optimization approach towards improved rotational alignment of graphene on Ge [8,9] we will present results from the preparation of Ge(110)/Si(110) wafers and graphene growth on them. Beyond growth we will look at selected aspects of subsequent processing in a 200 mm Si wafer pilot line including patterning and interaction with photoresists as well as the deposition of other materials on graphene. Among the challenges ahead, re-usability of the Ge virtual substrates and wafer-scale graphene transfer procedures eliminating disadvantages of currently existing noble metal-assisted techniques [8] will be addressed. [1] A.C. Ferrari et al., “Science and technology roadmap for graphene, related two-dimensional crystals, and hybrid systems”, Nanoscale, 2015, 7, 4598-4810 [2] G. Fiori et al., “Electronics based on two-dimensional materials”, Nature Nanotechnology 2014, 9, 768–779 [3] L. Colombo et al., “Graphene growth and device integration”, IEEE Proceedings, 2013, 101, 1536-1556 [4] G. Lupina et al., “Residual metallic contamination of transferred chemical vapor deposited graphene”, ACS Nano, 2015, 9, 4776-4785 [5] G. Lippert et al., “Graphene grown on Ge(001) from atomic source”, Carbon, 2014, 75, 104-112 [6] J. Dabrowski et al., “Direct growth of low-doped graphene on Ge/Si(100) surfaces”, 2016, arXiv:1604.02315 [7] I. Pasternak et al., “Graphene growth on Ge(100)/Si(100) substrates by CVD method”, Scientific Reports, 2016, 6, 21773 [8] J.-H. Lee et al., “Wafer scale growth of single-crystal monolayer graphene on reusable hydrogen-terminated germanium”, Science, 2014, 344, 286-289 [9] B. Kiraly et al., “Electronic and mechanical properties of graphene-germanium interfaces grown by chemical vapor deposition”, Nano Lett., 2015, 15, 7414-7420