Virtual Processors Research Articles

PARALLEL MESHLESS RADIAL BASIS FUNCTION COLLOCATION METHOD FOR NEUTRON DIFFUSION PROBLEMS

The meshless global radial basis function (RBF) collocation method is widely used to model physical phenomena in science and engineering. The method produces highly accurate solutions with an exponential convergence rate. However, due to the global approximation structure of the method, dense node distributions lead to long computation times and hinder the applicability of the technique. In order to overcome this issue, this study proposes a parallel meshless global RBF collocation algorithm. The algorithm is applied to 2-D neutron diffusion problems. The multiquadric is used as the RBF. The algorithm is developed with Mathematica and eight virtual processors are used in calculations on a multicore computer with four physical cores. The method provides accurate numerical results in a stable manner. Parallel speedup increases with the number of processors up to five and seven processors for external and fission source problems, respectively. The speedup values are limited by the constrained resource sharing of the multicore computer’s memory. On the other hand, significant time savings are achieved with parallel computation. For the four-group fission source problem, when 4316 interpolation nodes are employed, the utilization of seven processors instead of sequential computation decreases the computation time of the meshless approach by 716 s.

Scheduling Parallel Real-Time Tasks on Virtual Processors

In many popular parallel programming models, e.g., OpenMP (OpenMP, 2013), applications are usually dispatched into several dedicated scheduling entities (named ”threads” in common) for which the processor time of physical platform is provided through the OS schedulers. This behavior requires for a hierarchical scheduling framework, considering each thread as a virtual processor (VP). Moreover, hierarchical scheduling allow separate applications to execute together on a common hardware platform, with each application having the “illusion” of executing on a dedicated component. However, the problem for scheduling parallel real-time tasks on virtual multiprocessor platform has not been addressed yet. An analogous approach to virtual scheduling for parallel real-time tasks is federeted scheudling, where each task exclusively executes on a set of dedicated physical processors. However, federated scheduling suffers significant resource wasting. In this article, we study the scheduling of real-time parallel task on virtual multiprocessors. As a physical processor is shared by virtual processors, tasks effectively share processors with each other. We conduct comprehensive performance evaluation to compare our proposed approach with existing methods of different types. Experiment results show that our approach consistently outperforms existing methods to a considerable extent under a wide range of parameter settings.

Comparison of Machine Learning Approaches for Missing Data Imputation Among Non-Small Cell Lung Cancer Patients

<h3>Purpose/Objective(s)</h3> Cancer registries are important sources of real-world data capturing a large number of complex data elements such as cancer stage and treatments, but the prevalence of missing data is often high. Previous research suggest missing data can identify patients within cancer registries with worse survival outcomes, potentially introducing substantial bias in studies using complete case analysis. Recent computational advances have enabled the application of machine learning (ML) imputation methods to large real-world datasets, however, the efficacy of these approaches for cancer patients is unknown. <h3>Materials/Methods</h3> We queried the National Cancer Database for non-small cell lung cancer (NSCLC) patients diagnosed in 2014 with complete data in 19 variables of known clinical and prognostic significance. Complete records were chosen given a reference value is needed to compare the efficacy of imputation techniques. We performed data preprocessing and generated synthetic missing data in 10 to 50% of records at random for each variable, then performed imputation using substitution (control) and five different ML approaches: Bayesian ridge regression under a multivariate imputation by chained equations (MICE) framework, k-nearest neighbors (KNN), matrix completion by spectral regularization (SoftImpute), iterative random forests (MissForest), and denoising autoencoders (DA). Imputation efficacy was measured by normalized root-mean-square error (RMSE) for continuous variables and proportion of falsely classified entries (PFC) for categorical variables. Algorithm runtimes were measured using a cloud computing instance with 16 virtual processors and 42 gigabytes of memory. <h3>Results</h3> We identified 50,790 NSCLC patients with complete data, each with 81 features after data preprocessing. Mean substitution for continuous variables had a RMSE of 0.091, and mode substitution for categorical variables had a PFC of 0.406. In comparison, among the tested ML methods, MICE had the lowest RMSE (best performance) for continuous variables ranging from 0.069 to 0.077 for 10 to 50% missing data, and MissForest had the lowest PFC (best performance) for categorical variables ranging from 0.251 to 0.311 for 10 to 50% missing data. Runtimes for MICE ranged from 118.9 to 267.9 seconds and for MissForest ranged from 112.0 to 186.8 seconds. KNN and DA had higher runtimes despite lower performance, while substitution runtimes were under 0.1 second for all levels of missing data. <h3>Conclusion</h3> ML methods achieved promising levels of imputation efficacy with acceptable computing runtimes for NSCLC patients within a large national cancer registry. These approaches can potentially improve clinical insights from registry data for NSLCC patients through enabling more complete cohorts incorporating ML imputed information.

Parallel Generalized Hebbian Algorithm for Large Scale Data Analytics

In order to store and analyse large amounts of data on a parallel cluster, Big Data Systems such as Hadoop and DBMSs require a complex configuration and tuning procedure. This is mostly the result of static partitioning occurring whenever data sets are imported into the file system or transferred into it. Following that, parallel processing is carried out in a distributed fashion, with the objective of achieving balanced parallel execution among nodes. The system is notoriously difficult to configure, particularly in the areas of node synchronisation, data redistribution, and distributed caching in main memory. The extended Hebbian algorithm, abbreviated as GHA, is a linear feedforward neural network model for unsupervised learning that finds the majority of its applications in principle components analysis. Sanger's rule is another name for the GHA that may be found in the academic literature. Its formulation and stability, with the additional feature that it may be used to networks that have more than one output. A unique hardware architecture for principal component analysis is presented here in the form of a paper. The Generalized Hebbian Algorithm (GHA) was chosen as the foundation for the design because to the fact that it is both straightforward and efficient. The architecture may be broken down into three distinct parts: the memory unit, the weight vector updating unit, and the primary computing unit. Within the weight vector updating unit, the computation of various synaptic weight vectors uses the same circuit in order to cut down on the area expenses. This is done in order to save space. The GHA architecture incorporates a versatile multi-computer framework that is based on mpi. Therefore, GHA may be efficiently executed on platforms that utilise either sequential processing or parallel processing. When the data set is studied for a short period of time or when a dynamic number of virtual processors is selected at runtime, we predict that our architecture will be able to profit from parallel processing on the cloud. In this research, a parallel implementation of a variety of machine learning algorithms that are built on top of the MapReduce paradigm is presented with the purpose of improving processing speed and saving time.

Assessment of Network &amp; Processor Virtualization in Cloud Computing

Cloud Computing is an emerging field in applied computer science. Cloud computing depends on virtualization, where a sole physical resource is virtualized into numerous virtual resources. Resources that are being virtualized include physical storage, processing units, volatile memories, network, and further physical resources. Processor and network virtualization offer several advantages like lessening hardware cost, energy consumption, and the human struggle for administration and management of resources. In this article, the primary concentration was on the evaluation and assessment of network virtualization between different cloud computing hypervisors and to contrast their evaluated results. This comparison is based on a few experiments performed on Citrix XenServer, Microsoft Hyper-V, and VMware vSphere hypervisors. XenServer uses Open vSwitch for its network virtualization whereas Hyper-V and vSphere use Microsoft network virtualization and vSphere switch for managing their network virtualization respectively. We have found that virtual networks are further scalable and secure than physical networks. We can assign multiple virtual interfaces or connections to a single virtual machine. In light of various experiments, in which we have compared non-virtualized with virtualized scenarios, for all these above-mentioned hypervisors, we found out that we can use virtual networks with and without VLAN Tags or VLAN Ids. Hyper-V provides further flexibility and options regarding VLAN Tag in comparison with XenServer or vSphere. We have also found that XenServer and vSphere give us extra network throughput in comparison with Hyper-V in terms of TCP and UDP whereas Round Trip Time (RTT) in the virtual network of all hypervisors are high in comparison with the non-virtual environment. Network CPU usage is also measured and found that vSphere and XenServer together consume more CPU during network activity in comparison with Hyper-V. We also found that processor virtualization did not majorly result from the average schedule time in comparison with a non-virtualized machine. We consequently conclude that in general a small reduction in the performance, in the case of virtualization is insignificant as compared with the advantages we get from virtualization when using cloud hypervisors. For the application of virtualization, this work will motivate to set up of data centers using a virtualized environment.

Cartesian Partitioning Models for 2D and 3D Parallel SpGEMM Algorithms

The focus is distributed-memory parallelization of sparse-general-matrix-multiplication (SpGEMM). Parallel SpGEMM algorithms are classified under one-dimensional (1D), 2D, and 3D categories denoting the number of dimensions by which the 3D sparse workcube representing the iteration space of SpGEMM is partitioned. Recently proposed successful 2D- and 3D-parallel SpGEMM algorithms benefit from upper bounds on communication overheads enforced by 2D and 3D cartesian partitioning of the workcube on 2D and 3D virtual processor grids, respectively. However, these methods are based on random cartesian partitioning and do not utilize sparsity patterns of SpGEMM instances for reducing the communication overheads. We propose hypergraph models for 2D and 3D cartesian partitioning of the workcube for further reducing the communication overheads of these 2D- and 3D- parallel SpGEMM algorithms. The proposed models utilize two- and three-phase partitioning that exploit multi-constraint hypergraph partitioning formulations. Extensive experimentation performed on 20 SpGEMM instances by using upto 900 processors demonstrate that proposed partitioning models significantly improve the scalability of 2D and 3D algorithms. For example, in 2D-parallel SpGEMM algorithm on 900 processors, the proposed partitioning model respectively achieves 85 and 42 percent decrease in total volume and total number of messages, leading to 1.63 times higher speedup compared to random partitioning, on average.

A Shared Satellite Ground Station Using User-Oriented Virtualization Technology

With the development of space missions, the increasing communication data volume, the diversity of mission-specific interfaces, and the growing security needs, the costs and system complexity of ground stations have increased. The architecture of the existing ground terminal is outdated and the operation and maintenance are labor-intensive, so the terminal components are unable to meet the demand of multi-satellite TT&C in the future. In this paper, a Shared Satellite Ground Station(SSGS) using user-oriented virtualization technology is proposed for coping with complex multi-satellite TT&C in the future. Based on a pool architecture, SSGS utilizes baseband processor virtualization and software-defined networking to implement resource sharing and a network that fuses high-speed and low-speed data streams with customization control. The case analysis verifies that when SSGS has a virtualization rate greater than 1, the execution rate of tasks is much larger than that of traditional ground stations. The case analysis also verifies that the virtualization rate of current commercial equipment is no less than 1.25 through equipment testing.

An efficient virtual CPU scheduling in cloud computing

In cloud computing, fine-grained virtual CPU scheduling techniques are essential in hiding physical resources from running applications and mitigating the decrease in performance upon virtualization. However, evaluating and predicting the behaviors of virtual processors is getting harder because of the diverse QoS requirements of cloud applications. In this paper, we propose a novel virtual CPU scheduling scheme to provide a high I/O performance for cloud applications. We present an evaluation function that evaluates the task characteristics of virtual machines by observing the amount of resource consumption of each virtual processor. Based on the evaluation function, the proposed scheduling scheme controls the priorities of virtual machines adaptively for fair distribution in handling I/O requests. Because our scheme evaluates both CPU-intensiveness and I/O-intensiveness of virtual machines, it provides high performance in terms of responsiveness even for various types of tasks. We implemented and experimented the proposed scheme on a virtual machine monitor. The experimental results showed that the proposed scheme increases the responsiveness and I/O bandwidth of virtual machines.

Domain‐specific virtual processors as a portable programming and execution model for parallel computational workloads on modern heterogeneous high‐performance computing architectures

AbstractWe advocate domain‐specific virtual processors (DSVP) as a portability layer for expressing and executing domain‐specific computational workloads on modern heterogeneous HPC architectures, with applications in quantum chemistry. Specifically, in this article we extend, generalize and better formalize the concept of a domain‐specific virtual processor as applied to scientific high‐performance computing. In particular, we introduce a system‐wide recursive (hierarchical) hardware encapsulation mechanism into the DSVP architecture and specify a concrete microarchitectural design of an abstract DSVP from which specialized DSVP implementations can be derived for specific scientific domains. Subsequently, we demonstrate, an example of a domain‐specific virtual processor specialized to numerical tensor algebra workloads, which is implemented in the ExaTENSOR library developed by the author with a primary focus on the quantum many‐body computational workloads on large‐scale GPU‐accelerated HPC platforms.

XIVE: External interrupt virtualization for the cloud infrastructure

In today's microprocessors, external interrupts are the only processor resource that has no full virtualization hardware support. Therefore, they create significant overhead in the form of virtual machine (VM) context switches, especially in cloud and hyperscale datacenter systems, in which the physical processors are shared by a large number of virtual processors allocated to the VMs running on the system. The IBM POWER9 processor closes this gap in the processor hardware virtualization support by introducing an eXternal Interrupt Virtualization Engine (XIVE) architecture. XIVE defines a holistic interrupt delivery mechanism that supports multiple layers of interrupt coalescing and hardware-based routing of interrupts to the correct physical thread and target level. As required, individual interrupts can thus be routed directly to a user process, to a specific supervisor or an operating system, or to the hypervisor, thereby eliminating the need for interrupt rerouting in software and minimizing the number of context switches. In addition, XIVE provides the means to automatically trigger escalation interrupts to the next higher privilege level in case the target of an interrupt is not dispatched. In this paper, we discuss the fundamental concepts of the XIVE architecture and provide an overview of the XIVE-based interrupt controller implementation of the IBM POWER9 processor.

A design flow for supporting component-based software development in multiprocessor real-time systems

Component-based software development established as an effective technique to cope with the increasing complexity of modern computing systems. In the context of real-time systems, the M-BROE framework has been recently proposed to efficiently support component-based development of real-time applications on multiprocessor platforms in the presence of shared resources. The framework relies on a two-stage approach where software components are first partitioned upon a virtual multiprocessor platform and are later integrated upon the physical platform by means of component interfaces that abstract from the internal details of the applications. This work presents a complete design flow for the M-BROE framework. Starting from a model of software components, a first method is proposed to partition applications to virtual processors and perform a synthesis of multiple component interfaces. Then, a second method is proposed to support the integration of the components by allocating virtual processors to physical processors. Both methods take resource sharing into account. Experimental results are also presented to evaluate the proposed methodology.

Design and energy-efficient resource management of virtualized networked Fog architectures for the real-time support of IoT applications

With the incoming 5G access networks, it is forecasted that Fog computing (FC) and Internet of Things (IoT) will converge onto the Fog-of-IoT paradigm. Since the FC paradigm spreads, by design, networking and computing resources over the wireless access network, it would enable the support of computing-intensive and delay-sensitive streaming applications under the energy-limited wireless IoT realm. Motivated by this consideration, the goal of this paper is threefold. First, it provides a motivating study the main “killer” application areas envisioned for the considered Fog-of-IoT paradigm. Second, it presents the design of a CoNtainer-based virtualized networked computing architecture. The proposed architecture operates at the Middleware layer and exploits the native capability of the Container Engines, so as to allow the dynamic real-time scaling of the available computing-plus-networking virtualized resources. Third, the paper presents a low-complexity penalty-aware bin packing-type heuristic for the dynamic management of the resulting virtualized computing-plus-networking resources. The proposed heuristic pursues the joint minimization of the networking-plus-computing energy by adaptively scaling up/down the processing speeds of the virtual processors and transport throughputs of the instantiated TCP/IP virtual connections, while guaranteeing hard (i.e., deterministic) upper bounds on the per-task computing-plus-networking delays. Finally, the actual energy performance-versus-implementation complexity trade-off of the proposed resource manager is numerically tested under both wireless static and mobile Fog-of-IoT scenarios and comparisons against the corresponding performances of some state-of-the-art benchmark resource managers and device-to-device edge computing platforms are also carried out.

Thermal-aware correlated two-level scheduling of real-time tasks with reduced processor energy on heterogeneous MPSoCs

Abstract With the exponential increase in power density and the relentless scaling of transistors in VLSI circuits over the past decades, modern high-performance processors fall into a predicament of high energy consumption and elevated chip temperature. Such increased energy consumption and chip temperature could induce significant economic, ecological, and technical problems. Thus, energy-efficient task scheduling with thermal consideration has become a pressing research issue in sustainable computing systems, especially for battery-powered real-time embedded systems with limited cooling techniques. This paper tackles the above challenge through scheduling tasks leveraging correlated optimizations at two different scales. Precisely, a two-level thermal-aware energy-efficient scheduling algorithm for real-time tasks on DVFS-enabled heterogeneous MPSoC systems is developed considering the constraints of task deadlines, task precedences, and chip peak temperature limit. At the processor level, a multi-processor model supporting dynamic voltage/frequency scaling is transformed to a virtual multi-processor model supporting only one fixed frequency level. At the core level, real-time tasks are assigned to individual cores of the virtual processor under the constraints of task precedence and peak temperature limit. Through nicely interleaving optimizations at both levels, high quality task scheduling solutions can be computed efficiently. Extensive simulations of synthetic real-time tasks and real-life benchmarks are performed to validate the proposed algorithm. Experimental results demonstrate the effectiveness of the proposed algorithm as compared to the benchmarking schemes.

A Hardware Implementation of the Levinson Routine in a Radio Detector of Cosmic Rays to Improve a Suppression of the Nonstationary RFI

The radio detector system for ultrahigh-energy cosmic rays in the Pierre Auger Observatory operates in the frequency range 30–80 MHz, which is often contaminated by human-made radio-frequency interferences (RFIs). Several filters were used to suppress the RFI: based on the FFT, an IIR notch filter, and an FIR filter based on the linear prediction. The last refreshes the FIR coefficients calculating either in the external ARM processor, internal soft-core NIOS processor implemented inside the field programmable gate aray (FPGA), or hard-core embedded processors [based on Integrated ARM Cortex-A9800 MHz Hardcore Processor System (HPS)] being a silicon part of the FPGA chip. Refreshment times significantly depend on the type of calculation process. For a stationary RFI, the FIR coefficients can be refreshed each minute or rarer. However, an efficient suppression of nonstationary short-term contaminations requires a much faster response. Calculations of FIR coefficients in an external Voipac PXA270M ARM processor take 1–2 s, by the soft-core virtual NIOS processor on the level of hundreds of milliseconds. The HPS allows a reduction of the refreshment time to ~20 ms (for a 32-stage FIR filter). A symmetry of covariance matrix allows one to use the much faster Levinson procedure instead of typical Gauss routine for solving a set of linear equations of time. A hardware implementation of this procedure inside the FPGA fabric as a specialized $\mu \text{C}$ (with 100-MHz clock) requires only ~53 800 clock cycles. We used 64- or 48-b floating-point representations to calculate FIR coefficients. Resources occupation is relatively high, as the design was optimized for a maximal register performance. However, the RFI suppression is very efficient. We expect a significant suppression of even a short-term nonstationary RFI.

Adaptive IIR-Notch Filter for RFI Suppression in a Radio Detection of Cosmic Rays

Radio stations can observe radio signals caused by coherent emissions due to geomagnetic radiation and charge excess processes mainly in the frequency band from 30 to 80 MHz. This range is highly contaminated by human-made radio frequency interference (RFI). In order to improve the signal-to-noise ratio, RFI filters are used to suppress this contamination. Infinite impulse response (IIR)-notch filters operate with fixed parameters and suppress several narrow bands. IIR filters are generally potentially unstable due to feedbacks; however, they are much shorter and more power efficient than finite impulse response filters. We implemented an NIOS virtual processor calculating new set of IIR filter coefficients, which are reloaded dynamically on-the-fly. Spectrum analysis of the 30–80-MHz band can also be supported by the Altera IP Cores. The NIOS adjusts the new coefficients of the filter checking whether the poles are inside the unique complex radius (a condition of stability) as well as tuning the width of the notch filter. Practical implementation was tested in the laboratory with signal and pattern generators. Laboratory results are very promising. The IIR filter follows the drifting frequencies over very wide ranges (even 15 MHz for investigated range of 30–80 MHz), keeping a suppression factor on a very high level (≥10). The novelty of this paper is an introduction of the adaptive IIR-notch filter, which has not been used in any previous experiment.

An Embedded System for a High-Speed Manipulator With Single Time Scale Visual Servoing

This study presents the development of an embedded system for controlling a high-speed robotic manipulator. Three different types of controllers including hardware proportional derivative (PD), software PD, and single time scale visual servoing are considered in this study. Novel field programmable gate array (FPGA) technology was used for implementing the embedded system for faster execution speeds and parallelism. It is comprised of dedicated hardware and software modules for obtaining sensor feedback and control signal (CT) estimation, providing the control signal to the servovalves. A NIOS II virtual soft processor system was configured in the FPGA for implementing functions that are computationally expensive and difficult to implement in hardware. Quadrature decoding, serial peripheral interface (SPI) input and output modules, and control signal estimation in some cases was carried out using the dedicated hardware modules. The experiments show that the proposed controller performed satisfactory control of the end effector position. It performed single time scale visual servoing with control signal updates at 330 Hz to control the end effector trajectory at speeds of up to 0.8 ms−1. The FPGA technology also provided a more compact single chip implementation of the controller.

VAED: VMI‐assisted evasion detection approach for infrastructure as a service cloud

SummaryCloud computing provides on demand provisioning of resources mostly offered as Infrastructure as a Service. The flexibility in services has opened doors for attackers. Research has been performed to detect various malware in the last few years. However, modern malware are advanced enough to detect the presence of virtualization environment, security analyzer, or even the hypervisor by observing the virtualization‐specific information such as virtual processor features, timing features, etc. The malware exhibit evasive nature and can fool existing security solutions by performing modern antidetection tactics. In this paper, we propose an approach named as VMI‐assisted evasion detection (VAED), deployed at virtual machine monitor, to detect the evasion‐based malware attacks. The VAED is based on learning the program semantic of evasive malware. It uses system call dependency graph approach generated using Markov Chain principle and keeps track of system call ordering with transition probability distribution between each pair system calls. It uses software break point injection technique to extract the system call traces of evasive malware samples, which is free from any modification in hardware‐specific values. Hence, it is secure from evasion attempts. The VAED is validated over evasive samples collected from the University of California on request, and results seem to be promising.

A SystemC Based Framework for Cycle Accurate Processor Simulation and Parameter Analysis

Abstract: The development of new domain specific microprocessors architectures is a very complex task. Hardware designers are confronted with several hundred design parameters (e.g. cache size, ALU operation, etc.) which can be combined in a nearly arbitrary way to develop new architectures. Often these parameters are guessed by the designer or best practice is used to find an apparently good parameter set. The utilization of virtual hardware can be one solution to solve this problem. Different parameter sets can be evaluated inside a simulation environment, without the need for designing any real hardware. Unfortunately, most virtual hardware simulators are either to inflexible or not accurate enough to get valuable results. Therefore, this paper presents a SystemC based framework, which enables the construction of highly parameterizable virtual hardware processor models, directed at parameter analysis. The structure and working principle of two exemplary processors are showcasing the use of this framework. A presentation of how different parameter sets impact the programs execution time and power consumption of the processor will be given, as a result of the virtual hardwares execution.

Cache-aware compositional analysis of real-time multicore virtualization platforms

Multicore processors are becoming ubiquitous, and it is becoming increasingly common to run multiple real-time systems on a shared multicore platform. While this trend helps to reduce cost and to increase performance, it also makes it more challenging to achieve timing guarantees and functional isolation. One approach to achieving functional isolation is to use virtualization. However, virtualization also introduces many challenges to the multicore timing analysis; for instance, the overhead due to cache misses becomes harder to predict, since it depends not only on the direct interference between tasks but also on the indirect interference between virtual processors and the tasks executing on them. In this paper, we present a cache-aware compositional analysis technique that can be used to ensure timing guarantees of components scheduled on a multicore virtualization platform. Our technique improves on previous multicore compositional analyses by accounting for the cache-related overhead in the components' interfaces, and it addresses the new virtualization-specific challenges in the overhead analysis. To demonstrate the utility of our technique, we report results from an extensive evaluation based on randomly generated workloads.

Power-efficient assignment of virtual machines to physical machines

Motivated by current trends in cloud computing, we study a version of the generalized assignment problem where a set of virtual processors has to be implemented by a set of identical processors. For literature consistency, we say that a set of virtual machines (VMs) is assigned to a set of physical machines (PMs). The optimization criterion is to minimize the power consumed by all the PMs. We term the problem Virtual Machine Assignment (VMA). Crucial differences with previous work include a variable number of PMs, that each VM must be assigned to exactly one PM (i.e., VMs cannot be implemented fractionally), and a minimum power consumption for each active PM. Such infrastructure may be strictly constrained in the number of PMs or in the PMs’ capacity, depending on how costly (in terms of power consumption) it is to add a new PM to the system or to heavily load some of the existing PMs. Low usage or ample budget yields models where PM capacity and/or the number of PMs may be assumed unbounded for all practical purposes. We study four VMA problems depending on whether the capacity or the number of PMs is bounded or not. Specifically, we study hardness and online competitiveness for a variety of cases. To the best of our knowledge, this is the first comprehensive study of the VMA problem for this cost function.