Virtual Processors Research Articles

Distribution of Operations and Data Arrays over Processors

For algorithms described by loop nests, a method of construction of affine mappings of operations and data arrays onto virtual processors is suggested. Only local communications between the processors are required; in particular, there may be no communications at all. The method makes it possible to find many heuristic solutions, allows for dependence on outer loop indices, and can be used for automated parallelizing sequential programs.

Mapping of Affine Loop Nests onto Independent Processors

A method is given for obtaining independent parts of algorithms, represented by affine loop nests (not necessary perfectly nested). The method is based on a modular affine mapping of algorithm operations onto independent virtual processors. The method can select more independent computations than the known procedures based on affine mappings.

Lesser Bear: A lightweight process library for SMP computers—scheduling mechanism without a lock operation

AbstractWe have designed and implemented a lightweight process (thread) library called ‘Lesser Bear’ for SMP computers. Lesser Bear has thread‐level parallelism and high portability. Lesser Bear executes threads in parallel by creating UNIX processes as virtual processors and a memory‐mapped file as a huge shared‐memory space. To schedule thread in parallel, the shared‐memory space has been divided into working spaces for each virtual processor, and a ready queue has been distributed.However the previous version of Lesser Bear sometimes requires a lock operation for dequeueing. We therefore proposed a scheduling mechanism that does not require a lock operation. To achieve this, each divided space forms a link topology through the queues, and we use a lock‐free algorithm for the queue operation. This mechanism is applied to Lesser Bear and evaluated by experimental results. Copyright © 2002 John Wiley & Sons, Ltd.

The Rationale for Distributed Semantics as a Topology Independent Embedded Systems Design Methodology and its Implementation in the Virtuoso RTOS

Virtuoso VSP is a fully distributed real-time operating system originally developed on the Inmos transputer. Its generic architecture is based on a small but very fast nanokernel and a portable preemptive microkernel. It was further on ported in single and virtual single processor implementations to a wide range of processors. This paper describes the rationale for developing the distributed semantics of Virtuoso's microkernel and describes some of the implementation issues. The analysis is based on the parallel DSP implementations as these push the performance limits most for hard real-time applications. Extensions of the model towards heterogeneous embedded target systems are discussed.

Lesser Bear—a light‐weight process library for SMP computers

AbstractWe have designed and implemented a light‐weight process (thread) library called ‘Lesser Bear’ for SMP computers. Lesser Bear has high portability and thread‐level parallelism. Creating UNIX processes as virtual processors and a memory‐mapped file as a huge shared‐memory space enables Lesser Bear to execute threads in parallel. Lesser Bear requires exclusive operation between peer virtual processors, and treats a shared‐memory space as a critical section for synchronization of threads. Therefore, thread functions of the previous Lesser Bear are serialized. In this paper, we present a scheduling mechanism to execute thread functions in parallel. In the design of the proposed mechanism, we divide the entire shared‐memory space into partial spaces for virtual processors, and prepare two queues (Protect Queue and Waiver Queue) for each partial space. We adopt an algorithm in which lock operations are not necessary for enqueueing. This algorithm allows us to propose a scheduling mechanism that can reduce the scheduling overhead. The mechanism is applied to Lesser Bear and evaluated by experimental results. Copyright © 2001 John Wiley & Sons, Ltd.

Performance evaluation of heterogeneous systems

This paper presents an investigation into the development of performance metrics for heterogeneous systems. General measures of speedup for sequential and parallel architectures are proposed. Speedup and efficiency are defined using the concept of virtual processor. These are utilised to obtain an efficient strategy for task to processor allocation achieving an efficiency near its maximum possible value. The performance metrics developed are considered general and accordingly are applicable to both heterogeneous and homogeneous architectures. Moreover, the metrics ensure that capabilities of the processors are exploited by maximising the efficiency of the architecture. The proposed concepts are validated experimentally using several algorithms and architectures.

The massively parallel genetic algorithm for RNA folding: MIMD implementation and population variation.

A massively parallel Genetic Algorithm (GA) has been applied to RNA sequence folding on three different computer architectures. The GA, an evolution-like algorithm that is applied to a large population of RNA structures based on a pool of helical stems derived from an RNA sequence, evolves this population in parallel. The algorithm was originally designed and developed for a 16384 processor SIMD (Single Instruction Multiple Data) MasPar MP-2. More recently it has been adapted to a 64 processor MIMD (Multiple Instruction Multiple Data) SGI ORIGIN 2000, and a 512 processor MIMD CRAY T3E. The MIMD version of the algorithm raises issues concerning RNA structure data-layout and processor communication. In addition, the effects of population variation on the predicted results are discussed. Also presented are the scaling properties of the algorithm from the perspective of the number of physical processors utilized and the number of virtual processors (RNA structures) operated upon.

Interfacing MATLAB with a parallel virtual processor for matrix algorithms

This paper describes the results of a project to interface MATLAB with a parallel virtual processor (PVP) that allows execution of matrix operations in MATLAB on a set of computers connected by a network. The software, a connection-oriented BSD socket-based client–server model, automatically partitions a MATLAB problem and delegates work to server processes running on separate remote machines. Experimental data on the matrix multiply operation shows that the speed improvement of the parallel implementation over the single-processor MATLAB algorithm depends on the size of the matrices, the number of processes, the speed of the processors, and the speed of the network connection. In particular, the advantage of doing matrix multiply in parallel increases as the size of the matrices increase. A speedup of 2.95 times was achieved in multiplying 2048 by 2048 square matrices using 15 workstations. The algorithm was also implemented on a network of four PC's, which was up to 2.5 times as fast as four workstations. The study also showed that there is an optimal number of processes for a particular problem, and so using more processes is not always faster.

Mapping strategies in data parallel programming models; the projection methods

We Analyze data parallel programming of some general purpose methods in linear algebra. Specifically, the projection methods to solve very large linear system and/or eigenproblem. The expensive parts of these methods are their projection phases. This portion of these algorithms has generally, a very simple structure for such a programming model. It is composed essentially of matrix-vector multiplications and inner-products. Then, we simply need to find a good data distribution in order to obtain a well adapted communication pattern and not loose too much storage space. We begin with a survey of data parallel behavior of some projection methods such as Arnoldi, GMRES, Lanczos, PRR,... After analyzing some methods of data mapping onto virtual processors we point out that for a fixed number of physical processors, the performances are a function of the mapping method. We will see also that the maximum size of the problems which can be solved on the architectures supporting the data parallel programming model is a function of the data mapping method. In conclusion we present the performances obtained on a Connection Machine 5 (CM5).

POTENTIAL: A highly adaptive core of parallel database system

POTENTIAL is a virtual database machine based on general computing platforms, especially parallel computing platforms. It provides a complete solution to high-performance database systems by a ‘virtual processor+virtual data bus+virtual memory’ architecture. Virtual processors manage all CPU resources in the system, on which various operations are running. Virtual data bus is responsible for the management of data transmission between associated operations, which forms the hinges of the entire system. Virtual memory provides efficient data storage and buffering mechanisms that conform to data reference behaviors in database systems. The architecture of POTENTIAL is very clear and has many good features, including high efficiency, high scalability, high extensibility, high portability, etc.

Virtual Processors: Migrating object-clusters unify concurrency and distribution

Concurrent and distributed software systems are currently very distinct in their usage and programming. In the case of Java the first requires threads, the latter RMI, CORBA, Voyager etc. However, they are tightly related and often cited in one breat

A new parallel model for the analysis of asynchronous algorithms

The BSP model barrier synchronization imposes some limits both in the range of available algorithms and also in their performance. Although BSP programs can be translated to MPI/PVM programs, the counterpart is not true. The asynchronous nature of some MPI/PVM programs does not easily fit inside the BSP model. Through the suppression of barriers and the generalization of the concept of superstep we propose two new models, the BSP-like and the BSP without barriers (BSPWB) models. While the BSP-like extends the BSP* model to programs written using collective operations, the more general BSPWB model admits the MPI/PVM parallel asynchronous programming style. The parameters of the models and their quality are evaluated on four standard parallel platforms: the CRAY T3E, the IBM SP2, the Origin 2000 and the Digital Alpha Server 8400. The study shows that the time spent in an h-relation is more independent on the number of processors than on the communication pattern. We illustrate the use of these BSP extensions through two problem-solving paradigms: the Nested Parallel Recursive Divide and Conquer Paradigm and the Virtual Pipeline Dynamic Programming Paradigm. The proposed paradigms explain how nested parallelism and processor virtualization can be introduced in MPI and PVM without having any negative impact in the performance and model accuracy. The prediction of the communication times is robust even for problems, where communication is dominated by small messages.

The Jalapeño virtual machine

Jalapeño is a virtual machine for Java™ servers written in the Java language. To be able to address the requirements of servers (performance and scalability in particular), Jalapeño was designed “from scratch“ to be as self-sufficient as possible. Jalapeño's unique object model and memory layout allows a hardware null-pointer check as well as fast access to array elements, fields, and methods. Run-time services conventionally provided in native code are implemented primarily in Java. Java threads are multiplexed by virtual processors (implemented as operating system threads). A family of concurrent object allocators and parallel type-accurate garbage collectors is supported. Jalapeño's interoperable compilers enable quasi-preemptive thread switching and precise location of object references. Jalapeño's dynamic optimizing compiler is designed to obtain high quality code for methods that are observed to be frequently executed or computationally intensive.

Method to simulate the acoustical quality of a room and associated audio-digital processor

A method for the simulation of the acoustical quality produced by a virtual sound source and for the localizing of this source with respect to one or more listeners, and one or more original sound sources. This method consists in: 1) fixing values of perceptual parameters defining the acoustical quality to be simulated and values of parameters defining the localization of a virtual source, 2) converting these values into a pulse response described by its energy distribution as a function of the time and the frequency, 3) carrying out a context compensation so as to take account of an existing room effect, 4) obtaining an artificial reverberation from elementary signals so as to achieve a virtual acoustic environment in real time and control the localizing of the virtual source. This method can be used to modify sound signals coming from a real source, or to create sound effects on recording media. An acoustic virtual processor which enables implementation of this method comprises a signal processing "room" module that enables the obtaining of an artificial reverberation and a signal processing "pan" module enabling the controlling of the localization and the movement of the sound source and that carries out a format conversion into another reproduction mode. The acoustic virtual processor can be used to fit out all types of entertainment halls or games halls.

Parallelism and recursion in message passing libraries: an efficient methodology

Nested parallelism appears naturally in many applications. It is required whenever a function performing parallel statements needs to call a subroutine using parallelism. A particular case occurs when the function is recursive. Nested parallelism is to parallel programming as basic as nested loops to sequential programming. Despite this, most existing parallel languages do not provide this feature. This paper presents a new methodology to expand message passing libraries (MPL) with nested parallelism. The tool to support the methodology has processor virtualization, load balancing, pipeline parallelism and collective operations, among other features. The computational results prove that the performance obtained is comparable to that obtained using classical message passing programs. Since the methodology does not force the programmer to leave the MPL environment, all the efficiency and portability of the MPL model is preserved. Copyright © 1999 John Wiley & Sons, Ltd.

Effects of multithreading on cache performance

As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question, however, remains as to how effective multithreading is on tolerating memory latency. The performance of multithreading is not only affected by the overlapping of memory latency with useful computation, but also strongly depends on the cache behavior and the overhead of multithreading (e.g., thread management and context-switch costs). In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion. To study these issues, this paper presents the Multithreaded Virtual Processor (MVP) model. MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling. Our studies with MVP show that, in general, the performance improvements are obtained not only by tolerating memory latency but also lower cache miss rates due to exploitation of data locality. However, multithreading creates an additional stress on the memory hierarchy caused by the interference among threads. Also, the dynamic behavior of multithreaded execution hinders the instruction locality that results in a high number of misses in the L1 instruction cache.

Design and implementation of a parallel cellular language for MIMD architectures

In this paper we present a new language, called ParCeL-1, intended to make easier the implementation of computation-intensive and artificial intelligence applications on highly parallel MIMD architectures. The computational model of ParCeL-1 is object-oriented and synchronous, based on virtual processors called cells that compute and communicate alternately. The current prototype is implemented on several multi-processor systems (Cray T3D, Intel Paragon, Telmat T-Node, workstation networks using PVM, and SGI Power Challenge Array). Several applications written in ParCeL-1 are described, together with their performances obtained on a 256-processor Cray T3D.

A parallel algorithm for gradient training of feedforward neural networks

This paper presents a message-passing architecture simulating multilayer neural networks, adjusting its weights for each pair, consisting of an input vector and a desired output vector. First, the multilayer neural network is defined, and the difficulties arising from parallel implementation are clarified using Petri nets. Then the implementation of a neuron, split into the synapse and body, is proposed by arranging virtual processors in a cascaded torus topology. Mapping virtual processors onto node processors is done with the intention of minimizing external communication. Then, internal communication is reduced and implementation on a physical message-passing architecture is given. A time complexity analysis arises from the algorithm specification and some simplifying assumptions. Theoretical results are compared with experimental ones measured on a transputer based machine. Finally the algorithm based on the splitting operation is compared with a classical one.

Scalable lossless compression algorithm for motion pictures

Lossless JPEG is inherently a sequential algorithm. In order to achieve real-time encoding/decoding of lossless JPEG for motion pictures, it should be parallelized. We show the parallelized version of lossless JPEG and the allocation of virtual processors. We also describe the preliminary performance prediction of the algorithm to confirm the possibility of the real-time processing.

Design and implementation of a Parallel Pthread Library (PPL) with parallelism and portability

Although multi thread libraries have been implemented to provide threads—a unit of concurrent/parallel execution—at user level, there is no thread library that provides both parallelism and portability. We designed and implemented the PPL (Parallel Pthread Library) with the following two requirements in mind: (1) It should permit parallel execution according to the system, and (2) it should provide a common thread environment for many operating systems and be highly portable. We employed a multi-routine approach to realize parallelism, separating the internal structure of PPL into two parts to expedite portability: namely, a virtual processor dependent module and a virtual processor-independent module. We implemented PPL in several systems and compared its performance with other user-level threads. Furthermore, we evaluated parallelism in multi-processor systems. The results show that PPL has sufficient portability and parallelism. © 1998 Scripta Technica. Syst Comp Jpn, 29(2): 28–35, 1998