Virtual Memory Support Research Articles

Design tradeoffs for software-managed TLBs

An increasing number of architectures provide virtual memory support through software-managed TLBs. However, software management can impose considerable penalties that are highly dependent on the operating system's structure and its use of virtual memory. This work explores software-managed TLB design tradeoffs and their interaction with a range of monolithic and microkernel operating systems. Through hardware monitoring and simulation, we explore TLB performance for benchmarks running on a MIPS R2000-based workstation running Ultrix, OSF/1, and three versions of Mach 3.0.

Design tradeoffs for software-managed TLBs

An increasing number of architectures provide virtual memory support through software-managed TLBs. However, software management can impose considerable penalties, which are highly dependent on the operating system's structure and its use of virtual memory. This work explores software-managed TLB design tradeoffs and their interaction with a range of operating systems including monolithic and microkernel designs. Through hardware monitoring and simulations, we explore TLB performance for benchmarks running on a MIPS R2000-based workstation running Ultrix, OSF/1, and three versions of mach 3.0. Results: New operating systems are changing the relative frequency of different types of TLB misses, some of which may not be efficiently handled by current architectures. For the same application binaries, total TLB service time varies by as much as an order of magnitude under different operating systems. Reducing the handling cost for kernel TLB misses reduces total TLB service time up to 40%. For TLBs between 32 and 128 slots, each doubling of the TLB size reduces total TLB service time up to 50%.

Microprocessor memory management units

This tutorial describes the current crop of commercial memory management units (MMUs) for 32-bit microprocessors. The discussion includes both complex- and reduced-instruction-set computers (CISCs and RISCs). The rationale, principles, and issues related to hardware support for memory management and virtual memory are reviewed. The design and features of high-end microprocessor MMUs are reviewed and compared with respect to a common set of criteria. Special attention is paid to Unix requirements and multiprocessor, multiple MMU considerations. The MMUs covered are Intel 80386, i486, and i860; Motorola's 68851 (MMU for the 68020), 68030, 68040, and 88200 (MMU for the 88000 series); the Fujitsu MB86920 (Sparc MMU); and the MIPS R2000/R3000.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The advantages of RISC architectures

Reduced Instruction Set Computers (RISCs) offer more performance per transistor than conventional Complex Instruction Set Computers (CISCs). There are now many examples of this advantage being exploited in the design of processors for high-end engineering workstations, where the RISC approach allows greater performance to be extracted from a single integrated circuit than could be obtained from a CISC processor based on the same silicon technology. Acorn has used the inherent advantage of RISC technology in a different way. The RISC approach allows 32 bit processing power to be offered at much lower cost than was possible with a CISC, because of the smaller die size required to implement the processor. The availability of this power allows system functionality to be moved from hardware to software, which in turn simplifies the support chips and further reduces system cost. A complete RISC system has been designed to partition efficiently onto four custom chips. The chipset combines with standard memory devices to deliver superminicomputer processing performance, with full support for multi-tasking and virtual memory, at a similar silicon cost to standard PC.

The status of manip - a multicomputer architecture for solving, combinatorial extremum-search problems

In this paper, we report the status of study on MANIP, a parallel computer for solving combinatorial extremum-search problems. The most general technique that can be used to solve a wide variety of these problems on a uniprocessor system, optimally or sub-optimally, is the branch-and-bound algorithm. We have adapted and extended branch-and-bound algorithms with lower-bound tests for parallel processing. Three major problems are identified in the design: interconnection networks for supporting the selection of subproblems, anomalies in parallelism and virtual-memory support. A unidirectional ring network has been shown to be the most cost-effective selection network. We provide sufficient conditions so that anomalies can be eliminated under certain conditions and show that anomalies are unavoidable otherwise. Lastly, we develop a modified branch-and-bound algorithm so that the amount of memory space required under a best-first search is significantly reduced.

Virtual Memory and the MC68010

The designers of this microprocessor used the continuation method to provide an elegant general solution to the problem of virtual memory support.

A 32-bit microprocessor with virtual memory support

THIS PAPER will discuss a 32b microprocessor implemented on a 290mil square chip containing approximately 60K transistors. The processor* is the first of a family of 16/32b microprocessor components. The device supports software transparent extensions of the basic instruction set through the use of slave processor chips. One such slave processor, a memory management unit, added to the processor will implement a demand paged virtual memory system. The basic instruction set contains 82 instructions supporting operations on 8, 16 and 32b integers, strings, packed decimal, bit/bitfields, arrays and high level program control constructs.

A verifiable protection system

This paper reports on the design and implementation of the UCLA Virtual Machine System, a multiuser operating system base that has been developed to provide ultra high reliability protection and security. Details are presented of the UCLA-VM system, a prototype of which now exists. Concepts which have influenced its structure are discussed, including program verification, security kernels, virtual machines, virtual memory, and the need for flexible information sharing facilities. A new mechanism, capability faulting, is developed in order to remove much of the virtual memory support from the security kernel. Flexible, reliable control of sharing is obtained by extensions to several of these concepts, especially through the use of levels of kernels.