Virtex-5 FPGA Research Articles

Ultrasound Kidney Images with IKNN-Dependent FPGA Abnormality Classification

Ultrasound imaging is commonly used to diagnose internal anomalies. Imaging for abnormality detection is a challenging process in today’s world. Even though there is an advancement in technology, tele-radiographers face difficulty in the accurate diagnosis of abnormalities. In order to resolve this issue, tele-radiology has paved a new way for doctors around the world to access the Internet to share the radiological images from one location to another. But frequent online access is one of the bottleneck issues. In order to overcome this drawback, Computer Assisted Diagnosis (CAD) is preferred in this proposed study and it uses VIRTEX-6 FPGA to clearly identify abnormality in the platform and also manual control is minimized in this condition. The proposed algorithm includes five steps: pre-processing, segmentation, feature extraction, selection and classification. The classification is performed using the Iterative K-Nearest Neighbor (IKNN) classifier based on the selected features. Unlike popular KNN, the proposed IKNN algorithm performs the similarity measurement on selective neighbors for a number of times where the number of neighbors has been dynamically selected at each iteration. Also, at each iteration, the method would select a subset of features in a random way. For the features selected and with the neighbors selected, the method computes the similarity value of Hist-sim which is being measured according to the features selected from the histogram features where the method computes the Haralick similarity with the features selected from the Haralick features. Using the features selected, the method computes the value of cumulative class drive similarity (CCDS). At each iteration the class with maximum similarity is selected and finally, the class being selected for the most number of times is selected as a result of classification. This improves the performance of classification. While comparing with the existing algorithms such as Support Vector Machine (SVM) with the linear, Radial Basis Function (RBF) and polynomial kernels, greater accuracy is achieved via IKNN classification. The specificity is found to be 95, 80 and 75 for normal, cystic and stone kidneys.

Design and Implementation of Real-Time Image Acquisition Chip Based on Triple-Hybrid Encryption System

With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4 μm2. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm2.

A post-quantum lattice based lightweight authentication and code-based hybrid encryption scheme for IoT devices

The Internet of Things (IoT) introduces an active connection between smart devices for revolutionizing our modern lives in this world. But, IoT devices often exhibit several security issues, so transmission between the nodes should be protected using cryptographic approaches. However, the complexity of conventional cryptographic approaches is very high and is vulnerable to quantum attacks. This paper presents a robust and lightweight post-quantum lattice-based authentication and code-based hybrid encryption scheme for resource-constrained IoT devices. The proposed Ring-Learning with Errors (Ring-LWE) based authentication scheme introduces Bernstein reconstruction in polynomial multiplication to achieve minimal computation cost; hence, resource-limited IoT devices are viable to use the reliable authentication mutually. This approach offers indefinite identity privacy and location privacy. Hence, the proposed signature generation and verification process are highly efficient compared to the existing ring signature systems. Also, the proposed post-quantum hybrid code-based encryption scheme follows Diagonal Structure Based QC‑LDPC Codes with column loop optimization and Simplified Log Domain Sum-Product Algorithm (SLDSPA) to provide the function of light weight encryption with minimum hardware requirements. The total authentication delay of the proposed authentication scheme is 23% less than the authentication scheme that is considered conventional polynomial multiplication. Also, the optimized design of the proposed code based HE uses only 64 slices and 640 slices on Xilinx Virtex-6 FPGA for encoding and decoding processes, respectively. These simulation results prove the effectiveness of the proposed cryptographic scheme against other competitive systems in terms of its functionality and hardware complexities.

Lightweight Architecture for Elliptic Curve Scalar Multiplication over Prime Field

In this paper, we present a novel lightweight elliptic curve scalar multiplication architecture for random Weierstrass curves over prime field Fp. The elliptic curve scalar multiplication is executed in Jacobian coordinates based on the Montgomery ladder algorithm with (X,Y)-only common Z coordinate arithmetic. At the finite field operation level, the adder-based modular multiplier and modular divider are optimized by the pre-calculation method to reduce the critical path while maintaining low resource consumption. At the group operation level, the point addition and point doubling methods in (X,Y)-only common Z coordinate arithmetic are modified to improve computation parallelism. A compact scheduling method is presented to improve the architecture’s performance, which includes appropriate scheduling of finite field operations and specific register connections. Compared with existing works, our design is implemented on the FPGA platform without using DSPs or BRAMs for higher portability. It utilizes 6.4~6.5k slices in Kintex-7, Virtex-7, and ZYNQ FPGA and executes an elliptic curve scalar multiplication for a field size of 256-bit in 1.73 ms, 1.70 ms, and 1.80 ms, respectively. Additionally, our design is resistant to timing attacks, simple power analysis attacks, and safe-error attacks. This architecture outperforms most state-of-the-art lightweight designs in terms of area-time products.

A Fault Clearance and Restoration Approach for MMC-Based MTDC Grid

With the growth in continuous energy demand, high-voltage Multi-Terminal DC (MTDC) systems are technically and economically feasible to transmit bulk power and integrate additional energy sources. However, the high vulnerability of the MTDC systems to DC faults, especially pole-to-pole (P2P) faults, is technically challenging. The development of DC fault ride-through techniques such as DC circuit breakers is still challenging due to their high cost and complex operation. This paper presents the DC fault clearance and isolation method for an MMC-based MTDC grid without adopting the high-cost DC circuit breakers. Besides, a restoration sequence is proposed to re-energize the DC grid upon clearing the fault. An MMC-based four-terminal DC grid is implemented in a Control-Hardware-in-Loop (CHIL) environment based on Xilinx Virtex-7 FPGAs and Real-Time Digital Simulator (RTDS). The RTDS results show that the MTDC system satisfactorily rides through DC faults and can safely recover after DC faults.

ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation

Fully homomorphic encryption (FHE) allows arbitrary computation on encrypted data and thus has potential in privacy-preserving computing. However, efficiency is still the bottleneck. In this paper we present an area-efficient and highly unified reconfigurable multi-core architecture (named ReMCA) for full Residue Number System (RNS) variant of Fan-Vercauteren variant of Brakerski’s scheme (RNS-BFV), which employs a variable number of reconfigurable processing elements (PEs) and RNS channels. The PE unit can be flexibly configured as NTT, INTT or modular multiplier, thereby avoiding the need of other extra computational units. To reduce the computational complexity, ReMCA merges the pre/post-processing into NTT/INTT and unifies the read/write structure of NTT and INTT. Also, a conflict-free memory access pattern that doesn’t need separate bit-reversal operation is proposed to optimize the memory access. Furthermore, targeting different computational requirements, a unified hardware architecture mapping model and data memory organization model are introduced, and all the computing units that RNS-BFV involved are optimized and mapped on ReMCA. ReMCA is evaluated on a Xilinx Virtex-7 FPGA platform. Running at 250MHz, it can perform 2260 homomorphic multiplication per second. When normalized to the same parameter set, the throughput and Area-Time-Products (ATPs) of ReMCA achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.45\times \sim 5.51\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.58\times \sim 5.12\times $ </tex-math></inline-formula> improvements.

Design of an Integrated Cryptographic SoC Architecture for Resource-Constrained Devices

One of the active research areas in recent years that has seen researchers from numerous related fields converging and sharing ideas and developing feasible solutions is the area of hardware security. The hardware security discipline deals with the protection from vulnerabilities by way of physical devices such as hardware firewalls or hardware security modules rather than installed software programs. These hardware security modules use physical security measures, logical security controls, and strong encryption to protect sensitive data that is in transit, in use, or stored from unauthorized interferences. Without mechanisms to circumvent the ever-evolving attacking strategies on hardware devices and the data that they process or store, billions of dollars will always be lost to attackers who ply their trade by targeting such vulnerable devices. This paper, therefore, proposes an integrated cryptographic SoC architecture solution to this menace. The proposed architecture provides security by way of key exchange, management, and encryption. The proposed architecture is based on a True Random Number generator core that generates secret keys that are used in Elliptic Curve Diffie-Hellman Key Exchange to perform elliptic curve scalar multiplication to obtain public and shared keys after the exchange of the public keys. The proposed architecture further relies on a Key Derivation Function based on the CubeHash algorithm to obtain Derived Keys that provide the needed security using the ChaCha20_Poly1305 Authenticated Encryption with Associated (AEAD) Data Core. The proposed Integrated SoC architecture is interconnected by AMBA AHB-APB on-chip bus and the system is scheduled and controlled using the PicoRV32 opensource RISC-V processor. The proposed architecture is tested and verified on the Virtex-4 FPGA board using a custom-designed GUI desktop application.

FPGA-Based Real-Time Simulation of Dual-Port Submodule MMC–HVDC System

Aiming at the problems of the high switch numbers, complex working mechanisms, and complicated real-time simulation of modular multilevel converters (MMCs) composed of dual-port submodules, in this study, we designed a unified equivalent model of the multiple submodule network by analyzing the combination of parallel submodules in the bridge arm. The proposed model decouples the submodules that do not affect each other in the subnetwork calculation process, thereby reducing the number of prestored parameters in the subnetwork simulation. In the Xilinx Virtex-7 FPGA VC709 (Xilinx Corporation, San Jose, CA, USA) development board, we replaced the inline computation combined with the prestorage of parameters with the proposed equivalent model to optimize the execution unit structure and redesigned the FPGA-Based Real-Time Digital Solver (FRTDS). Taking the P-FBSM-based MMC–HVDC system as the simulation object, we performed a real-time simulation with a step size of 10 μs, which verified the effectiveness of the proposed model and the improvement in the hardware. We compared the results with the offline MATLAB/Simulink simulation results to verify the accuracy of the simulation.

An Improved Unified AES Implementation Using FPGA

Encryption is an essential process in electronic data transmission because it securely protects the data from unauthorized access. In this digital era, information and its security are of great concern with technology advancements. As we have entered into 5G technology that targets end-to-end security and speed to communicate with intelligent devices. These devices and systems need an AES module having both the operation as encryption and decryption in a single module to communicate in duplex mode to access the information in a real-time environment. This article has architecture of a unified module with modified round operation and has been implemented on Virtex-7 FPGA platform. Mix column adds vertical alteration in the algorithm and this design has managed the utilization of Mix column block to make an optimized AES algorithm. The unified AES has achieved a maximum frequency of 290.3MHz and resource utilization of 9416 slice LUTs design, including some modification in traditional AES, resulting in less resource utilization and high throughput.

Accelerated RISC-V for Post-Quantum SIKE

In this work, we present a fast and area-efficient software-hardware implementation of the supersingular isogeny key encapsulation (SIKE) mechanism. Our software-hardware design achieves both the flexibility of software as well as the efficient performance of intense computations of hardware. In particular, our implementation takes advantage of new and highly optimized hardware modules for addition, multiplication, and hardware-software control, targeted at Xilinx FPGAs. In conjunction with a small RISC-V processor, we can support all four SIKE parameter sets. On a Virtex-7 FPGA, this implementation occupies 3,492 slices, 78 DSPs, and 29 BRAMs, to perform encapsulation and decapsulation over SIKEp434, SIKEp503, SIKEp610, and SIKEp751 in 14.5, 19.2, 29.8, and 42.7 ms, respectively. Despite supporting all four parameter sets, this design has the best area-time product of all isogeny accelerators in the literature.

A High-Performance SIKE Hardware Accelerator

Supersingular isogeny key encapsulation (SIKE) is a promising candidate in the NIST postquantum cryptography (PQC) standardization process, which has the smallest key lengths. It is the only isogeny-based cryptographic scheme in the NIST list that leverages the traditional elliptic curve cryptography (ECC) arithmetic; however, the high computational complexity is one of its limiting factors. In this work, we proposed a high-performance hardware architecture for the SIKE protocol. The architecture includes an improved multiplier based on the high-performance finite field multiplication (HFFM) algorithm which is 15%–20.7% faster than the previous multiplier based on the HFFM algorithm and a unified adder/subtractor with radix <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3^{b}$ </tex-math></inline-formula> . In addition, it also comprises an efficient scheduler strategy that decomposes all the functions of SIKE into finite field <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$F_{p}$ </tex-math></inline-formula> and then effectively schedules through optimized multiplication chains for maximal performance. The proposed architecture is synthesized and implemented on Xilinx Virtex-7 FPGA for all the four variants of SIKE having security levels from 1 to 5 and achieved 2.6%–7.8% faster speeds as well as consumed less equivalent number of slices (ENS) than the state-of-the-art designs. In the comparison of area and time (AT), the proposed architecture is 14.2%–34.5% lower than the previous architecture.

Simulation and Implemetation of High-Speed Data Transmission Over Aurora Protocol Using FPGA

Abstract: This paper proposes a simulation and implementation of highspeed knowledge transmission over twin freelance aurora channels on One GTX (Gigabit Transceivers) twin TILE by configuring multi-gigabit transceivers (MGT’s), that area unit gift within the virtex-5 FPGA victimization aurora protocol. (Here GT suggests that Gigabit transceivers (GT) and X indicates that these transceivers belong to Virtex-5 FXT platform. FXT platform supports superior embedded systems with advanced serial connectivity). Firstly, a 128-bit parallel knowledge is to be generated victimization simulators, that area unit enforced victimization VHDL language. The asynchronous first-in first-out (AFIFO) takes this 128-bit knowledge as input and produces an output of 16-bit parallel knowledge. This knowledge goes to the aurora module in parallel type as serial frames (i.e., 8 frames, every frame consists of two bytes). Finally, the 128-bit parallel knowledge is transmitted to the receiver module serially over fibre optic cable at the speed of three.125Gbps victimization study options of virtex5 FPGA. to attain high speed, Multi-Gigabit Transceivers (MGT) area unit used. In virtex-5 FPGA, these Multi-Gigabit Transceivers area unit obtainable as arduous IPs that operates at the clock rate of 156.25 megahertz (MGT clock). For configuring these MGT’s, Aurora protocol is employed, that converts the parallel knowledge into serial knowledge and the other way around. Finally, the information is transmitted on 2 freelance aurora channels and any testing is distributed victimization chip scope professional analyser to verify the integrity of information. Keywords: Aurora protocol, Virtex-5 FPGA, MGT’s, AFIFO, twin freelance Aurora Channels, GTX twin TILE, Serial knowledge Transmission.

Area-Time Efficient Hardware Architecture for CRYSTALS-Kyber

This paper presents a novel area-time efficient hardware architecture of the lattice-based CRYSTALS-Kyber, which has entered the third round of the post-quantum cryptography standardization competition hosted by the National Institute of Standards and Technology. By developing a dual-path delay feedback number theoretic transform multiplier dedicating for Kyber parameter set and deploying this multiplier in the Kyber architecture, the key generation, encryption, and decryption operations are accelerated substantially. Furthermore, the proposed architecture offers the best value of area-time product in comparison with existing approaches. The implementation results on Xilinx Vivado targeted for Virtex-7 FPGA board demonstrate that the proposed Kyber cryptoprocessor completes encryption and decryption operations in approximately 57.5 μs at the highest frequency of 226 MHz. Furthermore, the area-time product value when using the proposed Kyber architecture is improved by at least twofold compared with existing architectures.

FPGA Implementation of Secure Block Creation Algorithm for Blockchain Technology

Blockchain technology is essential to secure storage, authenticate data, and protect information from being misused and exploitation. Traditional methods of securing data using cryptographic algorithms include hashing functions like SHA-0, SHA-1, which have limitations like excess computational time, collision attacks, scalability, backtracking to retrieve the original message, etc. Using a combination of RSA and SHA together allows us to create a block on an FPGA, which when combined with other blocks establishes an encrypted Blockchain, which overcomes such limitations. Synthesis and implementation of the encrypted block have been compared and analyzed on Virtex-4, Virtex-5, and Spartan-6 FPGA boards. Based on the resource requirement like the slice registers, LUT-FF pairs and memory, Virtex-5 was chosen. Complete security is achieved as the hashing process is irreversible and backtracking of data is not possible. Previous problems of strengthening security, backtracking, excessive memory usage, and zero collision attacks are addressed and solved.

VLSI Architecture of Decision Based Adaptive Denoising Filter for Removing Salt &amp; Pepper Noise

A new Decision Based Adaptive Denoising Filter (DBADF) algorithm &amp; hardware architecture are proposed for restoring the digital image that is highly corrupted with impulse noise. The proposed DBADF detects only the corrupted pixels and that pixel is restored by the noise-free median value or previous value based upon the noise density in the image. The proposed DBADF uses a window initially and adaptively goes up to window based on the noise corruption more than 50% by impulse noise in the current processing window. The proposed architecture was found to exhibit better visual qualitative and quantitative evaluation based on PSNR, IEF, EKI, SSIM, FOM, and error rate. The DBAMF architecture also preserves the original information of digital image with a high density of salt &amp; pepper noise, when compared to many standard conventional algorithms. The proposed architecture has been simulated using the VIRTEX7 FPGA device and the reported maximum post place and route frequency are 149.995MHz and the dynamic power consumption is 179mW.

A Scalable Digit-Parallel Polynomial Multiplier Architecture for NIST-Standardized Binary Elliptic Curves

This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most relevant state-of-the-art multipliers. All multiplier architectures are implemented in Verilog HDL using the Vivado IDE tool. The implementation results are reported on a 28 nm Virtex-7 FPGA technology. The dedicated multipliers utilize slices of 1182 (for m=163), 1451 (for m=233), 1589 (for m=283), 2093 (for m=409) and 3451 (for m=571). Moreover, our dedicated designs can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Similarly, for all supported binary fields, our scalable architecture (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 μs for one finite field multiplication and (iv) consumes 3.905 W power. The proposed scalable digit-parallel architecture is more area-efficient than most recent state-of-the-art multipliers. Consequently, the reported results and comparison to the state of the art reveal that the proposed architectures are well suited for cryptographic applications.

Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier

This paper presents an area efficient and high-speed FPGA implementation of scalar multiplication using a Vedic multiplier. Scalar multiplication is the most important operation in Elliptic Curve Cryptography(ECC), which used for public key generation and the performance of ECC greatly depends on it. The scalar multiplication is multiplying integer k with scalar P to compute Q=kP, where k is private key and P is a base point on the Elliptic curve. The Scalar multiplication underlying finite field arithmetic operation i.e. addition multiplication, squaring and inversion to compute Q. From these finite field operations, multiplication is the most time-consuming operation, occupy more device space and it dominates the speed of Scalar multiplication. This paper presents an efficient implementation of finite field multiplication using a Vedic multiplier. The scalar multiplier is designed over Galois Binary field GF(2233) for field size=233-bit which is secured curve according to NIST. The performances of the proposed design are evaluated by comparing it with Karatsuba based scalar multiplier for area and delay. The results show that the proposed scalar multiplication using Vedic multiplier has consumed 22% less area on FPGA and also has 12% less delay, than Karatsuba, based scalar multiplier. The scalar multiplier is coded in Verilog HDL, synthesize and simulated in Xilinx 13.2 ISE on Virtex6 FPGA.

A Fast Spiking Neural Network Accelerator based on BP-STDP Algorithm and Weighted Neuron Model

Spiking neural networks (SNNs) are inspired from biological brains and have demonstrated great energy efficiency on hardware computing platforms. However, it is a challenge to implement an online training algorithm on SNN hardware to adapt to the realistic cognitive applications. Besides, the accuracies of SNN adopted rate-based coding scheme are highly depend on the number of coding timesteps, resulting in the long data processing time and massive power consumption. In this brief, a multilayer online training SNN accelerator based on spike-timing-dependent plasticity based back-propagation (BP-STDP) algorithm is carried out. To speed up the spike processing, a weighted neuron model is proposed according to the characteristics of BP-STDP training algorithm. In addition, the training module can reuse the integrate and fire arithmetic unit circuits in hidden layer neuron module, which can significantly reduce the hardware overheads. The proposed accelerator is verified on the Xilinx Virtex-7 FPGA under 100Mhz clock frequency for the application of handwritten digit recognition. The proposed accelerator achieves a 95.3% recognition accuracy rate while consuming 0.27 ms for recognizing one image, and 1.22 ms for training one image. Compared with the software implementation, the proposed accelerator demonstrates <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$41.87\times $ </tex-math></inline-formula> training speedup and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$56.96\times $ </tex-math></inline-formula> recognizing speedup.

Hardware-Implemented Security Processing Unit for Program Execution Monitoring and Instruction Fault Self-Repairing on Embedded Systems

Embedded systems are increasingly applied in numerous security-sensitive applications, such as industrial controls, railway transports, intelligent vehicles, avionics and aerospace. However, embedded systems are compromised in the execution of untrusted programs, where the instructions could be maliciously tampered with to cause unintended behaviors or program execution failures. Particularly for remote-controlled embedded systems, program execution monitoring and instruction fault self-repair are important to avoid unintended behaviors and execution interruptions. Therefore, this paper presents a hardware-enhanced embedded system with the integration of a Security Processing Unit (SPU) in which integrity signature checking and checkpoint-rollback mechanisms are coupled to achieve real-time program execution monitoring and instruction fault self-repairing. This System-on-Chip (SoC) design was implemented and validated on the Xilinx Virtex-5 FPGA development platform. Based on the evaluation of the SPU in terms of the performance overhead, security capability, and resource consumption, the experimental results show that, while the CPU executes different benchmarks, the average performance overhead of the SPU lowers to 1.92% at typical 8-KB I/D caches, and it provides both program monitoring and fault self-repairing capabilities. Unlike conventional hardware detection technologies that require manual handling to recovery program executions, the CPU–SPU collaborative SoC is a resilient architecture equipped with instruction tampering detection and a post-detection strategy of instruction fault self-repairing. Moreover, the embedded system satisfies a good balance between high security and resource consumption.

Efficient Architectures for Full Hardware Scrypt-Based Block Hashing System

The password-based key derivation function Scrypt has been employed for many services and applications due to its protection ability. It has also been employed as a proof-of-work algorithm in blockchain implementations. Although this cryptographic hash function provides very high security, the processing speed and power consumption to generate a hashed block for the blockchain network are low-performance. In this paper, a high-speed and low-power hardware architecture of the Scrypt function is proposed to generate blocks for the Scrypt-based blockchain network. This architecture minimizes the number of main computational blocks to reduce the power consumption of the system. In addition, the proposed sharing resources and pipelined architectures make the calculation speed increase significantly while the hardware cost is reduced by half compared to the parallel non-pipelined architecture. The full hardware system is designed and implemented on Xilinx Virtex-7 and Aveo U280 FPGA platforms. The hash rate of the proposed system reaches 229.1 kHash/s. Its hash rate, hardware and energy efficiencies are much higher than those of the other works implemented on FPGA and GPU hardware platforms. The proposed hardware architecture is also successfully implemented in an ASIC design using ROHM 180 nm CMOS technology.