Virtex-5 FPGA Research Articles

Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microblaze Soft Core Processor

Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.

Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems

This brief presents the efficient VLSI implementation of coordinate rotation digital computer (CORDIC)-based sorted QR decomposition (SQRD) for multiple-input and multiple-output (MIMO) systems. SQRD is widely adopted in MIMO signal processing to mitigate error propagation. However, its iterative sorting process after every column annihilation requires a large hardware overhead and suffers from a latency issue. The proposed CORDIC-based SQRD modifies a real-value decomposition matrix to utilize symmetry and jointly performs sorting processes and CORDIC rotations with adjacent symmetric columns to reduce the required number of CORDIC rotations and CORDIC stages. Furthermore, the VLSI design of the proposed SQRD has been synthesized and implemented with a Virtex-6 FPGA and a 65-nm CMOS technology, respectively. The 65-nm implementation results show an overall processing latency of 266.5 ns, a throughput of 48.8 MSQRD per second, and can support a 4.7-Gbps MIMO system throughput.

Delta-Sigma Modulation for Next Generation Fronthaul Interface

A new function split option for the next generation fronthaul interface (NGFI) is demonstrated based on all-digital RF transmitter using bandpass delta-sigma modulation. Different from other low layer split (LLS) options, such as option 6 (MAC-PHY), 7 (high-low PHY), and 8 (CPRI), the proposed option 9 implements RF functions in the digital domain, and splits within the RF layer, with high-RF layer centralized in the distributed unit (DU) and low-RF layer distributed in remote radio units (RRUs). A proof-of-concept all-digital RF transmitter based on real-time delta-sigma modulation is implemented using a Xilinx Virtex-7 FPGA. A 5-GSa/s delta-sigma modulator is demonstrated to encode LTE/5G signals with bandwidth up to 252 MHz and modulation format up to 1024-QAM to a 5-Gb/s OOK signal, which is transmitted over 30-km single-mode fiber from DU to RRU. To relax the FPGA speed requirement, a 32-pipeline architecture is designed. Two-carrier aggregation of 5G and 14-carrier aggregation of LTE signals are demonstrated with error vector magnitude (EVM) performance satisfying the 3GPP specifications. Compared with option 8 (CPRI), although the proposed option 9 split occurs at a lower level, it offers improved spectral efficiency and reduced NGFI data rate than CPRI. Moreover, other LLS options, such as 6, 7, and 8, all require a complete RF layer implemented in the analog domain at remote cell sites; whereas option 9 realizes high-RF layer in the digital domain at DU, and eliminates the need of analog RF devices, such as DAC, local oscillator and mixer at RRU, which not only makes low-cost, energy-efficient, and small-footprint cell sites possible for the wide deployment of small cells, but also paves the road toward software defined radio (SDR) and virtualization of DU and RRU for improved compatibility and reconfigurability among multiple radio access technologies (multi-RATs). Given its centralized architecture and deterministic latency, option 9 is suitable for radio coordination applications, and has potential in low-frequency narrowband scenarios with cost, power, and/or size sensitive cell sites, such as massive machine type communication (mMTC) and narrowband internet of things (NB-IoT).

Implementation of fast FFT design for 128-point using Radix-22 CFA

In this paper, implementation of fast FFT design for 128- point using Radix-22 CFA is presented. This research uses a common factor algorithm which is based on Radix-22. A 2-point DFT butterfly structure is the lowest complexity structure and Radix-22 CFA is used to reduce logic and area by reducing the number of twiddle factors. The VHDL code is written and synthesized using Xilinx FPGA device xc7vx330t-3ffg1761 to implement the proposed design. This design is coded in VHDL and MATLAB. VHDL code is targeted to synthesize into Xilinx Virtex-7 FPGA and simulated into ModelSim PE Student Edition 10.4a. MATLAB code is simulated into MATLAB 2012. The proposed design achieves 149.822 MHz clock frequency, used 2802 slices on the Virtex-7 and SQNR 33.49 dB at 16-bit I/O word length.

Flexible elliptic curve cryptography coprocessor using scalable finite field arithmetic blocks on FPGAs

The increasing dependency of modern day information transferred over the network demands an increasing need of efficient implementations of security protocols on server and client devices to process the encryption and decryption of messages. This paper presents the design of an efficient scalable and unified Elliptic Curve Cryptography (ECC) coprocessor that takes advantage of the DSP48E slices on Xilinx FPGAs. The proposed coprocessor is able to evaluate the elliptic curve point multiplication (ECPM) for all 15 curves recommended by the National Institute of Standards and Technology (NIST). The DSP48E slices available in Xilinx FPGAs improve the performance of the coprocessor and provide the ability to evaluate dual-field arithmetic. The coprocessor has been implemented on a Xilinx Virtex-5 FPGA and it requires 4244 registers, 8316 LUTs, 2291 slices, 5 BRAMs and 25 DSP48E slices. It can evaluate the ECPM between 0.857 ms and 9.662 ms for prime curves and between 0.239 ms and 4.523 ms for binary curves. This paper also proposes a set of scalable finite field arithmetic blocks that can be programmed to implement different ECPM algorithms. In comparison with other ECC coprocessors in the current literature, the proposed design is very competitive in terms of timing performance and hardware resource utilization, while combining the scalability and dual-field features that are not available in other designs.

FPGA implementation of 1000base-x Ethernet physical layer core

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

Dual Split-Merge: A high throughput router architecture for FPGAs

Modern FPGAs have become competitive platforms for System-on-Chip (SoC) designs resulting in the emergence of Network-on-Chip (NoC) paradigm as a promising solution for FPGAs interconnects problems. This paper proposes a high throughput FPGA-oriented router architecture denoted by Dual Split-Merge (DSM). The proposed architecture divides the router into two independent internal routers handling each network dimension. The division allows an incoming packet to face only half the complex logic and half the arbitration, increasing both the network throughput and the maximum operating frequency. Each internal router utilizes split and merge primitives that obviate the need for a switch crossbar and a switch allocater, decreasing the router area. The implementation results show the significant improvements in performance of the proposed router over the existing ones. The proposed router has a higher throughput than all other routers and a small network latency. A 4 × 4 network of DSM routers achieves a maximum throughput of 4.6 Gflits/s on Virtex-6 FPGA.

An asynchronous mesh NoC based booth multiplication

The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The Booth structure of a multiplier is a wide-used and efficient structure of real IC systems, and the performance of a Booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a Booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8-bit asynchronous Booth multiplier, which is synthesized and post simulated with a Xilinx Virtex-7 FPGA development board.

Highly-parallel hardware implementation of optimal ate pairing over Barreto-Naehrig curves

Bilinear pairing over elliptic curves is the key technology to construct identity based encryption schemes. An appropriate hardware design can significantly speed up pairing computation. In this paper, we present a highly-parallel hardware design for optimal ate pairing over Barreto-Naehrig curves. The proposed design exploits parallelism at different levels of the pairing algorithm, including Fp and Fp2 operations as well as the operations based on Fp2. Especially the proposed architecture of dual Fp2 units at the top level makes the pairing computation more efficient. Finally, we implement a system on chip (SoC) that contains Microblaze CPU, AXI-Lite bus and the pairing computation unit. The design is verified on a Virtex-7 FPGA device with the parameters of pairing chosen according to the Identity-Based Cryptographic Algorithms SM9 enacted by China. The results show that our design computes the optimal ate pairing of 128-bit security within 394,806 cycles, which is about 3.4 ms under the working frequency of 115 MHz, and consumes about 28 k Slices and 128 DSPs.

Hyperchaos-Based Spreading Codes Generator for DS-CDMA Communication Systems

In this paper, we propose a new hyperchaos-based spreading codes generator (HSCG) for multi-users direct sequence spread spectrum (DSSS) communication systems. For experimental validation, we implement the proposed generator in Xilinx FPGA Virtex-5 technology. Contrary to the traditional spreading codes, the proposed HSCG offers interesting statistical properties such as good autocorrelation, very small cross-correlation, no repetition of the generated spreading codes and high degree of security. In addition, the developed hardware architecture used for implementing the HSCG permits to generate simultaneously an infinite number of multi-length spreading codes with high hardware performances in terms of logic area consumption, throughput and latency. Real-time results are given for 32-, 64- and 128-bit chaotic spreading codes. All of these properties are validated and compared with that of classical codes (Gold sequences, Walsh–Hadamard) through bit error rate (BER) performance evaluation in a DS-CDMA system in AWGN and time-invariant multipath channels. With its interesting performances, the proposed HSCG is very useful for the next generations of mobile communication systems.

Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system

This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT.

Design and Digital Implementation of Fast and Recursive DCT II–IV Algorithms

Using the proposed factorizations of discrete cosine transform (DCT) matrices, fast and recursive algorithms are stated. In this paper, signal flow graphs for the n-point DCT II and DCT IV algorithms are introduced. The proposed algorithms yield exactly the same results as with standard DCT algorithms but are faster. The arithmetic complexity and stability of the algorithms are explored, and improvements of these algorithms are compared with previously existing fast and stable DCT algorithms. A parallel hardware computing architecture for the DCT II algorithm is proposed. The computing architecture is first designed, simulated, and prototyped using a 40-nm Xilinx Virtex-6 FPGA and thereafter mapped to custom integrated circuit technology using 0.18- $$\upmu $$ m CMOS standard cells from Austria Micro Systems. The performance trade-off exists between computational precision, chip area, clock speed, and power consumption. This trade-off is explored in both FPGA and custom CMOS implementation spaces. An example FPGA implementation operates at clock frequencies in excess of 230 MHz for several values of system word size leading to real-time throughput levels better than 230 million 16-point DCTs per second. Custom CMOS-based results are subject to synthesis and place-and-route steps of the design flow. Physical silicon fabrication was not conducted due to prohibitive cost.

Hardware implementation of adaptive feedback based reversible image watermarking for image processing application

This paper presents a reversible image watermarking (RIW) method including an adaptive feedback part based on difference expansion (DE). With respect to some parameters of the image, peak signal to noise ratio (PSNR), the highest payload capacity and the corresponding embedding threshold are spontaneously calculated by using the proposed adaptive feedback-based reversible Image watermarking (AFRIW). The payload capacity for data embedding is briefly explained. The machinery part of the adaptive feedback for controlling the payload capacity is presented. Software verification of three cover images is presented. Based on some image parameters, the comparative result between the proposed AFRIW algorithm and DE-based RIW method is presented. This paper also presents the VLSI architecture of this proposed algorithm for RIW. The proposed architecture has been implemented using VIVADO 2016.2 based on Xilinx Virtex-7 FPGA and Zynq device platforms. The software implementation results clearly demonstrated that the AFRIW method provides higher PSNR than the DE-based RIW method. The hardware implementation results indicate that the proposed algorithm has low timing complexity over other existing feedback based RIW algorithms which in turn provide higher speed.

A fast digit based Montgomery multiplier designed for FPGAs with DSP resources

A fast Montgomery multiplier design utilizing the DSP resources in modern FPGAs is presented. In the proposed design, the operand size is the multiples of 528 bits and the digit size is 48 bits. The design has 48 × 48 bit digit multipliers built from the DSP slices performing 24 × 16 bit multiplications and a carry select accumulator built from the DSP slices performing 48 bit additions. The proposed Montgomery multiplier works iteratively. In each iteration, a digit of an operand is multiplied by the digits of the other, the result is accumulated, and reduced by Montgomery method. An iteration takes not one but eight cycles to keep the digit multiplier count low and save some hardware resources. The proposed design is implemented for Virtex-7 FPGAs. The performance results are comparable with the best results in the literature. Substantial savings in FPGA logic resources are obtained.

A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field

SummaryThis workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art.

FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports

In recent years, there has been an increasing growth of using vision-based systems for tracking the players in team sports to evaluate and enhance their performance. Player tracking using vision systems is a very challenging task due to the nature of sports games, which includes severe and frequent interactions (e.g. occlusions) between the players. Additionally, these vision systems have high computational demands since they require processing of a huge amount of video data based on the utilization of multiple cameras with high resolution and high frame rate. As a result, most of the existing systems based on general-purpose computers are not able to perform online real-time player tracking, but track the players offline using pre-recorded video files, limiting, e.g., direct feedback on the player performance during the game. In this paper, we present a reconfigurable system to track the players in indoor sports automatically and without user interaction. The proposed system performs real-time processing of the incoming video streams from the cameras, achieving online player tracking. The teams are identified, and the players’ positions are detected based on the colors of their jerseys. FPGA technology is used to handle the compute-intensive vision processing tasks by implementing the video acquisition, video preprocessing, player segmentation, and team identification & player detection modules in hardware, realizing an online real-time system. While the pixel processing is performed in the FPGA, the less compute-intensive player tracking is performed on a general purpose computer. The maximum achieved frame rate for the FPGA implementation is 96.7 fps using a mature Xilinx Virtex-4 FPGA, and can be increased to 136.4 fps using a Xilinx Virtex-7 device. The Player tracking requires an average time of 2.5 ms per frame in the host-PC. As a result, the proposed reconfigurable system supports a maximum frame rate of 78.9 fps using two cameras with a resolution of 1392 × 1040 pixels each. Our results show that the achieved average precision and recall for player detection are up to 84.02% and 96.6%, respectively. Including player tracking, the achieved average precision and recall are up to 94.85% and 94.72%, respectively. Using the proposed FPGA implementation, a speedup by a factor of 15.2 is achieved compared to an OpenCV-based software implementation on a PC equipped with a 2.93 GHz Intel i7-870 CPU.

FPGA-Based On-Board Geometric Calibration for Linear CCD Array Sensors.

With increasing demands in real-time or near real-time remotely sensed imagery applications in such as military deployments, quick response to terrorist attacks and disaster rescue, the on-board geometric calibration problem has attracted the attention of many scientists in recent years. This paper presents an on-board geometric calibration method for linear CCD sensor arrays using FPGA chips. The proposed method mainly consists of four modules—Input Data, Coefficient Calculation, Adjustment Computation and Comparison—in which the parallel computations for building the observation equations and least squares adjustment, are implemented using FPGA chips, for which a decomposed matrix inversion method is presented. A Xilinx Virtex-7 FPGA VC707 chip is selected and the MOMS-2P data used for inflight geometric calibration from DLR (Köln, Germany), are employed for validation and analysis. The experimental results demonstrated that: (1) When the widths of floating-point data from 44-bit to 64-bit are adopted, the FPGA resources, including the utilizations of FF, LUT, memory LUT, I/O and DSP48, are consumed at a fast increasing rate; thus, a 50-bit data width is recommended for FPGA-based geometric calibration. (2) Increasing number of ground control points (GCPs) does not significantly consume the FPGA resources, six GCPs is therefore recommended for geometric calibration. (3) The FPGA-based geometric calibration can reach approximately 24 times faster speed than the PC-based one does. (4) The accuracy from the proposed FPGA-based method is almost similar to the one from the inflight calibration if the calibration model and GCPs number are the same.

Development and Implementation of Parallel to Serial data Transmitter Using Aurora Protocol for High Speed Serial Data Transmission on Virtex-7 FPGA

The objective of this paper is Development and Implementation of parallel to serial data converter using Aurora protocol for high speed serial data transmission at the rate of 3.125Gbps by using architectural features of Virtex-7 FPGA. It involves the study and configuring the Xilinx Core Generator Tool to achieve the required high speed serial data transmission by using of Aurora 8b/10b Protocol & Multi-Gigabit Transceivers present in Virtex-7 FPGA. Firstly, a 192-bit parallel data is generated using simulators, which is implemented using VHDL language. The 192-bit data is sent to Asynchronous First-In First-Out (AFIFO) as input and produces an output of 32-bit parallel data. This data is sent to the aurora module in parallel form as successive frames (i.e. 6 frames, each frame consists of 4 bytes). Finally, the 192-bit parallel data is transmitted to the receiver module serially over fiber optic cable at the rate of 3.125Gbps using architectural features of virtex7 FPGA. Finally, the data is transmitted on dual independent aurora channels and the entire logic will be tested for its complete functionality in standalone mode by porting on to the Virtex-7 FPGA based custom Hardware. Keywords: Aurora Protocol, Independent Aurora Channels, Serial Data Transmission, Virtex-7 FPGA, AFIFO, GTX TILE, MGT’s

An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIM

This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route Placed design.

Low Area FPGA Implementation of DROM-CSLA-QTL Architecture for Cryptographic Applications

Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.