VHDL Programs Research Articles

Design and Simulation of Vedic Multiplier Using Verilog HDL

Abstract: This Paper is created for the simulation of a high speed Vedic multiplier. In the proposed paper, the multiplier circuit is designed by using algorithms that involve Vedic Mathematics. Calculations that involve Vedic mathematics are derived from the old contexts known as Vedas. The VHDL programs are synthesized and simulated using Xilinx ISE simulator. The study of Vedic multipliers is done in comparison with the conventional multipliers to find the fact that which multiplier is fast and efficient and the research and analysis has shown that the Vedic multiplier is more efficient than conventional multipliers because of its fast response in digital signal processing and it gives less delay in system logic design. Vedic mathematics used in the Vedic multiplier increases the speed of multiplier as it reduces the number of partial products. Hence, the speed of the overall digital design can be increased by implementing a Vedic multiplier.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter (RSD-ADC) is presented featuring a high signal to noise ratio (SNR), spurious free dynamic range (SFDR) and signal to noise plus distortion (SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC (residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

Slicing tools for synchronous reactive programs

In this paper, we present two slicing tools: VHDL_Slice and Est_slice that compute static executable slices of VHDL and Esterel programs respectively. The slicers have been tested on a number of small and medium sized examples.

Program slicing for VHDL

Hardware description languages (HDLs) are used today to describe circuits at all levels. In large HDL programs, there is a need for source code reduction techniques to address a myriad of problems in design, simulation, testing, and formal verification. Program slicing is a static program analysis technique that allows an analyst to automatically extract portions of programs relevant to the aspects being analyzed. Slicing is fundamentally based on data and control dependences between program points. However, program slicing algorithms have traditionally been designed for sequential languages, and the presence of concurrent constructs such as those found in HDLs complicates slicing considerably. In this paper, we develop the concepts needed for slicing VHDL. The techniques extend readily to other HDLs such as Verilog. Our techniques are based on a slicing-oriented VHDL execution semantics that augments traditional dependences with inter-procedural dependences between VHDL processes. Based on these concepts, we have developed an automatic VHDL slicing tool composed of a traditional slicer and a front-end that captures VHDL simulation semantics. This paper discusses our techniques for VHDL slicing, the slicer tool, and slicing applications in design, simulation, testing, and formal verification of VHDL programs. A particularly important application of HDL slicing is source code reduction leading to reduced state spaces for model checking, and we also present empirical results for this.

Debugging Hardware Designs Using a Value-Based Model

In this paper we describe the use of model-based diagnosis for locating bugs in hardware designs. Nowadays hardware designs are written in a programming language. We restrict our view to hardware designs written in a subset of the commonly used hardware description language VHDL. This subset includes all synthesize-able (register transfer level (RTL)) programs, i.e., programs that can be automatically converted into a gate level representation. Therefore almost all VHDL programs are RTL programs. We show the conversion of VHDL programs into a logical representation. This representation is a model that can be directly used by a model-based diagnosis engine for computing diagnoses. The resulting diagnoses are mapped back to the VHDL code fragments of the original program explaining a misbehavior. In addition, we specify some rules optimizing the obtained results. We further present some arguments showing that the proposed debugging technique scales up to large designs.

Debugging VHDL designs using model-based reasoning

The application of formal methods in software engineering and hardware design has become an important field of research. It aims at minimizing time to market and reduce the overall development costs. While formal verification, e.g. model-checking, is widely used, methods for helping programmers or engineers in locating and fixing faults within a hardware design or software are rarely available. In this paper we describe part of the advanced diagnosis and measurement selection capabilities of the model-based diagnosis tool VHDLDIAG designed for (semi)automatically locating bugs in VHDL programs. VHDL is an Ada-like and widely used hardware description language. VHDL programs are converted into logical descriptions which are then used by a diagnosis engine for detecting the parts of the program responsible for an observed misbehavior. The results of diagnosis, i.e. the malfunctioning program fragments, are mapped back to the program code. Because of the logical description used VHDLDIAG can be applied to a wide range of programs from small to very large ones with up to thousands of MBytes of source code. This paper presents techniques which use multiple versions of a design in diagnosis, as well as the measurement selection process used in VHDLDIAG. Formal definitions and performance results using real-world VHDL programs are given.

Comment on "Event suppression by optimizing VHDL programs"

This paper presents several corrections and comments to the above paper. Errors in the original very high speed integrated circuit hardware descriptive language (VHDL) code are identified. This paper also suggests much simpler optimized VHDL code to achieve the same result.

VHDL semantics and validating transformations

Formal models are used to provide an unambiguous definition of the semantics of very high speed integrated circuit hardware description language (VHDL) and to prove equivalences of VHDL programs. This paper presents a formal model of the dynamic semantics of VHDL that characterizes several important features of VHDL such as delta delays, pulse rejection limits, disconnection delays, postponed processes, sequential statements, and resolution functions. The underlying logic is interval temporal logic, which assists in characterizing the timing information contained in a VHDL program. The semantic definition is not dependent on the VHDL simulation cycle since it only defines the net effect of evaluating a VHDL program. It is argued that this declarative style coupled with the inherent advantages of temporal logic makes it possible to validate transformations (or rewrite rules) on VHDL programs and to formally reason about the timing aspects of VHDL. In particular, we present proofs of soundness of rewrite rules such as process folding and signal collapsing, and use temporal logic to derive an algorithm for determining when a given VHDL program is free of transaction preemption.

Model-based diagnosis of hardware designs

The state of the art in hardware design is the use of hardware description languages such as VHDL. The designs are tested by simulating them and comparing their output to that prescribed by the specification. A significant part of the design effort is spent on detecting unacceptable deviations from this specification and subsequently localizing the sources of such faults. In this paper, we describe an approach to employ model-based diagnosis for fault detection and localization in very large VHDL programs, by automatically generating the diagnosis model from the VHDL code and using observations about the program behavior to derive possible fault locations from the model. In order to achieve sufficient performance for practical applicability, we have developed a representation that provides a highly abstracted view of programs and faults, but is sufficiently detailed to yield substantial reductions in the fault localization costs when compared to the current manpower-intensive approach. The implementation in conjunction with the knowledge representation is designed with openness in mind in order to facilitate use of the highly optimized simulation tools available.

Event suppression by optimizing VHDL programs

The performance and efficiency of event-driven simulations, such as VHDL and Verilog simulation, depend on the number of events that occur during the simulation. In this paper, we classify events into two categories, sensitive events and insensitive events, according to the necessity of simulations, and show classification algorithms for both combinational circuits and sequential circuits. We also implement the optimization methodology that eliminates unnecessary simulation activity caused by the insensitive events. VHDL programs can be rewritten by augmenting suppressed sensitivity lists. Experiments show that the optimized VHDL programs run almost two times faster than the original ones.

Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming

A method for generation of design verification tests from behavior-level VHDL programs is presented. The method generates stimuli to execute desired control-flow paths in the given VHDL program. This method is based on path enumeration, constraint generation and constraint solving techniques that have been traditionally used for software testing. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements, and wait statements which are not found in traditional software programming languages. Our model of constraint generation is specifically developed for VHDL programs with such constructs. Control-flow paths for which design verification tests are desired are specified through certain annotations attached to the control statements in the VHDL programs. These annotations are used to enumerate the desired paths. Each enumerated path is translated into a set of mathematical constraints corresponding to the statements in the path. Methods for generating constraint variables corresponding to various types of carriers in VHDL and for mapping various VHDL statements into mathematical relationships among these constraint variables are developed. These methods treat spatial and temporal incarnations of VHDL carriers as unique constraint variables thereby preserving the semantics of the behavioral VHDL programs. Constraints are generated in the constraint programming language CLP(R) and are solved using the CLP(R) system. A solution to the set of constraints so generated yields a design verification test sequence which can be applied for executing the corresponding control path when the design is simulated. If no solution exists, then it implies that the corresponding path can never be executed. Experimental studies pertaining to the quality of path coverage and fault coverage of the verification tests are presented. >