Debugging Hardware Designs Using a Value-Based Model

Abstract

In this paper we describe the use of model-based diagnosis for locating bugs in hardware designs. Nowadays hardware designs are written in a programming language. We restrict our view to hardware designs written in a subset of the commonly used hardware description language VHDL. This subset includes all synthesize-able (register transfer level (RTL)) programs, i.e., programs that can be automatically converted into a gate level representation. Therefore almost all VHDL programs are RTL programs. We show the conversion of VHDL programs into a logical representation. This representation is a model that can be directly used by a model-based diagnosis engine for computing diagnoses. The resulting diagnoses are mapped back to the VHDL code fragments of the original program explaining a misbehavior. In addition, we specify some rules optimizing the obtained results. We further present some arguments showing that the proposed debugging technique scales up to large designs.