Model Checking Bluespec Specified Hardware Designs

Abstract

Using RTL (Register Transfer Level) models for the verification of complex hardware designs involves reducing the state space of designs using various abstraction techniques. In this paper, we propose faster and earlier verification of hardware designs at a level of abstraction above RTL. We consider a high-level (above RTL) hardware model that uses atomic rules to describe the behavior of a design, which can then be synthesized to RTL code. Bluespec System Verilog (BSV) is an example of such a high-level specification language. We propose a methodology for verification of BSV models using Spin, which is a Model Checking tool. Verification of high-level BSV models may avoid the need for using abstraction techniques since such models already ignore various low-level details that are irrelevant for verifying a design's behavioral properties. Moreover, using our proposed methodology different behaviors of BSV models can be efficiently verified at high-level aiding in faster verification.