VLSI Research Articles

Simple power-efficient preamplifier-shaper channel for readout interface of silicon detectors

This paper presents the design and characteristics of a front-end readout system for silicon sensors used in nuclear spectroscopy studies. Furthermore, the study proposes circuit topologies that combine gain-boosting and class-AB techniques featuring a good performance regarding gain, accuracy, speed, linearity, and power consumption, meeting the stringent requirements of deep submicrometer CMOS technologies. The readout channel comprises a charge-sensitive amplifier with a tunable discharge time, pole-zero cancellation circuit, and first-order unipolar shaper with a peaking time of 90 ns. The building blocks are made up of single-stage op-amps, thus not requiring compensation. Furthermore, the circuit is optimized for a detector capacitance of 5 pF, and the noise performance is discussed. Experimental results in a 180 nm CMOS process and a supply voltage of ±0.9 V validate the designed front-end channel. The total area of the chip obtained was 0.028 mm2. The conversion gain was 3.1 mV/fC, and the system maintained linearity up to an input charge range of 150 fC with a maximum output swing of 460 mV and recovered to the baseline within 400 ns. The compact design and the power consumption of only 1.97 mW provided a feasible solution for current radiation detectors coupled to many highly dense electronic channels.

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

AI-Augmented Fault Detection and Diagnosis in VLSI Circuits: A Step toward Intelligent Chip Design

Fault detection and diagnosis are critical challenges in Very Large Scale Integration (VLSI) circuits, where even minor defects can cause significant performance degradation or system failure. Traditional fault detection methods often struggle with scalability and real-time analysis as circuits grow increasingly complex. This paper proposes an AI-augmented framework that leverages machine learning algorithms and neural networks to enhance the fault detection process in VLSI circuits. The proposed model not only identifies and classifies faults with high accuracy but also provides root-cause diagnostics, significantly reducing testing time and maintenance costs. Simulation results demonstrate the effectiveness of the AI-based approach in comparison with conventional techniques, showcasing improved fault coverage, faster detection, and scalability for modern chip designs. This study serves as a step toward the integration of intelligent diagnostics into chip manufacturing, paving the way for more robust and self-healing electronic systems.

Multicore memristor from electrically readable nanoscopic racetracks.

The manipulation and detection of mobile domain walls in nanoscopic magnetic wires underlies the development of multibit memories. The studies of such domain walls have focused on macroscopic wires that allow for optical detection by using magneto-optic effects. In this study, we demonstrated the electrical tracking with a spatial resolution of better than 40 nm of multiple mobile domain walls in nanoscopic racetracks, using a set of anomalous Hall detectors integrated into the racetracks. Electrical time-series signals from the Hall detectors allow for the static and dynamic phase space visualization of the dynamics of a domain wall or multiple domain walls that can be described by a multicore memristor model. The domain wall dynamics and stochasticity can be controlled in racetracks even to deep submicron dimensions.

Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Abstract The efficiency of various stages of physical design in the Very Large Scale Integration (VLSI) circuit can be enhanced by using multi-objective optimization techniques. The circuit is partitioned into a set of modules at the beginning of the physical design phase. This step is known as circuit partitioning. All subsequent physical design stages, like floor planning, placement, pin configuration, and routing etc, are influenced by the outcome of the circuit partitioning method being used. The efficiency of the partitioning method controls the quality of ultimate architecture. The efficiency achieved by the final product may be decreased by incorrect partitioning. This study compares the effectiveness of four Meta-heuristic optimization methods include the Genetic Algorithm (GA), Satin Bowered Bird (SBO), Particle Swarm Optimization (PSO), Simulated Annealing (SA) — in terms of number of net cut, duration of sleeping mode, and efficiency in power consumption for addressing the VLSI circuit partitioning problem. This experiment achieves K-way partitioning of the circuit that minimizes net cuts as well as maximizes sleep duration simultaneously, by evaluating optimization function. Solutions developed using GA, SBO and PSO consistently surpass those acquired using SA with respect to quality of optimal solution. The average optimum net cut and sleep duration achieved by this experiment are 10.7 and 9.9 in GA ; 11.5 and 12.3 in SBO, 11.80 and 9.10 in PSO; and 16.8 and 6.7 in SA based method respectively. This research resulted in a considerable reduction in power consumption, with the system’s average power efficiency achieved by 21.6%, 26.84%, 19.85%, and 14.62%, respectively, in GA, SBO , PSO, and SA based optimizations. The experimental results are compared with a recent publication and proposed GA, SBO, and PSO based methods achieve 18.75%, 4.17%, and 1.04% improvement in terms of average net cut respectively. The proposed GA, SBO, PSO and SA based methods also achieve 44.90%, 51.30%, 40.05%, and 18.60% improvement in terms of average power efficiency.

Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions

Objectives. The problem of restoring the functional description of digital VLSI devices presented at the transistor level is considered. The objective of the work is to develop means for extraction of blocks representing logical networks from two-level descriptions of CMOS circuits at the transistor level, which were obtained as a result of recognition (extraction) of subcircuits that implement logic elements.Methods. Graph based methods and software tools are proposed for extracting a connected blocks representing a logical network from two-level descriptions of a transistor circuits in SPICE format. In the graph interpretation, the task is reduced to constructing a labeled directed graph of a logical network based on a labeled undirected bipartite graph specifying a two-level description of the transistor circuit.Results. The proposed method makes it possible to identify lexicographically ranked logical networks, from which a transition is made to logical equations that specify the functions implemented at the outputs of the resulting networks. Software tools have been developed that provide the generation of a hierarchical description in SPICE format that implements the original circuit at the transistor level, as well as descriptions of found logical networks in the SF language of hierarchical structural and functional descriptions of discrete devices and in high-level languages (VHDL and Verilog).Conclusion. The developed methods are implemented in C++, included in the program for decompiling transistor CMOS circuits and tested within it on practical examples of transistor-level circuits. The paper provides examples of reverse engineering of some practical transistor circuits.

Pragmatic structure optimization: Achieving optimal crosstalk delay and gate oxide reliability of randomly mixed CNT bundle interconnects

This study explores the potential of randomly mixed carbon nanotube bundle (RMCB) as a viable on-chip interconnect. Achieving high-quality carbon nanotubes (CNTs) with uniform diameters is challenging for the current framework of enhanced fabrication techniques. The Stoyan and Yaskov technique is employed to optimize CNT arrangement within a specified rectangular area. This method accounts for statistical variation in CNT diameters, offering a more realistic and fabrication-focused approach to designing CNT bundle interconnects. Eight such practical RMCB structures (RMCB-50 to RMCB-350) are selected using this technique, each characterized by distinct CNT counts and variable diameters. Comprehensive average crosstalk-delay and reliability assessments are conducted by comparing different CNT bundle interconnects with the best-optimized RMCB (O-RMCB) interconnect, placed on various dielectric substrates such as SiO2, SiC, BN. The study unequivocally indicates that O-RMCB produces highly favorable results and stands as the most suitable future solution for VLSI circuits. Additionally, the thickness optimization of O-RMCB interconnect is explored, yielding in improvements in both performance and reliability compared to other well-known CNT bundled interconnects.

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

Design and analysis of low power sense amplifier for static random access memory

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Optimizing VLSI Design Verification with Histogram-Based Difference Algorithm

Abstract: This research explores the optimization of Very Large Scale Integration (VLSI) plan confirmation utilizing the Histogram-Based Distinction Calculation (HBDA) and compares its execution with conventional calculations. Through comprehensive tests, HBDA illustrates predominant confirmation speed, precision, and asset utilization compared to ordinary strategies such as Exhaustive Comparison Algorithm (ECA), Cross-Correlation Calculation (CCA), and Energetic Time Twisting Calculation (DTWA). Particularly, HBDA accomplishes a normal confirmation speed of 25 milliseconds, with a precision of 98.5% and asset utilization of 75%. In differentiation, ECA shows slower confirmation speed (150 milliseconds) and higher asset utilization (100%), whereas CCA and DTWA appear halfway in execution in terms of speed, exactness, and asset utilization. The related work survey highlights different inventive strategies in VLSI plan and optimization, counting neuromorphic computing, vitality gathering, and IoT frameworks. By and large, this research contributes to progressing VLSI plan confirmation techniques, advertising a more effective and solid approach to guarantee the usefulness and unwavering quality of cutting-edge electronic frameworks.

Gamification for Teaching Integrated Circuit Processing in an Introductory VLSI Design Course

Gamification is being incorporated into university classrooms due to its educational benefits for students learning, including encouraging student behavior and engagement, and consequently improving learning outcomes. Despite gamification being increasingly used in education, little has been developed related to Very-Large-Scale Integration (VLSI). In this article, we describe two different gamification experiences applied to integrated circuit processing and design in an introductory VLSI design course for Electronic Engineers. While gamification in universities is still not very mature and our experience spans only two academic years, we observed that, with the practice of gamifying part of our course, the topics treated in games were profoundly learned and the experience was very positive in every aspect of the teaching–learning process.

Retraction Note: Adaptive wavelet ELM-fuzzy inference system-based soft computing model for power estimation in sustainable CMOS VLSI circuits

Retraction Note: Adaptive wavelet ELM-fuzzy inference system-based soft computing model for power estimation in sustainable CMOS VLSI circuits

Design of Energy Efficient Arithmetic VLSI Circuits

Advanced electronics have become an integral part of human lives, from Smartphones in our pockets to the modern vehicles on the road and to the satellites that orbit the earth. Power consumption has become a major constraint in these applications, often employing data- intensive digital signal processing systems and architectures. While enormous transistor density at the nanoscale has been increased in the Very Large-Scale Integration (VLSI) multicore era comparable to Moore's law, improving the performance of computing systems has become extremely difficult. Sustaining technological advancements for such energy-constrained devices has paved the way for new areas in research. “Approximate Computing (AC)” has become one of the most promising paradigms, a field that has gainedsignificant attention in the quest for energy efficiency in recent years. AC algorithms are numerically approximate rather than accurate. Inherent error resilience is the primary source of motivation behind AC. Recent research demonstrates that error resilience is pervasive in cyber search, deep learning, multimedia, recognition and data mining. Arithmetic units are the fundamental building blocks in most of the data dominated applications at the micro- architectural level of abstraction. AC is optimal for power and area efficient arithmetic circuits.

On-chip based power estimation for CMOS VLSI circuits using support vector machine

Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budget and to take the necessary steps for the reduction of power consumption. Over the years, most of the approaches were designed to estimate the power usage, however, most of the conventional techniques are time consuming, resource-intensive and largely manual. Machine learning techniques have received much attention in many of the engineering applications and are capable for modelling the complex systems through historical data. Hence, in this work on chip-based power estimation for complementary metal-oxide-semiconductor (CMOS) VLSI using support-vector machine (SVM) is presented to estimate the power. The SVM is employed to estimate the usage of power at runtime. The performance of this model is evaluated in terms of Power usage, delay, data accuracy and error rate.

Design and optimization of high electron mobility transistor with high-k dielectric material integration

We have developed and simulated a high electron mobility transistor (HEMT) operating in the 5 nm regime. This HEMT uses hafnium oxide (HfO2), a high-k dielectric material, to create an undoped region (UR) beneath the gate. While the gate and undoped regions share equal thickness, the channel length differs. This innovative undoped under the gate dielectric HEMT design mitigates the maximum electric field (V) within the channel area, leading to a significant increase in drain current. The utilization of a high-k dielectric in the HEMT structure results in a saturated Ion current that is 60% higher compared to conventional structures. Specifically, we use an AlGaN/GaN/SiC-based HEMT with an intrinsic section below the gate, using HfO2 as the high-k dielectric substantial, for applications requiring high power and high-frequency power amplifiers. Compare this advanced HEMT design to conventional HEMTs and you will see improved conductivity, a greater drain current (Id), a 54% increase in transconductance (Gm), and a lower on-resistance (Ron). Additionally, advancements in the electric field in the Y direction are seen. This HEMT structure exhibits superior performance compared to alternative materials analyzed. The integration of AlGaN/GaN materials in HEMTs opens up extensive opportunities in the realms of radio frequency very large-scale integration (VLSI) and power electronics.

Development of Power-Delay Product Optimized ASIC-Based Computational Unit for Medical Image Compression

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.

GaAs-on-insulator based vertical heterojunction tunnel FET: proposal and analysis for VLSI circuit applications

This work analyses the Gallium Arsenide (GaAs)-on-insulator based vertical heterojunction tunnel FET with Gallium Antimonide (GaSb) as source material and GaAs as channel/drain material (GaSb/GaAs VTFET) to enhance the performance of the device and is compared with the Silicon-based VTFET. Silvaco Atlas TCAD tool is employed to perform numerical calculations. Tentative fabrication process flow of GaSb/GaAs VTFET is presented. GaSb is a low bandgap material that enhances the tunneling of charge carriers at source-channel heterojunction. GaSb/GaAs VTFET device outperforms Si-based VTFET in terms of electrical performance metrics such as ON-state current (ION), and ION/IOFF increases by a factor of 11 and 270 respectively; whereas OFF-state current (IOFF), subthreshold swing (SS), threshold voltage (VT) and drain-induced barrier lowering (DIBL) reduce by 95.98%, 39.36%, 17.14% and 29.17% respectively. Further, analog/RF and linearity/distortion performance analysis is carried out. GaSb/GaAs VTFET has improved analog/RF performances in terms of cut-off frequency (fT), gain-bandwidth product (GBP), transit time (τ), device efficiency (DE), transconductance frequency product (TFP) and suppressed distortions in compare to Si-based VTFET. Finally, GaSb/GaAs VTFET is evaluated for process variations and designing digital inverter and common source amplifier circuits. The Look-up-table (LUT) based Verilog-A model within the CADENCE tool has been employed to scrutinize the transient responses of inverter and common source amplifier circuits. Unity gain frequency and 3-dB bandwidth obtained for GaSb/GaAs VTFET amplifier are 15 GHz and 5.97 GHz. Therefore, this work presents GaSb/GaAs VTFET’s strong candidature for analog and digital VLSI circuit designing.

Certain investigation on hybrid neural network method for classification of ECG signal with the suitable a FIR filter

The Electrocardiogram (ECG) records are crucial for predicting heart diseases and evaluating patient’s health conditions. ECG signals provide essential peak values that reflect reliable health information. Analyzing ECG signals is a fundamental technique for computerized prediction with advancements in Very Large-Scale Integration (VLSI) technology and significantly impacts in biomedical signal processing. VLSI advancements focus on high-speed circuit functionality while minimizing power consumption and area occupancy. In ECG signal denoising, digital filters like Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) are commonly used. The FIR filters are preferred for their higher-order performance and stability over IIR filters, especially in real-time applications. The Modified FIR (MFIR) blocks were reconstructed using the optimized adder-multiplier block for better noise reduction performance. The MIT-BIT database is used as reference where the noises are filtered by the MFIR based on Optimized Kogge Stone Adder (OKSA). Features are extracted and analyzed using Discrete wavelet transform (DWT) and Cross Correlation (CC). At this modern era, Hybrid methods of Machine Learning (HMLM) methods are preferred because of their combined performance which is better than non-fused methods. The accuracy of the Hybrid Neural Network (HNN) model reached 92.3%, surpassing other models such as Generalized Sequential Neural Networks (GSNN), Artificial Neural Networks (ANN), Support Vector Machine with linear kernel (SVM linear), and Support Vector Machine with Radial Basis Function kernel (SVM RBF) by margins of 3.3%, 5.3%, 23.3%, and 24.3%, respectively. While the precision of the HNN is 91.1%, it was slightly lower than GSNN and ANN but higher than both SVM linear and SVM -RBF. The HNN with various features are incorporated to improve the ECG classification. The accuracy of the HNN is switched to 95.99% when the DWT and CC are combined. Also, it improvises other parameters such as precision 93.88%, recall is 0.94, F1 score is 0.88, Kappa is 0.89, kurtosis is 1.54, skewness is 1.52 and error rate 0.076. These parameters are higher than recently developed models whose algorithms and methods accuracy is more than 90%.

Design and implementation of a nano-scale high-speed multiplier for signal processing applications

Digital signal processing (DSP) is an engineering field involved with increasing the precision and dependability of digital communications and mathematical processes, including equalization, modulation, demodulation, compression, and decompression, which can be used to produce a signal of the highest caliber. To execute vital tasks in DSP, an essential electronic circuit such as a multiplier plays an important role, continually performing tasks such as the multiplication of two binary numbers. Multiplier is a crucial component utilized to implement a wide range of DSP tasks, including convolution, Fourier transform, discrete wavelet transforms (DWT), filtering and dithering, multimedia information processing, and more. A multiplier device includes a clock and reset buttons for more flexible operational control. Each digital signal processor constitutes a multiplier unit. A multiplier unit functions entirely autonomously from the central processing unit (CPU); consequently, the CPU is burdened with a significantly reduced amount of work. Since DSP algorithms must constantly carry out multiplication tasks, the employment of a high-speed multiplier to execute fast-speed filtering processes is vital. The previous multipliers had lots of weaknesses, such as high energy, low speed, and high area, because they implemented this necessary circuit based on traditional technology such as complementary metal-oxide semiconductor (CMOS) and very large-scale integration (VLSI). To solve all previous drawbacks in this necessary circuit, we can use nanotechnology, which directly affects the performance of the multiplier and can overcome all previous issues. One of the alternative nanotechnologies that can be used for designing digital circuits is quantum dot cellular automata, which is high speed, low area, and low power. Therefore, this manuscript suggests a quantum technology-based multiplier for DSP applications. In addition, some vital circuits, such as half adder, full adder, and ripple carry adder (RCA), are suggested for designing a multiplier. Moreover, a systolic array, accumulator, and multiply and accumulate (MAC) unit are proposed based on the quantum technology-based multiplier. Nonetheless, each of the suggested frameworks has a coplanar configuration without rotated cells. The suggested structure is developed and verified utilizing the QCADesigner 2.0.3 tools. The findings showed that all circuits have no complicated configuration, including a higher number of quantum cells, latency, and an optimum area.

A Low Complexity Cooperative Spectrum Sensor for Cognitive –Radio Network Based on Approximate Computing

With the rapid growth of new wireless technologies, the issue of spectrum scarcity is becoming more prominent due to the limited availability of radio spectrum. Unutilized spectrum bands designated for primary users are known as spectrum holes or white spaces. Assigning these white spaces to secondary users can enhance spectrum utilization. Dynamic spectrum access is crucial for sharing licensed spectrum with secondary users, as opposed to static allocation policies which impede effective spectrum utilization. Spectrum sensing aims to detect licensed users in the spectrum to prevent interference from secondary users. Approximate computing has emerged as a strategy to enhance efficiency by leveraging the fault resilience of various applications. It introduces trade-offs in design optimizations, allowing for significant reductions in VLSI circuit area and energy consumption. A cooperative spectrum-sensing (CSS) algorithm based on approximate computing for cooperative cognitive-radio networks is proposed to reduce computational complexity for efficient hardware design while maintaining detection performance. The hardware-efficient architecture of the cooperative spectrum sensor (CSR) based on the CSS algorithm, combined with resource-sharing architectural optimization, outperforms existing implementations by occupying less area, achieving shorter sensing times, and displaying superior hardware efficiency. Keywords—Approximate Computing, Cooperative Spectrum Sensor(CSR), very-large scale integration(VLSI)