On-chip based power estimation for CMOS VLSI circuits using support vector machine

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Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budget and to take the necessary steps for the reduction of power consumption. Over the years, most of the approaches were designed to estimate the power usage, however, most of the conventional techniques are time consuming, resource-intensive and largely manual. Machine learning techniques have received much attention in many of the engineering applications and are capable for modelling the complex systems through historical data. Hence, in this work on chip-based power estimation for complementary metal-oxide-semiconductor (CMOS) VLSI using support-vector machine (SVM) is presented to estimate the power. The SVM is employed to estimate the usage of power at runtime. The performance of this model is evaluated in terms of Power usage, delay, data accuracy and error rate.