Very Large Scale Integration Technology Research Articles

NBTI Effect Survey for Low Power Systems in Ultra-Nanoregime

Background: Electronic device scaling with the advancement of technology nodes maintains the performance of the logic circuits with area benefit. Metal oxide semiconductor (MOS) devices are the fundamental blocks for building logic circuits. Area minimization with higher efficiency of the circuits motivates the researchers of very large-scale integration (VLSI) design. Moreover, the reliability of digital circuits is one of the biggest challenges in VLSI technology. A major issue in reliability is negative bias temperature instability (NBTI) degradation. NBTI affects the efficiency and reliability of electronic devices Methods: This paper presents a review of NBTI physical-based mechanisms. NBTI's impact on VLSI circuits and techniques has been studied to mitigate and compensate for the effect of NBTI. Results: This review paper presents an idea to relate the NBTI and leakage mitigation techniques. This study gives an overview of the efficiency, complexity, and overhead of NBTI mitigation techniques and methodologies. Conclusion: This survey provides a brief idea about NBTI degradation by using reliability simulation. Moreover, the extensive aging effect is discussed in the paper.

Biaxial Piezoelectric MEMS Mirrors with Low Absorption Coating for 1550 nm Long-Range LIDAR.

This paper presents the fabrication and characterization of a biaxial MEMS (MicroElectroMechanical System) scanner based on PZT (Lead Zirconate Titanate) which incorporates a low-absorption dielectric multilayer coating, i.e., a Bragg reflector. These 2 mm square MEMS mirrors, developed on 8-inch silicon wafers using VLSI (Very Large Scale Integration) technology are intended for long-range (>100 m) LIDAR (LIght Detection And Ranging) applications using a 2 W (average power) pulsed laser at 1550 nm. For this laser power, the use of a standard metal reflector leads to damaging overheating. To solve this problem, we have developed and optimised a physical sputtering (PVD) Bragg reflector deposition process compatible with our sol-gel piezoelectric motor. Experimental absorption measurements, performed at 1550 nm and show up to 24 times lower incident power absorption than the best metallic reflective coating (Au). Furthermore, we validated that the characteristics of the PZT, as well as the performance of the Bragg mirrors in terms of optical scanning angles, were identical to those of the Au reflector. These results open up the possibility of increasing the laser power beyond 2W for LIDAR applications or other applications requiring high optical power. Finally, a packaged 2D scanner was integrated into a LIDAR system and three-dimensional point cloud images were obtained, demonstrating the scanning stability and operability of these 2D MEMS mirrors.

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

This paper aims to present a unified overview of the main Very Large-Scale Integration (VLSI) implementation solutions of forward and inverse discrete sine transforms using systolic arrays. The main features of the most important solutions to implement the forward and inverse discrete sine transform (DST) using systolic arrays are presented. One of the central ideas presented in the paper is to emphasize the advantages of using regular and modular systolic array computational structures such as cyclic convolution, circular correlation, and pseudo-band correlation in the VLSI implementation of these transforms. The use of such computational structures leads to architectures well adapted to the features of VLSI technologies, with an efficient use of the hardware structures and a reduced I/O cost that helps avoiding the so-called I/O bottleneck. With the techniques presented in this review, we have developed a new VLSI implementation of the DST using systolic arrays that allow efficient hardware implementation with reduced complexity while maintaining high-speed performances. Using a new restructuring input sequence, we have been able to efficiently reformulate the computation of the forward DST transform into a special computational structure using eight short quasi-cycle convolutions that can be computed with low complexity and where some of the coefficients are identical. This leads to a hardware structure with high throughput. The new restructuring sequence is the use of the input samples in a natural order as opposed to previous solutions, leading to a significant reduction of the hardware complexity in the pre-processing stage due to avoiding a permutation stage to reverse the order. Moreover, the proposed VLSI architecture allows an efficient incorporation of the obfuscation technique with very low overheads.

Mixed analog–digital method of designing a heterogeneous network with the desired collective behavior and rapid convergence

Among many advances given by the diffusive coupling on the synchronization problem, recently a design method for a continuous-time heterogeneous network with the desired collective behavior has been developed. Meanwhile, by its use of high-gain, implementation issues arise in discrete-time frameworks. The goal of this paper is thus to introduce a simple scheme that follows the philosophy of Carver Mead, a pioneer of VLSI (Very Large Scale Integration) technology, that removes those implementation issues. In the end, we utilize what corresponds to derivative consensus in continuous-time, which can be realized by, for instance, an analog electric circuit. This provides a mixed analog–digital method of designing a heterogeneous network with the desired collective behavior and rapid convergence.

Low power design methodology in quantum-dot cellular automata

The signal distribution network (SDN) in VLSI (Very Large Scale Integration) technology consumes enormous power and layout area among different components. In this article, an extensive focus has been given to designing low-power interconnection in QCA technology. Revolving door elimination techniques, a new crossover methodology, and a circuit without fixed polarized cells are proposed in this research work to make an energy-efficient QCA circuit. The revolving door elimination technique provides us almost 50% energy efficiency over the standard crossover technique. The proposed signal distribution network (SDN) methodology encountered 47% area and nearly 15% energy benefits concerning previously reported SDN techniques. New methodologies are implemented on different nano-communication and computing circuits like XOR gate, odd-even parity generator, priority encoder, decoder, pseudo-random number generator (PRNG) to verify the functionality of proposed methodologies.

An Investigation for the Negative-Bias Temperature Instability Aware CMOS Logic

Background: Scaling of the dimensions of semiconductor device plays a very important role in the advancement of Very Large-Scale Integration (VLSI) technology. There are many advantages of scaling in VLSI technology such as increment in the speed of the device and less area requirement of the device. Aggressive device scaling causes some limitations in the form of short channel effects which produce large leakage current. Large leakage current harms the characteristics of the device and affects the reliability of the device. Objective: The most important and popular reliability issue in Deep Sub Micron (DSM) regime is Negative- Bias Temperature Instability (NBTI). NBTI effect increases the threshold voltage of p-channel Metal Oxide Semiconductor (PMOS) device over the time and affects the different characteristics of the device. As a result, circuit delay exceeds the design specification and there may be timing violations or logic failure. Different performance parameters are observed under NBTI effect for different logic gates. Methods: This paper presents an impact of NBTI at 22nm Berkeley short-channel IGFET model4 (BSIM4) Predictive Technology Model (PTM) for Complementary Metal Oxide Semiconductor (CMOS) logic gates. Reliability simulations are utilized to evaluate the amount of gradual damage in PMOS device due to NBTI effect. Results : The impact of NBTI degradation is checked for various CMOS logic gates using Mentor Graphics’s Eldo circuit simulator. Output voltage and drain current are reducing over the time under NBTI effect. Conclusion: NBTI degradation increases the threshold voltage of PMOS device over time and affects the different characteristics of the device.

Design and Analysis of CMOS Phase Lock Loop (PLL) Using VLSI Technology

Abstract: This paper proffers comparative research of Complementary MOSFET (CMOS) of the Phase Lock Loop (PPL) circuit. Our approach is based on hybrid design Phase Lock Loop (PLL) circuits combined in a single unit. A phase-locked loop (PLL) is used in space communication for synchronization purposes also very useful in time to digital converters and in instrumentation engineering. A phased lock loop (PLL) is a control system that makes an output signal whose frequency depends on the input phase difference. The phase detector takes the phase of an input signal and compares it with the phase procured from its output oscillator regulates the frequency of its oscillator to manage the phase matches. Different techniques like analogue and digital simulation with the help of mathematical/logical connections are found in Research to create the Phase Locked Loop (PLL). This limitation can be overcome by replicating the circuit block whose supply voltage is being reduced to manage the same throughout. This paper includes design features for low power phase-locked loop using Very-large-scale integration (VLSI) technology. The signal from the phase detector controls the oscillator in a feedback loop. As such: an operational device the PLL has a wide range of applications in computers sciences, telecommunication, and electronic system applications; we aim to design and examine the phase lock loop circuit in multiple technologies and examine their power capacity. By using the hybrid structure of NMOS and PMOS, here we have achieved the circuit of Phase Lock Loop (PLL) using VLSI technology. Keywords: Technology, CMOS, Phase lock loop, Micro wind, Voltage control oscillator, VLSI technology.

Transistors based on two-dimensional materials for future integrated circuits

Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies.

An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach

This paper proposes a time-domain analog calculations model based on a pulse-width modulation (PWM) approach for neural network calculations including weighted-sum or multiply-and-accumulate calculation and rectified-linear unit operation. We also propose very-large-scale integration (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, our circuits use transient operation in charging/discharging processes to capacitors through resistors. Since the circuits calculate multiple weighted-sums by charging a capacitance, they can be operated with extremely low energy consumption. However, because a relatively long time constant is required to guarantee calculation resolution in the time domain, they have to use very high-resistance devices, on the order of giga-ohms. We designed, fabricated, and tested a proof-of-concept complementary metal-oxide-semiconductor (CMOS) VLSI chip using a 250-nm fabrication technology to verify weighted-sum operation based on the proposed model with binary weights and PWM input signals, which realizes the BinaryConnect model. In the chip, memory cells of static-random-access memory (SRAM) are used for synaptic connection weights. High-resistance operation was realized by using the subthreshold operation region of MOS transistors, unlike in the ordinary in-memory-computing circuits. We evaluated the energy efficiency and temperature characteristics by measurement using the fabricated chip, where the highest energy efficiency for the weighted-sum calculation was 300 TOPS/W (Tera-Operations Per Second per Watt). The effects by a temperature change can be compensated for by adjusting the bias voltage. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible.

Programmable logic devices – key components for today’s and tomorrow’s electronic-based systems

Since their introduction in the 1970s, Programmable Logic Devices (PLDs) evolved from implementing small glue-logic designs to large, configurable multi-processor Systems-on-Chip (SoC). Today’s most prominent PLD technology, known as FPGA (Field-Programmable Gate Array), is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME-dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non-Recurring Engineering) costs of ASICs (Application-Specific Integrated Circuits). This work outlines how today’s and future electronic-based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien.

Analysis and minimization of crosstalk noise in copper interconnects for high-speed VLSI circuits

Due to the rapid advances of technologies, the scaling of parameters are decreasing. In VLSI (Very Large Scale Integration) technology, the feature size of integrated circuits (IC) has driving reduced in terms of power, speed, area and cost characteristics. The decreasing the sizes in sub-quarter microns, spacing between the components on-chip VLSI design and the signal switching time in terms of pico seconds or even less. As a result, the signal integrity (SI) issues are occurring at higher frequencies and high data rates. The evaluation of crosstalk noise between the coupled interconnect is one of the prominent issue in designing of high-speed ICs. In this paper, investigated the crosstalk noise of coupled copper (Cu) interconnect models with analytically at 32 nm technology nodes. Also, investigated the crosstalk reduction with shield insertion technique and increasing physical spacing between the coupled lines. For the low power VLSI applications, the shield insertion technique is preferable for reducing the crosstalk effects in coupled interconnects.

Optimization and Scaling of Ge-Pocket TFET

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage ( ${V} _{\textsf {DD}}$ ). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current ( ${I} _{\textsf {on}}$ ) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length ( ${L} _{\textsf {gate}}$ ) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications.

High resolution TEM analysis of focused ion beam amorphized regions in single crystal silicon—A complementary materials analysis of the teardrop method

The predominant challenge of nanomachining by focused ion beam (FIB) is the generational down-scaling of minimum dimensions of cutting-edge technologies such as very large scale integration (VLSI) process technology. To keep pace with feature size reduction, the state of the art FIB beam profiles must also shrink proportionally. This requirement for FIB profile shrinking necessitates tests that analyze FIB profiles and their characteristics. With such tests in hand, the suitability for VLSI technology applications may be specified, developed, and qualified. The authors present herein various aspects and some fine details of the recently improved beam profile analysis, aka “teardrop” test. This test is based on obtaining real beam characteristics by analyzing amorphization traces produced by scanning the beam in question over a [001] Si single crystal sample, in a series of lines of increasing doses, followed by thorough analysis procedure. To derive the most accurate beam characteristics, the amorphized r...

Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees

Electromigration (EM) in very large scale integration (VLSI) interconnects has become one of the major reliability issues for current and future VLSI technologies. However, existing EM modeling and analysis techniques are mainly developed for a single wire. For practical VLSI chips, the elemental EM reliability unit called interconnect tree is a multibranch interconnect segment consisting of a continuously connected, highly conductive metal (Cu) lines terminated by diffusion barriers and located within the single level of metallization. The EM effects in those branches are not independent and have to be considered simultaneously. In this paper, we demonstrate, for the first time, a first principle-based analytical solution of this problem. We have derived the analytical expressions describing the hydrostatic stress evolution in several typical interconnect trees: 1) the straight-line three-terminal wires; 2) the T-shaped four-terminal wires; and 3) the cross-shaped five-terminal wires. The new approach solves the stress evolution in a multibranch tree by de-coupling the individual segments through the proper boundary conditions (BCs) accounting the interactions between different branches. By using Laplace transformation technique, analytical solutions are obtained for each type of the interconnect trees. The analytical solutions in terms of a set of auxiliary basis functions using the complementary error function agree well with the numerical analysis results. Our analysis further demonstrates that using the first two dominant basis functions can lead to 0.5% error, which is sufficient for practical EM analysis.

Low Power-Area Design of Full Adder Using Self Resetting Logic With GDI Technique

Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area ,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs have been proposed over last few years with different logic styles. To reduce the power consumption several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets, charge sharing by parasitic components while connecting source and drain of CMOS transistors There are situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic which are widely used in dynamic logic circuits. Overall performance of various adder designs is evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V. On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low PDP among its counterparts.

A novel design of quantum dot cellular automata 5-input majority gate with some physical proofs

In a very fast growth of very large scale integration (VLSI) technology, it is the demand and necessity of time to achieve a reliable design with low power consumption. The quantum dot cellular automata (QCA), due to its small size, very high switching speed and ultra-low power consumption, can be an alternative for CMOS VLSI technology at nano-scale level. A novel 5-input majority gate for QCA is proposed in this paper which is suitable for designing QCA circuits in a simple and symmetric manner. Based on it, we have designed a full adder with some physical proofs provided for the functions of Boolean techniques to verify the functionality of the proposed devices properly. For computer simulations analysis, functionality of full adder has been checked using the QCADesigner tool. Both simulation results and physical proofs confirm the usefulness of our proposed gate design for designing any digital circuit.

The Blue LED Nobel Prize: Historical context, current scientific understanding, human benefit

The Blue LED Nobel Prize: Historical context, current scientific understanding, human benefit

English

Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of integrated circuit technology. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost advantages in VLSI systems. There are, however, potential problems which may retard the effective use and growth of future VLSI technology. Among these is the problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. Because of the high device counts and limited input/output access that characterize VLSI circuits, conventional testing approaches are often ineffective and insufficient for VLSI circuits. .The vital role of primitive polynomials for designing PN sequence generators. The standard LFSR (linear feedback shift register) used for pattern generation may give repetitive patterns. Which are in certain cases is not efficient for complete test coverage. The LFSR based on primitive polynomial generates maximum-length PRPG.Built-in self-test (BIST) is a commonly used design technique that allows a circuit to test itself. BIST has gained popularity as an effective solution over circuit test cost, test quality and test reuse problems. In this paper we are presenting an implementation of a tester using VHDL

Toward 300 mm wafer-scalable high-performance polycrystalline chemical vapor deposited graphene transistors.

The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of "back end of the line" devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26,000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ∼ 74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm(2)/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobility observed here is ∼ 40% higher than the peak mobility values reported for single-crystalline graphene, a major advancement for polycrystalline graphene that can be readily manufactured. Intrinsic graphene features such as soft current saturation and three-region output characteristics at high field have also been observed on wafer-scale CVD graphene on which frequency doubler and amplifiers are demonstrated as well. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available.

Spike-Based Synaptic Plasticity in Silicon: Design, Implementation, Application, and Challenges

The ability to carry out signal processing, classification, recognition, and computation in artificial spiking neural networks (SNNs) is mediated by their synapses. In particular, through activity-dependent alteration of their efficacies, synapses play a fundamental role in learning. The mathematical prescriptions under which synapses modify their weights are termed synaptic plasticity rules. These learning rules can be based on abstract computational neuroscience models or on detailed biophysical ones. As these rules are being proposed and developed by experimental and computational neuroscientists, engineers strive to design and implement them in silicon and en masse in order to employ them in complex real-world applications. In this paper, we describe analog very large-scale integration (VLSI) circuit implementations of multiple synaptic plasticity rules, ranging from phenomenological ones (e.g., based on spike timing, mean firing rates, or both) to biophysically realistic ones (e.g., calcium-dependent models). We discuss the application domains, weaknesses, and strengths of various representative approaches proposed in the literature, and provide insight into the challenges that engineers face when designing and implementing synaptic plasticity rules in VLSI technology for utilizing them in real-world applications.