Very Large Scale Integration Implementation Research Articles

Hybrid shared‐memory and message‐passing multiprocessor system‐on‐chip for UWB MAC layer

Ultra-wideband (UWB) is a well-known radio technology whose media access control (MAC) protocol, WiMedia MAC, has considerable potential to ensure high-speed and high-quality data communication for wireless personal area networks. However, these benefits involve a heavy computational workload, thereby posing a challenge to the conventional very-large-scale integration (VLSI) approach in terms of providing the required performance and power efficiency. Therefore, this study aims to optimise the VLSI implementation of the WiMedia MAC system by proposing a hybrid shared-memory and message-passing multiprocessor system-on-chip (MPSoC) architecture. The proposed solution combines the state-of-the-art MPSoC technology and application-specific instruction-set processor techniques to (i) accelerate the MAC protocol at task level by using parallel processing, (ii) enable the using of custom instructions to optimise the inter-processor communication by using an explicit message passing mechanism, and (iii) ease the implementation process by using a high-level software/hardware co-design methodology. The proposed platform is implemented on both system-level SystemC for architecture exploration and standard-cell technology for future chip implementation. Experimental results show that the proposed hybrid MPSoC architecture achieves 24% performance improvement and 22% power savings over the conventional shared-memory-only one.

Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display System

High-quality and cost-efficient image upscaling design is very important for many real-time video processing applications, especially when the display panel resolution reaches ultrahigh definition. Compared with New Edge-Directed Interpolation (NEDI) based implicit edge directional upscaling, explicit methods require less computational resource and more easily reach real-time performance, especially when the required image definition and upscaling ratio are very high. Nevertheless, the investigation of applications of explicit methods in video processing systems remains largely missing arguably because it is commonly believed that explicit edge-directed interpolation tends to introduce unexpected artifacts because of inaccurate detection and hence its image quality is relatively poor. This paper proposes an explicit edge-directed adaptive interpolation method that leverages more sophisticated edge detection and orientation estimation algorithms to avoid misinterpolation, thereby providing similar or even better image quality than those with implicit methods. Targeting the real-time 4K video display system, the proposed edge-directed image upscaling algorithm is further implemented with an efficient very-large-scale integration (VLSI) architecture. The experimental results demonstrate that the proposed interpolation algorithm outperforms previous explicit and implicit edge-directed methods in both objective and subjective tests. The presented VLSI implementation further demonstrates that the maximum output video sequence of the proposed interpolation method can reach 4k × 2k@60 Hz with a reasonable hardware cost.

VLSI implementation of an ultra-low-cost and low-power image compressor for wireless camera networks

In this paper, a novel hardware-oriented color image compression algorithm based on digital halftoning and block truncation coding (BTC) techniques is proposed for very large-scale integration (VLSI) implementation. The proposed technique consists of a threshold generator, a bitmap generator, a BTC training module, a predictor, and a signed Golomb–Rice coding module. Because the wireless camera network is developed for perceiving, measuring, and collecting information from the environment, each camera sensing node should be designed to achieve low cost, small size, high compression rates, and low power consumption. Hence, a novel low-complexity, high-performance, transform-free, hardware-oriented color image compression algorithm based on digital halftoning and BTC is proposed. In order to achieve the performance of compressing images in real time, the proposed color image compression algorithm was realized by a VLSI technique. The VLSI architecture in this work contains only 8.1-k gate counts, and the core area is 81,000 μm2 synthesized using a TSMC 0.18-μm CMOS process. The operating frequency of this work is 100 MHz and consumes 2.91 mW, which is efficient to develop wireless electronic systems with the demand of color image compression in real time. Compared with JPEG- and JPEG-LS-based designs, this work reduces gate counts by at least 71.1 % and power consumption by 53 % and only requires a one-line-buffer memory.

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck–boost dc–dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.

Unified VLSI architecture for photo core transform used in JPEG XR

A unified very large-scale integration (VLSI) architecture with butterflies that can perform photo core transform (PCT) in JPEG XR image compression is presented. The proposed architecture can achieve the unified architecture design, which supports the three elemental operations of PCT, and it has the characteristics of lower hardware cost, shorter critical path, lower power consumption, more efficient hardware utilisation and regular structure for VLSI implementation. Finally, the implementation on Altera field programmable gate array (FPGA) devices validates the effectiveness of the design.

A Digital Liquid State Machine With Biologically Inspired Learning and Its Application to Speech Recognition.

This paper presents a bioinspired digital liquid-state machine (LSM) for low-power very-large-scale-integration (VLSI)-based machine learning applications. To the best of the authors' knowledge, this is the first work that employs a bioinspired spike-based learning algorithm for the LSM. With the proposed online learning, the LSM extracts information from input patterns on the fly without needing intermediate data storage as required in offline learning methods such as ridge regression. The proposed learning rule is local such that each synaptic weight update is based only upon the firing activities of the corresponding presynaptic and postsynaptic neurons without incurring global communications across the neural network. Compared with the backpropagation-based learning, the locality of computation in the proposed approach lends itself to efficient parallel VLSI implementation. We use subsets of the TI46 speech corpus to benchmark the bioinspired digital LSM. To reduce the complexity of the spiking neural network model without performance degradation for speech recognition, we study the impacts of synaptic models on the fading memory of the reservoir and hence the network performance. Moreover, we examine the tradeoffs between synaptic weight resolution, reservoir size, and recognition performance and present techniques to further reduce the overhead of hardware implementation. Our simulation results show that in terms of isolated word recognition evaluated using the TI46 speech corpus, the proposed digital LSM rivals the state-of-the-art hidden Markov-model-based recognizer Sphinx-4 and outperforms all other reported recognizers including the ones that are based upon the LSM or neural networks.

VLSI implementation of coupled MRF model using pulse‐coupled phase oscillators

Efficient pixel-parallel image processing using a pulse-coupled phase oscillator model and its very large scale integration (VLSI) implementation is proposed. A processing unit that corresponds to a pixel of an image transmits spike pulses to other units, and updates its own analogue state value at timing when spikes come from other units. From a VLSI implementation point of view, this mechanism is suitable for very low-power operation because analogue buffers are unnecessary for data transmission. On the basis of this model, a VLSI image processor chip that performs a coupled Markov random field model for image region segmentation is designed and fabricated. A very low-power VLSI design has been achieved by the combination of an analogue oscillator and digital coupling function generator circuits with time-domain computation. The processing performance of the fabricated oscillator-based image processor chip using a 0.25 μm CMOS process has achieved 43.2 GOPS or 656 GOPS/W. Experiments using the fabricated chip have shown successful image region segmentation in one- and two-dimensional images.

English

A new very large scale integration (VLSI) algorithm for a 2𝑁-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. In the proposed method multiply the multipliers by using array multiplier and to add the co-efficients by using Carry Look-ahead Adder (CLA). In the proposed system we are reducing the area by using the array multiplier and Carry Look-ahead Adder (CLA). The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the sub expression sharing techniques that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.

VLSI Implementation of Segmentation of Single Channel ECG

In this paper the implementation of extraction of respiratory signal from ECG signal in very large scale integration (VLSI) using discrete wavelet transform (DWT) is discussed. The Indirect method to obtain the respiratory signal from ECG can benefit both respiratory and cardiac activities. The accuracy of the extracted respiratory signal will be high. The implementation is based on bit serial approach (BS) which substitute multiply and accumulate operations. BS provides a multiplication-free method for calculating inner products of fixed-point data. But increase in filter order leads complexity. Here we propose high-speed and low power architecture. The proposed method is implemented in hardware description language and verified via simulation. The proposed architecture scheme yields significantly reduced complexity, less area and high speed features.

RESOURCEFUL FAST DHT ALGORITHM FOR VLSIIMPLEMENTATION BY SPLIT RADIX ALGORITHM

A new very large scale integration (VLSI) algorithmic rule for a 2 N -length discrete hartley transform (DHT) that may be expeditiously enforced on a extremely standard and parallel VLSI design having a regular structure is given. The DHT algorithmic rule may be expeditiously split on many parallel elements that may be dead at the same time. Moreover, the planned algorithmic rule is compatible for the subexpression sharing technique that may be used to significantly reduce the hardware complexness of the highly parallel VLSI implementation.

Efficient VLSI architecture for interpolation decoding of Hermitian codes

A fast, area efficient very large scale integration (VLSI) architecture is proposed for a unique decoding algorithm of Hermitian codes which was presented recently by Lee and O'Sullivan from an interpolation perspective. The algorithm iteratively computes the sent message through a majority voting procedure by using the Grobner bases of interpolation modules. The algorithm has a regular structure which makes it suitable for VLSI implementation. The circuitry is simplified as the decoding algorithm directly gives the message word at the end of the decoding algorithm without separate steps like Chien search and Forney's formula. In terms of hardware requirements, for the widely used high rate Hermitian codes, the Lee–O'Sullivan algorithm is q times faster than Kotters algorithm with the same space complexity of O(q 4). Further speed improvements can be achieved by combining the main idea of Guruswami list decoding with the Lee–O'Sullivan algorithm. In terms of hardware, the addition of this concept, will further reduce the running time of the algorithm and make the circuitry about two times faster than the original Lee–O'Sullivan algorithm. The implementation results for both the Koetter and the Lee–O'Sullivan algorithms on Xilinx Virtex-5 shows that the proposed decoder can be operated at higher clock frequency with almost same area complexity.

VLSI Implementation of High Performance Optimized Architecture for Video Coding Standards

This study presents a fast search algorithm and its Very Large Scale Integration (VLSI) design to implement an Enhanced Diamond Search (EDS) of Block-based Motion estimation for video compression systems. The proposed algorithm reduces the number of search points with a slight increase in average Sum-of-Absolute Difference (SAD) per pixel and significant reduction in Peak Signal-to-Noise Ratio (PSNR) than the Full search (FS). The speed improvement ratio is 11.26%. A novel Motion Estimation (ME) algorithm is proposed in this study that exhibits some properties with potential to facilitate optimized VLSI implementation and to achieve high performance for real video sequences. The main characteristic of this proposed architecture is possessing of only five processing elements (PE) that are used to calculate minimum SAD by using efficient comparators and compressors. Simulation results indicate that our proposed architecture employs low power and processes the video data with high speed than existing architectures without significant change in the video quality.

A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture

A new very large scale integration (VLSI) algorithm for a 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> -length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing technique that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.

An Improved Low-cost Adaptive Bicubic Interpolation Arithmetic and VLSI Implementation

A novel scaling algorithm is proposed which consists of a bicubic interpolation and an adaptive sharpening filter. The proposed sharpening filter is added to mitigate the blurring effects existing in bicubic interpolation methods. We also verify the scaling quality by taking into account the adaptive technique. Furthermore, we present both the procedures of filtering before and after interpolation in order to reduce the overall computing time. Compared with the previous reported techniques, our method performs better in terms of both quantitative evaluation and visual quality. To achieve the goal of real time and low cost, we describe a pipelined very large scale integration (VLSI) architecture for the implementation of the algorithm. The VLSI architecture of our image scaling processor contains 695 LEs and yields a processing rate of about 165 MHz by using field-programmable gate array (FPGA) technology. Our proposed architecture reduces the amount of gates by 36.8% while achieves an average PSNR increase of 1.5 dB in image quality.

A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes

This paper highlights the implementation challenges faced by the current high performing error resilient joint source channel coding (JSCC) techniques based on the concept of soft-input soft-output (SISO) decoding of arithmetic codes (AC). Further, it proposes several efficient algorithmic and a very large scale integration (VLSI) architectural techniques to improve the throughput performance of SISO for JSCC. The VLSI hardware implementation of the proposed algorithm, when implemented on a 90 nm standard cells technology running at 588 MHz, achieves a decoding throughput of up to 2.63 Mbits/s capable of decoding QCIF format for video conferencing.

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing

Sparse signal recovery finds use in a variety of practical applications, such as signal and image restoration and the recovery of signals acquired by compressive sensing. In this paper, we present two generic very-large-scale integration (VLSI) architectures that implement the approximate message passing (AMP) algorithm for sparse signal recovery. The first architecture, referred to as AMP-M, employs parallel multiply-accumulate units and is suitable for recovery problems based on unstructured (e.g., random) matrices. The second architecture, referred to as AMP-T, takes advantage of fast linear transforms, which arise in many real-world applications. To demonstrate the effectiveness of both architectures, we present corresponding VLSI and field-programmable gate array implementation results for an audio restoration application. We show that AMP-T is superior to AMP-M with respect to silicon area, throughput, and power consumption, whereas AMP-M offers more flexibility.

Relaxed fault-tolerant hardware implementation of neural networks in the presence of multiple transient errors.

Reliability should be identified as the most important challenge in future nano-scale very large scale integration (VLSI) implementation technologies for the development of complex integrated systems. Normally, fault tolerance (FT) in a conventional system is achieved by increasing its redundancy, which also implies higher implementation costs and lower performance that sometimes makes it even infeasible. In contrast to custom approaches, a new class of applications is categorized in this paper, which is inherently capable of absorbing some degrees of vulnerability and providing FT based on their natural properties. Neural networks are good indicators of imprecision-tolerant applications. We have also proposed a new class of FT techniques called relaxed fault-tolerant (RFT) techniques which are developed for VLSI implementation of imprecision-tolerant applications. The main advantage of RFT techniques with respect to traditional FT solutions is that they exploit inherent FT of different applications to reduce their implementation costs while improving their performance. To show the applicability as well as the efficiency of the RFT method, the experimental results for implementation of a face-recognition computationally intensive neural network and its corresponding RFT realization are presented in this paper. The results demonstrate promising higher performance of artificial neural network VLSI solutions for complex applications in faulty nano-scale implementation environments.

Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture

In this paper, we propose a trellis-search based soft-input soft-output detection algorithm and its very large scale integration (VLSI) architecture for iterative multiple-input multiple-output (MIMO) receivers. We construct a trellis diagram to represent the search space of a transmitted MIMO signal. With the trellis model, we evenly distribute the workload of candidates searching among multiple trellis nodes for parallel processing. The search complexity is significantly reduced because the number of candidates is greatly limited at each trellis node. By leveraging the trellis structure, we develop an approximate Log-MAP algorithm by using a small list of largest exponential terms to compute the LLR (log-likelihood ratio) values. The trellis-search based detector has a fixed-complexity and is very suitable for parallel VLSI implementation. As a case study, we have designed and synthesized a trellis-search based soft-input soft-output MIMO detector for a 4 × 4 16-QAM system using a 1.08 V TSMC 65 nm technology. The detector can achieve a maximum throughput of 1.7 Gb/s with a core area of 1.58 mm2.

Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III

In this brief, a new efficient radix-2 fast algorithm for the computation of type-III discrete Hartley transform of length that has a small arithmetic cost and is well suited for a very large-scale integration (VLSI) implementation is presented. This recursive method requires a small number of arithmetic operations compared with existing methods, has a regular and simple computational structure, and can be easily implemented. A small number of arithmetic operations are achieved with the proposed algorithm as compared with existing algorithms. Moreover, the regular and simple computational structure and the existing parallelism of the proposed algorithm offer the possibility of an efficient fast parallel VLSI implementation.

Reduced-complexity column-layered decoding and implementation for LDPC codes

Layered decoding is well appreciated in low-density parity-check (LDPC) decoder implementation since it can achieve effectively high decoding throughput with low computation complexity. This work, for the first time, addresses low-complexity column-layered decoding schemes and very-large-scale integration (VLSI) architectures for multi-Gb/s applications. At first, the min-sum algorithm is incorporated into the column-layered decoding. Then algorithmic transformations and judicious approximations are explored to minimise the overall computation complexity. Compared to the original column-layered decoding, the new approach can reduce the computation complexity in check node processing for high-rate LDPC codes by up to 90% while maintaining the fast convergence speed of layered decoding. Furthermore, a relaxed pipelining scheme is presented to enable very high clock speed for VLSI implementation. Equipped with these new techniques, an efficient decoder architecture for quasi-cyclic LDPC codes is developed and implemented with 0.13 µm VLSI implementation technology. It is shown that a decoding throughput of nearly 4 Gb/s at a maximum of 10 iterations can be achieved for a (4096, 3584) LDPC code. Hence, this work has facilitated practical applications of column-layered decoding and particularly made it very attractive in high-speed, high-rate LDPC decoder implementation.