Very Large Scale Integration Implementation Research Articles

A VLSI Image Processing Algorithm for Biomedical Applications

The domain of signal processing that is dedicated to applications in the medical sector has shown phenomenal expansion over the course of the last decade. It’s possible that developments in fields such as computer-aided design (CAD), healthcare, and automated signal processing have played a key part in this expansion. As a result of the current COVID-19 epidemic, there is a greater need for biomedical signal analysis, and from an imaging point of view, biomedical research projects far exceed those that use more basic signal processing methodologies. The fundamentals of image processing and the processing of biological pictures have been the subject of a lot of studies, and the findings of these studies have shown a variety of possible applications in a variety of settings. A examination of the existing literature reveals that there are a limited number of solutions that are based on very large scale integration (VLSI). As a direct consequence of this, this chapter devotes a significant amount of its focus to the investigation of biological image processing, particularly in terms of its applications and VLSI implementations. It is hoped that researchers and investigators would find this useful in better preparing a solution to this issue so that it may be put into action. Following an analysis of the most recent developments in research, a number of possible directions for future research have been contemplated.

VLSI implementation of Kogge-Stone Adder for low-power applications

The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems. This study compares the latency, space, and energy used by the Kogge-Stone Adder after development and implementation in Xilinx Vivado using Verilog to those of the Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA). The results show that the KSA has a decrease in power consumption as well as improvements in high speed and area compaction when compared to the RCA and CLA.

A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design.

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved. We also propose several techniques to improve the performance on recognition tasks and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST and Fashion-MNIST datasets. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module

The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

This paper aims to present a unified overview of the main Very Large-Scale Integration (VLSI) implementation solutions of forward and inverse discrete sine transforms using systolic arrays. The main features of the most important solutions to implement the forward and inverse discrete sine transform (DST) using systolic arrays are presented. One of the central ideas presented in the paper is to emphasize the advantages of using regular and modular systolic array computational structures such as cyclic convolution, circular correlation, and pseudo-band correlation in the VLSI implementation of these transforms. The use of such computational structures leads to architectures well adapted to the features of VLSI technologies, with an efficient use of the hardware structures and a reduced I/O cost that helps avoiding the so-called I/O bottleneck. With the techniques presented in this review, we have developed a new VLSI implementation of the DST using systolic arrays that allow efficient hardware implementation with reduced complexity while maintaining high-speed performances. Using a new restructuring input sequence, we have been able to efficiently reformulate the computation of the forward DST transform into a special computational structure using eight short quasi-cycle convolutions that can be computed with low complexity and where some of the coefficients are identical. This leads to a hardware structure with high throughput. The new restructuring sequence is the use of the input samples in a natural order as opposed to previous solutions, leading to a significant reduction of the hardware complexity in the pre-processing stage due to avoiding a permutation stage to reverse the order. Moreover, the proposed VLSI architecture allows an efficient incorporation of the obfuscation technique with very low overheads.

VLSI Implementation of DENLMS Adaptive Filter for Biomedical Applications

Very Large Scale Integration (VLSI) implementation of the Delayed Error Normalized LMS (DENLMS) adaptive filter using a pipelined architecture is proposed and it can be used for biomedical applications. The proposed pipelined VLSI architecture increases the performance of adaptive filters by lowering the amount of time spent on critical path calculation. When compared to the current Error Normalized Least Mean Square (ENLMS) method for pipelining purposes, the DENLMS technique requires an additional delay element, and because of the delay element, the algorithm functions faster and more effective in low-power applications. The proposed pipelined architecture of the DENLMS filter, on the other hand, improves the efficiency while consuming less power overall. The cell leakage power reduction and total dynamic power reduction obtained by using the DENLMS filter are 31.8% and 33.5%, respectively, although the overall area of the filter has increased by 20.4%.

A study on VLSI implementation of image enhancement techniques

AbstractIn real‐time, the images captured are not always appreciable for visual perception. The quality of the image relies on the illumination condition. Contrast enhancement is required to improve the visual quality of the image. In this article, the image enhancement techniques that are adaptable for real‐time images are studied. Further, an investigation is done on implementing the image processing algorithms in very large‐scale integration (VLSI) hardware. As the image data are comparatively larger, the computational complexity and the memory requirement are more. From the study, the need for efficient computation of such image processing algorithms is realized. The efficient computation of image processing algorithms on hardware platforms, in particular on field programmable gate array (FPGA), is reviewed. As an experiment, the gamma‐transformation technique used for image enhancement is realized. Initially, the prototype is modeled using MATLAB, and then it is implemented using an FPGA.

Design and Implementation of High Performance PPSK demodulator in Biomedical Implant

Background/Objective: The important challenge for the realization of hearing aids is small size, low cost, low power consumption, and better performance, etc. Keeping these requirements in view this work concentrates on the VLSI (Very Large Scale Integrated) implementation of the analog circuit that mimics the PPSK (Passive Phase Shift Keying) demodulator with a low pass filter. Methodology: This research deals with RF Cochlear implant circuits and their data transmission. A PPSK modulator is used for uplink data transmission in biomedical implants with simultaneous power, data transmission. This study deals with the implementation of a PPSK demodulator with related circuits and a low pass filter which are used in cochlear implants consumes low power and operates at 14MHz frequency. These circuits are designed using FINFET 20nm technology with 0.4v DC supply voltage. Findings: The performance of the proposed design over the previous design is operating at low threshold voltage, reduces static leakage currents, and often observed greater than 30 times of improvement in speed performance Novelty: As the conventional design with the same supply voltage(0.4v) exhibit high power dissipation and delay and require more amount of time to demodulate the signal. Whereas the proposed FINFET based monostable circuit and PPSK demodulator with a low pass filter has proven better in terms of less delay and power dissipation and can transmit the data with less bit error rate in stipulated time. Keywords: Cochlear Implant (CI); Fin Field Effect Transistor (FINFET); Electrode Array; Back Telemetry; PPSK Demodulator

VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

This paper presents a low-cost and high-quality, hardware-oriented, two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image and video encoders. In order to reduce memory requirement and improve image quality, a novel Loeffler DCT based on a coordinate rotation digital computer (CORDIC) technique is proposed. In addition, the proposed algorithm is realized by a recursive CORDIC architecture instead of an unfolded CORDIC architecture with approximated scale factors. In the proposed design, a fully pipelined architecture is developed to efficiently increase operating frequency and throughput, and scale factors are implemented by using four hardware-sharing machines for complexity reduction. Thus, the computational complexity can be decreased significantly with only 0.01 dB loss deviated from the optimal image quality of the Loeffler DCT. Experimental results show that the proposed 2-D DCT spectral analyzer not only achieved a superior average peak signal–noise ratio (PSNR) compared to the previous CORDIC-DCT algorithms but also designed cost-efficient architecture for very large scale integration (VLSI) implementation. The proposed design was realized using a UMC 0.18-μm CMOS process with a synthesized gate count of 8.04 k and core area of 75,100 μm2. Its operating frequency was 100 MHz and power consumption was 4.17 mW. Moreover, this work had at least a 64.1% gate count reduction and saved at least 22.5% in power consumption compared to previous designs.

Low-power DSSS transmitter and its VLSI implementation

An interesting area of application in wireless data communication is direct-sequence spread spectrum (DSSS). Spread spectrum communication techniques make the signals more robust against interference and jamming. These are based on a concept that narrowband signal is scrambled before transmission in such a way that the signals occupy a much larger part of the radio frequency spectrum. As the digital and the analogue system components are required on the same substrate in today’s mixed-signal chips, the DSSS transmitter system is proposed to be implemented in field-programmable gate array (FPGA)–based platforms and application-specific integrated circuits (ASICs). With a low-power very large-scale integration (VLSI) architecture, sophisticated processing of wide-bandwidth DSSS systems can be exploited in FPGAs/ASICs. In this article, binary pseudo-noise (PN) sequences are generated using a low-power linear feedback shift register (LFSR) in order to spread transmit signals extensively. The proposed low-power design of LFSR and DSSS transmitter with implementation results is illustrated in this paper. Dynamic power dissipation of the proposed DSSS transmitter is reduced up to 15% and 15.6% when compared to the conventional LFSR and the Gold code–based systems respectively. The proposed hardware is implemented in 180-nm technology and operates at 15.36-MHz frequency.

A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box

In recent research, very large-scale integration (VLSI) design and its implementation plays a major role. It has been considered as compact and contains additional techniques. However, it undergoes security threats like differential power analysis (DPA) attacks, confidential information leakage, suspicious data insertion, brute force attacks, and other severe attacks. Hence, the cryptographic techniques that have been implemented to enhance the security level for VLSI devices is the focus of this survey. The symmetric cryptographic technique of advanced encryption standard (AES) is considered suitable for this security enhancement and it is an advanced encryption process, and so the intelligible data are transmitted in an unintelligible form to confuse the attackers and the data is securely transmitted without any interruption. Different techniques to implement the AES approaches in VLSI devices are analyzed. The dynamic S-box technique is also analyzed for key-dependent processes. The key-dependent S-box of block ciphers is more secure than a general fixed S-box. The strength of the cipher is increased by the usage of an S-box. A dynamic S-box, generated to be key-dependent and with a discrete logarithmic approach, enhanced the S-box nonlinearity. Several measures analyzed regarding security and complexity of nonlinear transformation of S-box improved. Hence, the AES algorithm with dynamic S-box makes the system dynamic, more nonlinear, and with an unbreakable architecture. In this review, it also identified that to implement nonlinear transformation in AES, an S-box component has been used. This survey has been provided as guidelines for VLSI architecture implementation in a more secure way with cryptographic algorithm of AES and a dynamic S-box.

Computation-efficient image watermarking architecture with improved performance

This work presents a computation efficient image watermarking very large-scale integration (VLSI) architecture with improved robustness and throughput. The computational complexity is reduced by the incorporation of integer DCT, whereas the throughput is improved by the implementation of a four-stage pipeline architecture. Further, in the present work, the secret watermark bits are inserted in the DCT low-frequency coefficients using a mean adaptive threshold value, which not only results in a minimum degradation to the host image quality but also increases the robustness of the proposed algorithm. The VLSI implementation of the proposed algorithm using CadenceⓇ circuit design tools in 180 nm technology demonstrates an overall power consumption of 4.47 mW and a throughput of 2.5 Gbps that are better than the results reported in the literature.

Lossless CFA Image Compression Chip Design for Wireless Capsule Endoscopy

This paper presents a hardware-oriented lossless color filter array (CFA) image compression algorithm for very-large-scale integration (VLSI) circuit design. In order to achieve high performance, low complexity and low memory requirement, a novel lossless CFA image compression algorithm based on JPEG-LS is proposed for the VLSI implementation. A previous study showed the usage of a context table with its memory consuming more than 81% of the chip area for a JPEG-LS encoder design. The proposed algorithm implements a JPEG-LS-based lossless image compression algorithm that eliminates the use of the context technique and its memory in order to reduce the chip area while still maintaining its high performance. The proposed algorithm includes a pixel restoration, an adaptive Golomb-Rice parameter prediction and an improved Golomb-Rice coding technique. This paper was realized using a 0.18μ m CMOS process with synthesized gate counts and core area of 4.8 k and 57,625μm 2 , respectively. The synthesized operating frequency of this design reached 200 MHz by using a pipeline scheduling technique. Compared with the previous JPEG-LS-based designs, this paper reduced the gate count to at least 28% and increased the average compression ratio by over 17.15% using the video endoscopy images from the Gastro Gastroenterologist Hospital.

VLSI Implementation for an Adaptive Haze Removal Method

In the real-time outdoor application of computer vision-based systems, haze removal, a preprocessing technique that can recover clear images from foggy ones, is necessary for object detection. Therefore, in this paper, an efficient haze removal method suitable for hardware design is proposed to obtain high quality fog-free images. Based on the atmosphere scattering model and the dark channel prior method, the atmospheric light of the whole image and the transmission map could be extracted. These are important and necessary parameters of the recovery model. Instead of using single global atmospheric light to restore foggy image, a local atmospheric light estimation method is applied in the proposed design to achieve optimal results. To ensure that the overall image is consistent without block artifacts, dynamic adjustment of local atmospheric light is made based on global atmospheric light. Additionally, to obtain a transmission map, a refined estimation method is performed to ease the halo effect. In terms of both quantitative and qualitative evaluations, the simulation results indicate that the proposed design exhibits superior performance without color oversaturation and distortion. To meet the requirements of real-time applications, a six-stage very-large-scale integration (VLSI) architecture for the proposed algorithm is implemented by using TSMC 0.13-um technology. The synthesis results show that the design yields a processing rate of approximately 200 Mpixels/s, which is rapid enough to facilitate Full HD resolution at 30 fps in real time.

Very‐large‐scale integration implementation of the integral pulse frequency modulation model for spectral estimation of heart rate variability

Heart rate variability (HRV) can be used to assess autonomic control activities. Among the HRV analysis methods, the integral pulse frequency modulation (IPFM) model demonstrates the functional mechanism for the cardiac pacemaker that can explain the generation of heartbeats. In this study, the IPFM model was implemented into a low-cost very-large-scale integration (VLSI) chip, and the active spectrum of HRV was then estimated by solving for the nerve-modulation signal in the model based on the compressed sensing (CS) method. The proposed IPFM chip utilised a time-sharing scheme for hardware resource sharing, a look-up table to calculate the sine and cosine operations, and multiplexers to control the data flow. Furthermore, based on the hardware resource sharing scheme, the proposed chip achieved a low-cost and high-speed design. Implemented with TSMC 90 nm CMOS technology, the proposed IPFM core had an operation frequency of 62.5 MHz with only 9.8 K gate counts. The spectrum of HRV could be effectively estimated through the VLSI implementation of IPFM based on CS.

VLSI implementation of anisotropic probabilistic neural network for real-time image scaling

This study proposes an VLSI implementation of anisotropic probabilistic neural network (APNN) for real-time video processing applications. The APNN interpolation method achieves good sharpness enhancement at edge regions and reveals the noise reduction at smooth region. For real-time applications, the APNN interpolation is further implemented with efficient pipelined very-large-scale integration (VLSI) architecture. The VLSI architecture of APNN has a five-layer structure, which is comprised of Euclidian layer, Gaussian layer, weighting layer, summation layer, and division layer. The VLSI implementation outperforms software with the low-loss quality. The experimental results indicate that the performance of VLSI implementation is competent for image interpolation. The presented VLSI implementation of APNN interpolation method can reach $$1920\times 1080$$ at 30 frames per second (FPS) with a reasonable hardware cost.

VLSI design of low‐cost and high‐precision fixed‐point reconfigurable FFT processors

Fast Fourier transform (FFT) plays an important role in digital signal processing systems. In this study, the authors explore the very large-scale integration (VLSI) design of high-precision fixed-point reconfigurable FFT processor. To achieve high accuracy under the limited wordlength, this study analyses the quantisation noise in FFT computation and proposes the mixed use of multiple scaling approaches to compensate the noise. In addition, a statistics-based optimisation scheme is proposed to configure the scaling operations of the cascaded arithmetic blocks at each stage for yielding the most optimised accuracy for a given FFT length. On the basis of this approach, they further present a VLSI implementation of area-efficient and high-precision FFT processor, which can perform power-of-two FFT from 32 to 8192 points. By using the SMIC 0.13 μ m process, the area of the proposed FFT processor is 27 m m 2 with a maximum operating frequency of 400 MHz. When the FFT processor is configured to perform 8192-point FFT at 40 MHz, the signal-to-quantisation-noise ratio is up to 53.28 dB and the power consumption measured by post-layout simulation is 35.7 mW.

Multi-Peak Double-Dwell GPS Weak Signal Acquisition Method and VLSI Implementation for Energy-Constrained Applications

Power consumption of Global Positioning System (GPS) acquisition is a great challenge for energy-constrained applications. In this work, a metric named acquisition mean computation overhead is proposed to measure the energy cost. A novel multi-peak double-dwell (MP/DD) acquisition method for GPS weak signal is proposed. It adopts multi-peak correlation results as candidates in the first acquisition dwell and selects the largest one as the final acquisition result in the second acquisition dwell. Theoretical analysis and numerical simulation are presented in detail. Meanwhile, the very-large-scale integration (VLSI) implementation of coarse- and fine-grained acquisition engines applied to the proposed method is done. The detection probability and acquisition mean computation overhead are simulated using the Monte-Carlo method, and its mean acquisition power is tested with an actual chip. We fabricated the GPS signal acquisition engine with a 40 nm complementary metal oxide semiconductor (CMOS) process. The simulation results demonstrate that detection probability is promoted from 18% to 67% when signal power is equal to 23 dB/Hz. The acquisition mean computation overhead is reduced greatly by 64%. Measurement results show that the energy consumption of this design is only 21.5% of the conventional double-dwell/maximum (DD/MAX) method.

Hardware/Software Co-Design and VLSI Implementation for the Intelligent Surveillance System

In this paper, we present a hardware design for the intelligent surveillance system. We have developed a complete system-level solution on algorithm level, and then algorithm has been implemented in very-large-scale integration (VLSI). The behavior of the moving objects is evaluated using adaptive search method. We propose the method to track the moving people in successive frames by object boundary box and velocity without color cues or appearance model. Even though people are interacting with each other or the occlusion is occurring due to other foreground objects, still the proposed algorithm can perform well in such situations. Furthermore, we consider the distance of object from camera for an adaptive search range to deal with the people movement issue. Although foreground is similar to the background in some conditions, the proposed algorithm can still detect the object well. We also propose an embedded data compression technique, which does not only reduce the computational complexity, but also achieves high compression rate. The overall system is developed in a platform-based system-on-a-programmable-chip for demonstration of result. In VLSI implementation results, the logical gate count is 139.890 K and the throughput of foreground detection is 6403 K pixels/s.

VLSI Implementation of a Cost-Efficient Micro Control Unit With an Asymmetric Encryption for Wireless Body Sensor Networks

This paper presents a very large-scale integration (VLSI) circuit design of a micro control unit (MCU) for wireless body sensor networks (WBSNs) in cost-intention. The proposed MCU design consists of an asynchronous interface, a multisensor controller, a register bank, a hardware-shared filter, a lossless compressor, an encryption encoder, an error correct coding (ECC) circuit, a universal asynchronous receiver/transmitter interface, a power management, and a QRS complex detector. A hardware-sharing technique was added to reduce the silicon area of a hardware-shared filter and provided functions in terms of high-pass, low-pass, and band-pass filters according to the uses of various body signals. The QRS complex detector was designed for calculating QRS information of the ECG signals. In addition, the QRS information is helpful to obtain the heart beats. The lossless compressor consists of an adaptive trending predictor and an extensible hybrid entropy encoder, which provides various methods to compress the different characteristics of body signals adaptively. Furthermore, an encryption encoder based on an asymmetric cryptography technique was designed to protect the private physical information during wireless transmission. The proposed MCU design in this paper contained 7.61k gate counts and consumed 1.33 mW when operating at 200 MHz by using a 90-nm CMOS process. Compared with previous designs, this paper has the benefits of increasing the average compression rate by over 12% in ECG signal, providing body signals analysis, and enhancing security of the WBSNs.