VHSIC Hardware Description Language Research Articles

An Automatic Design Framework for Real-Time Power System Simulators Supporting Smart Grid Applications

Smart grid technology is the next step to the evolution of classical power grids, providing robustness, reliability, and security throughout the network, enabling real-time management and control. To achieve these goals, distributed computing (microgrid concept) and intelligent control algorithms, tailored to the nature and needs of the network under study, are necessary. To deal with the vast diversity of power grids, being able to capture the dynamics of any given network, and create tools for network analysis, apparatus testing, and power grid management, an automatic design framework for real-time power system simulators is needed. In this article, a prototype of this approach is presented, employing Field Programmable Gate Array (FPGA) platforms due to their reconfigurability that enables low-power, low-latency, and high-performance designs, as a first attempt towards an open source platform, compatible with the majority of hardware design suites. It comprises two major parts: (i) a user-oriented section, built in Matlab/Simulink; and (ii) a hardware-oriented section, written in Matlab and Very High Speed Integrated Circuit (VHSIC)-Hardware Description Language (VHDL) code. To verify its functionality, two test power networks were given in a schematic format, analyzed through Matlab code and turned into dedicated hardware simulators with the aid of the VHDL template. Then, simulation results from Simulink and the prototype were compared for error estimation. The results show the prototype’s successful implementation with minimal resources utilization, high performance and low latency in the order of nanoseconds in Xilinx 6- and 7-series FPGAs, therefore proving its modularity and efficient use in many different scenarios, meeting low-latency/real-time requirements while enabling further smart grid research.

Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA

Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM® v9.0) and a real power converter.

IOT Based Water Quality Monitoring System

Since water pollution is increasing globally so the implementation of water quality monitoring is effective and efficient with increasing the development of wireless sensor network (WSN) technology in the internet of things (IoT) environment. Water quality monitoring is remotely monitoring by real-time data acquisition, transmission, and processing. This paper presents a reconfigurable sensor interface device for monitoring water quality systems with an IoT environment for the developing smart water quality monitoring system (SWQM). We are using field programmable array (FPGA) design board, sensors, Zigbee based wireless communication module, and personal computer. The FPGA board is the core component of the developing system and it is programmed with VHDL (very high speed integrated circuit hardware description language) with using Quartus – II software and Q sys tool by using C language. We are considering the six parameters of water data like water pH, water level, turbidity, humidity, carbon dioxide (CO2) on the surface of water and water temperature in parallel real-time bases with high speed from multiple different sensors nodes.

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size.

Electronic Abacus (e-Abacus) using FPGA Altera DE2 Board

The development of electronic abacus using Altera DE2 115, is to integrate the use of abacus along with electronic devices which offer better visualisation of the abacus operations. The main focus of this technology is to assist the primary school students in validating a fundamental arithmetic operation. The electronic abacus is developed by integrating an abacus, abacus decoder module and field programming gate array (FPGA) based processor. DE2 115 is chosen as the development module and very high-speed integrated circuit hardware description language (VHDL) as a main programming language. The arithmetic algorithm developed for the electronic abacus is limited to the computational of whole numbers only, involving the basic arithmetic operation of additional, subtraction, multiplication and division. This electronic abacus comes with two operational modes, display and arithmetic mode. In the display mode, the abacus beads position at column one until column seven is displayed as numerical representation on the liquid crystal display (LCD) screen. A computation of arithmetic operations with less than three operators is available in the arithmetic mode with the capability of displaying the negative numerical and infinite value. From the simulation conducted in Quartus II, the implementation of the algorithm in FPGA utilise 4% from the total logical element allowed and consume approximately 143.4 mW of power. As a conclusion, this enhanced ancient apparatus hopefully will contribute to the development of more lively and interesting teaching approach.

Frequency Scaling Based Power Efficient Current Source Design on FPGA

Power deficiency is one of the major problems that the whole world is facing now. This is happening because of the immense increase in the world’s population and the global increase of industrialization. So in order to minimize the consumption of power, an energy efficient current source is designed with the help of Field Programmable Gate Array (FPGA). This work gives light on how the power variation takes place in a current source with an increase in frequency value. In this research work, the current source is implemented on 28 nanometers (nm) Airtx-7 FPGA. The work is demonstrated on Xilinx 14.1 ISE simulator. VHSIC Hardware Description Language (VHDL) is used for writing the code of current source. The frequency of current source with Airtx-7 FPGA is increased from 100MHz to 5GHz. It is analyzed that the total power consumption is less as the value of frequency is low. So it is always advisable to operate the device at a lower frequency range in order to save more energy.

Implementation of Word Level Parallel Processing Unfolding Algorithm using VHDL

Aim of this paper is to apply the unfolding algorithm to FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filter and compare with original filter and parallel processing filters architecture. FIR filter and IIR filter are implemented by using VHDL (Very High Speed Integrated Circuit Hardware Description Language).In this paper, 2-parallel processing and 3-parallel processing of FIR and IIR filter are implemented and FIR and IIR filter are also implemented with unfolding factor 2 and unfolding factor 3 using VHDL. The simulation is done on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3. Implemented design works on 1200 KHz clock whereas parallel inputs are generated on 3600 KHz clock. The proposed technique reduces the critical path delay in comparison with existing literature. Also, the experimental result shows that the speed for 3-unfolded IIR filter is more than 3-parallel IIR filter.

Design for the system of high‐speed data transmission and data pre‐processing for synthetic aperture radar imaging based on the system‐on‐a‐programmable‐chip

For the chirp scaling algorithm of synthetic aperture radar imaging, an efficient transmission of a large volume of data is indispensable. Prior to imaging, there is a requirement for appropriate pre-processing of the echo signal by digital down conversion (DDC). The DDC module has to remove the carrier, having an appropriate filtering processing and down-sampling processing. No matter what imaging mode is chosen, such as the stripmap mode, spotlight mode, and sliding spotlight, the needs of the whole imaging system are matched by setting a series of configurations about this pre-processing module and this transmission module. The system-on-a-programmable-chip constituted by the Advanced RISC Machine and field programmable gate array (FPGA) is the perfect experimental platform to test the performance of this system. Some of the algorithms, which are more feasible for this specific project for pre-processing in Maltab, were transplanted to FPGA using the VHSIC Hardware Description Language for functional verification. Finally, the processing results in Matlab were compared with this system to find the difference. At the same time, the time that elapsed from the 2 GB original data entering the system to the time the processed results were completely returned to the PC was also counted.

An Automatic AW-SOM VHDL IP-core Generator

In this paper, the authors present a MATLAB IP generator for hardware accelerators of All-Winner Self-Organizing Maps (AW-SOM). AW-SOM is a modified version of Kohonen’s Self Organizing Maps (SOM) algorithm, which is one of the most used Machine Learning algorithms for data clustering, and vector quantization. The architecture of the AW-SOM method is meant for hardware implementations, and its main feature is a processing speed almost independent to the number of neurons since each of them is processed in a parallel way; the parallelization can be easily exploited by hardware custom hardware designs. The IP generator is built-in MATLAB and provides the user with the possibility to design a custom and efficient hardware accelerator. Several settings can be set such as the number of features and the number of neurons. The target language is the VHSIC Hardware Description Language (VHDL). The generated IP cores can be used for the training of the model and a built-in function of the software can also check the clustering performances using its inference capabilities. The accelerators produced by the software have been also characterized in terms of max frequency, hardware resources, and power consumption. The authors performed the hardware implementations on a XILINX Virtex 7 xc7vx690t FPGA.

AES Modes of Operation

Cryptography is the science of secret codes. Previously we used DES algorithms in order to secure but cannot encrypt completely. Thus, we referred AES Algorithms to create a ciphertext in encryption and is given as an input in decryption. In present scenario, everyone sharing their data in online using internet alsoonline transactions like e-banking for money transfers, in shopping malls, restaurants, and many more. While transferring a huge amount or any confidential data there are many chances to hack the data.There are different modes of operations used in AES in accordance with the efficiency to blur the data. The design has been done in VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and simulated and synthesized using Xilinx.

An efficient and adaptable multimedia system for converting PAL to VGA in real-time video processing

Real-time video processing has found its range of applications from defense to consumer electronics for surveillance, video conferencing, etc. With the advent of Field Programmable Gate Arrays (FPGAs), flexible real-time video processing systems which can meet hard real-time constraints are easily realized with short development time. Most of the existing solutions have high utilization of system resources and are not quite flexible with many applications. Here we propose a hardware–software co-design for an FPGA-based real-time video processing system to convert video in standard Phase Alternating Line (PAL) 576i format to standard video of Video Graphics Array (VGA)/Super Video Graphics Array (SVGA) format with little utilization of resources. Switching between multiple video streams, character/text overlaying, and skin color detection are also incorporated with the system. The system is also adaptable for rugged applications. VHSIC Hardware Description Language (VHDL) codes for the architecture were synthesized using Altera Quartus II and targeted for Altera Stratix I FPGA. Results achieved confirm that the proposed system performs efficient conversion with very less resource utilization compared to the existing solutions. Since the proposed system is also flexible, many other applications can be incorporated in the future.

Selective branch prediction schemes based on FPGA MIPS processor for educational purposes

Processor performance is measured by amount of ILP (Instruction Level Parallelism) represented by its design. this parallelism is limited by the execution of conditional branch instructions which may break the flow of the program execution. To overcome this problem, several ways were suggested in order to predict both the direction of instructions execution and the address of the instruction to be executed next. In this paper, a design for a dynamic branch predictor was implemented in VHDL (VHSIC Hardware Description Language) then it was integrated with FPGA (Field Programmable Gate Arrays) MIPS (Microprocessor without Interlocked Pipelined Stages) processor and its ability to increase prediction accuracy and MIPS processor performance was approved. This predictor combines gshare and bimodal branch prediction techniques by dividing the PHT (Pattern History Table) into two branch streams corresponding to taken and not-taken states. This combined branch predictor was synthesized using the XILINX ISE (Integrated Software Environment) Design Suite 14.7 tool.

Analysis and Synthesis of Elevator Controller Based On VHSIC Hardware Description Language

Analysis and Synthesis of Elevator Controller Based On VHSIC Hardware Description Language

Multi-purpose trigger system for medium particle detector devices

Abstract We report on an architecture of a multi-purpose trigger system based on inexpensive and off-the-shelf modules, with logic implemented in three levels, that can be used in a variety of small/medium systems just by writing a few registers using the accompanying software. The developed trigger algorithms are described in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and implemented using a Xilinx XC6LX45-2 FPGA. In its present implementation, for the sake of simplicity, communication with the external world is done using the Serial Peripheral Interface (SPI), which allows easy connection to a Raspberry Pi2 running Linux. The Raspberry software was written in C++ and enables configuring and checking of the underlying FPGA and retrieving the monitoring data. The system has been used, with success, in several applications, from lab setup to industrial and pre-clinical environments showing its versatility and robustness.

A New CPFSK Demodulation Approach for Software Defined Radio

This paper proposes a new coherent Frequency-Shift Keying (FSK) demodulation technique for software defined radio platform, based on a new Digital Phase Locked Loop (DPLL) architecture. The proposed DPLL addresses the frequency dependence on classic DPLL architectures found in the literature. In classical approaches, the loop filter constants are dependent on the frequency level of the FSK transmitted symbols. The proposed approach applies a simpler feedback loop, with a single integrator and a phase detector architecture based on the small-angle approximation [Formula: see text], which resulted in a DPLL totally independent of frequency. The proposed demodulator has been implemented in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) and evaluated for continuous-phase frequency shift keying (CPFSK) and Gaussian minimum shift keying (GMSK) signals. For CPFSK signals, the demodulator has been evaluated for 2, 4 and 8 frequency levels, with modulation indexes [Formula: see text], [Formula: see text] and [Formula: see text], respectively. For evaluation of GMSK signals, several Gaussian filter bandwidths were considered. In addition, a brief analysis for 2-CPFSK and GMSK is presented over multipath and carrier frequency offset. Results show that the proposed method presents a significantly reduced bit error rate when compared to other coherent methods presented in the literature.

Research and Implementation of Natural Sampling SPWM Digital Method for Three-Level Inverter of Photovoltaic Power Generation System Based on FPGA

The digital method of natural sampling sinusoidal pulse width modulation (SPWM) is studied based on the characteristics of neutral point clamped three-level inverters of Photovoltaic power generation system. Based on field programmable gate array (FPGA), A three-level natural sampling SPWM digital framework is constructed. The digital implementation methods of triangular carrier generation, sinusoidal modulation waveform generation, switching state combination configuration and dead-zone setting are studied. A ultra-realtime comparison calculation method of switching time based on FPGA technology is proposed in this paper. This method avoids complex calculation such as Taylor series expansion and convergence judgment in natural sampling SPWM. Under the same conditions, the harmonic content of the SPWM output waveform using this method is smaller than that of the symmetrical regular sampling method. And the harmonic content is equivalent to that of natural sampling. The digital natural sampling method can further improve the quality of output waveform and the stability of DC bus voltage of three-level inverters. The theoretical research is realized by VHDL (Very High Speed Integrated Circuit Hardware Description Language) and FPGA chip. The experimental results prove the correctness and feasibility of the digital method.

Implementation of application specific soft-core architecture for switching converters

Application Specific Processors (ASPs) are used in many areas. In this paper, an application specific soft-core processor for control of switching power converters is designed and implemented. The proposed designed architecture is constructed based on fixed-point arithmetic with minimal functional units. The control algorithm, which is used in this architecture, is Finite-Set Model Predictive Control (FS-MPC). The proposed soft-core processor is coded in VHSIC Hardware Description Language (VHDL) and implemented on Field-Programmable Gate Array (FPGA) platform. This architecture consists of minimum functional unit with only two adders and two multipliers, a control unit and a selection unit. The designed architecture is general and low cost and can be used in any type of converters. In this paper the functionality of the processor is examined by three types of converters namely three-phase inverters, dual transistor forward converter and active front end rectifier. In comparison with other controllers, output results indicate the accuracy of proposed architecture.

Why we should use Min Max DEVS for modeling and simulation of digital circuits

The delay is a very important element in modeling hardware behavior, and is realized in many hardware description languages such as ADLIB-SABLE, Verilog, and VHDL. The state of the art on hardware delay identifies four classes. In the first class, mean values are used as a precise delay element in the simulation; we found it in VHDL (VHSIC (very high speed integrated circuit) Hardware Description Language), where a single value is utilized to characterize the transport delay. In the second class, the delay is represented by an interval min max, meaning that the delay value is precisely unknown and every value in the interval can represent a possible value for the actual delay. In the third class, a delay is expressed in the form of a stochastic distribution. Fuzzy models of delay constitute the last class. In reality, it is very difficult, if not impossible, to obtain a precise value of the delay; there are many reasons for that: temperature, voltage, variation in the manufacturing process, and other environment parameters. The Min Max DEVS formalism allows an efficient design of the min max delay by proposing a definition of the lifetime function based on time interval. Moreover, its simulation semantics allows the simulation of Min Max DEVS models with only one replication, allowing us to conclude whether the min max delay is too large or exact simulations cannot be obtained. In this paper, we propose to highlight the Min Max DEVS formalism through examples from digital circuits, after having recalled its basic definitions and its simulation semantics. Then, we compare the simulation results obtained with those provided by the well-known tool in the field of digital circuits, Verilog, using the same examples.

Maglev Train Signal Processing Architecture Based on Nonlinear Discrete Tracking Differentiator.

In a maglev train levitation system, signal processing plays an important role for the reason that some sensor signals are prone to be corrupted by noise due to the harsh installation and operation environment of sensors and some signals cannot be acquired directly via sensors. Based on these concerns, an architecture based on a new type of nonlinear second-order discrete tracking differentiator is proposed. The function of this signal processing architecture includes filtering signal noise and acquiring needed signals for levitation purposes. The proposed tracking differentiator possesses the advantages of quick convergence, no fluttering, and simple calculation. Tracking differentiator’s frequency characteristics at different parameter values are studied in this paper. The performance of this new type of tracking differentiator is tested in a MATLAB simulation and this tracking-differentiator is implemented in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). In the end, experiments are conducted separately on a test board and a maglev train model. Simulation and experiment results show that the performance of this novel signal processing architecture can fulfill the real system requirement.

Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes

In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.